201 lines
12 KiB
C
201 lines
12 KiB
C
/***********************************************************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
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* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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* applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
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* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
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* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
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* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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*
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* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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* File Name : r_cg_port.h
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* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
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* Device(s) : R5F10268
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* Tool-Chain : CCRL
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* Description : This file implements device driver for PORT module.
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* Creation Date: 2024-05-24
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***********************************************************************************************************************/
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#ifndef PORT_H
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#define PORT_H
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/***********************************************************************************************************************
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Macro definitions (Register bit)
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***********************************************************************************************************************/
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/*
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Port Mode Register (PMm)
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*/
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/* Pmn pin I/O mode selection (PMm7 - PMm0) */
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#define _01_PMn0_NOT_USE (0x01U) /* not use Pn0 as digital I/O */
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#define _01_PMn0_MODE_INPUT (0x01U) /* use Pn0 as input mode */
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#define _00_PMn0_MODE_OUTPUT (0x00U) /* use Pn0 as output mode */
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#define _02_PMn1_NOT_USE (0x02U) /* not use Pn1 as digital I/O */
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#define _02_PMn1_MODE_INPUT (0x02U) /* use Pn1 as input mode */
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#define _00_PMn1_MODE_OUTPUT (0x00U) /* use Pn1 as output mode */
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#define _04_PMn2_NOT_USE (0x04U) /* not use Pn2 as digital I/O */
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#define _04_PMn2_MODE_INPUT (0x04U) /* use Pn2 as input mode */
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#define _00_PMn2_MODE_OUTPUT (0x00U) /* use Pn2 as output mode */
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#define _08_PMn3_NOT_USE (0x08U) /* not use Pn3 as digital I/O */
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#define _08_PMn3_MODE_INPUT (0x08U) /* use Pn3 as input mode */
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#define _00_PMn3_MODE_OUTPUT (0x00U) /* use Pn3 as output mode */
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#define _10_PMn4_NOT_USE (0x10U) /* not use Pn4 as digital I/O */
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#define _10_PMn4_MODE_INPUT (0x10U) /* use Pn4 as input mode */
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#define _00_PMn4_MODE_OUTPUT (0x00U) /* use Pn4 as output mode */
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#define _20_PMn5_NOT_USE (0x20U) /* not use Pn5 as digital I/O */
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#define _20_PMn5_MODE_INPUT (0x20U) /* use Pn5 as input mode */
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#define _00_PMn5_MODE_OUTPUT (0x00U) /* use Pn5 as output mode */
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#define _40_PMn6_NOT_USE (0x40U) /* not use Pn6 as digital I/O */
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#define _40_PMn6_MODE_INPUT (0x40U) /* use Pn6 as input mode */
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#define _00_PMn6_MODE_OUTPUT (0x00U) /* use Pn6 as output mode */
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#define _80_PMn7_NOT_USE (0x80U) /* not use Pn7 as digital I/O */
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#define _80_PMn7_MODE_INPUT (0x80U) /* use Pn7 as input mode */
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#define _00_PMn7_MODE_OUTPUT (0x00U) /* use Pn7 as output mode */
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/*
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Port Register (Pm)
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*/
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/* Pmn pin data (Pm0 to Pm7) */
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#define _00_Pn0_OUTPUT_0 (0x00U) /* Pn0 output 0 */
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#define _01_Pn0_OUTPUT_1 (0x01U) /* Pn0 output 1 */
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#define _00_Pn1_OUTPUT_0 (0x00U) /* Pn1 output 0 */
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#define _02_Pn1_OUTPUT_1 (0x02U) /* Pn1 output 1 */
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#define _00_Pn2_OUTPUT_0 (0x00U) /* Pn2 output 0 */
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#define _04_Pn2_OUTPUT_1 (0x04U) /* Pn2 output 1 */
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#define _00_Pn3_OUTPUT_0 (0x00U) /* Pn3 output 0 */
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#define _08_Pn3_OUTPUT_1 (0x08U) /* Pn3 output 1 */
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#define _00_Pn4_OUTPUT_0 (0x00U) /* Pn4 output 0 */
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#define _10_Pn4_OUTPUT_1 (0x10U) /* Pn4 output 1 */
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#define _00_Pn5_OUTPUT_0 (0x00U) /* Pn5 output 0 */
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#define _20_Pn5_OUTPUT_1 (0x20U) /* Pn5 output 1 */
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#define _00_Pn6_OUTPUT_0 (0x00U) /* Pn6 output 0 */
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#define _40_Pn6_OUTPUT_1 (0x40U) /* Pn6 output 1 */
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#define _00_Pn7_OUTPUT_0 (0x00U) /* Pn7 output 0 */
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#define _80_Pn7_OUTPUT_1 (0x80U) /* Pn7 output 1 */
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/*
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Pull-up Resistor Option Register (PUm)
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*/
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/* Pmn pin on-chip pull-up resistor selection (PUmn) */
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#define _00_PUn0_PULLUP_OFF (0x00U) /* Pn0 pull-up resistor not connected */
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#define _01_PUn0_PULLUP_ON (0x01U) /* Pn0 pull-up resistor connected */
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#define _00_PUn1_PULLUP_OFF (0x00U) /* Pn1 pull-up resistor not connected */
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#define _02_PUn1_PULLUP_ON (0x02U) /* Pn1 pull-up resistor connected */
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#define _00_PUn2_PULLUP_OFF (0x00U) /* Pn2 Pull-up resistor not connected */
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#define _04_PUn2_PULLUP_ON (0x04U) /* Pn2 pull-up resistor connected */
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#define _00_PUn3_PULLUP_OFF (0x00U) /* Pn3 pull-up resistor not connected */
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#define _08_PUn3_PULLUP_ON (0x08U) /* Pn3 pull-up resistor connected */
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#define _00_PUn4_PULLUP_OFF (0x00U) /* Pn4 pull-up resistor not connected */
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#define _10_PUn4_PULLUP_ON (0x10U) /* Pn4 pull-up resistor connected */
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#define _00_PUn5_PULLUP_OFF (0x00U) /* Pn5 pull-up resistor not connected */
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#define _20_PUn5_PULLUP_ON (0x20U) /* Pn5 pull-up resistor connected */
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#define _00_PUn6_PULLUP_OFF (0x00U) /* Pn6 pull-up resistor not connected */
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#define _40_PUn6_PULLUP_ON (0x40U) /* Pn6 pull-up resistor connected */
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#define _00_PUn7_PULLUP_OFF (0x00U) /* Pn7 pull-up resistor not connected */
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#define _80_PUn7_PULLUP_ON (0x80U) /* Pn7 pull-up resistor connected */
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/*
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Port Input Mode Register (PIMm)
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*/
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/* Pmn pin input buffer selection (PIMmn) */
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#define _00_PIMn0_TTL_OFF (0x00U) /* set Pn0 normal input buffer */
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#define _01_PIMn0_TTL_ON (0x01U) /* set Pn0 TTL input buffer */
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#define _00_PIMn1_TTL_OFF (0x00U) /* set Pn1 normal input buffer */
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#define _02_PIMn1_TTL_ON (0x02U) /* set Pn1 TTL input buffer */
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#define _00_PIMn2_TTL_OFF (0x00U) /* set Pn2 normal input buffer */
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#define _04_PIMn2_TTL_ON (0x04U) /* set Pn2 TTL input buffer */
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#define _00_PIMn3_TTL_OFF (0x00U) /* set Pn3 normal input buffer */
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#define _08_PIMn3_TTL_ON (0x08U) /* set Pn3 TTL input buffer */
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#define _00_PIMn4_TTL_OFF (0x00U) /* set Pn4 normal input buffer */
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#define _10_PIMn4_TTL_ON (0x10U) /* set Pn4 TTL input buffer */
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#define _00_PIMn5_TTL_OFF (0x00U) /* set Pn5 normal input buffer */
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#define _20_PIMn5_TTL_ON (0x20U) /* set Pn5 TTL input buffer */
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#define _00_PIMn6_TTL_OFF (0x00U) /* set Pn6 normal input buffer */
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#define _40_PIMn6_TTL_ON (0x40U) /* set Pn6 TTL input buffer */
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#define _00_PIMn7_TTL_OFF (0x00U) /* set Pn7 normal input buffer */
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#define _80_PIMn7_TTL_ON (0x80U) /* set Pn7 TTL input buffer */
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/*
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Port Output Mode Register (POMm)
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*/
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/* Pmn pin output mode selection (POMmn) */
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#define _00_POMn0_NCH_OFF (0x00U) /* set Pn0 output normal mode */
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#define _01_POMn0_NCH_ON (0x01U) /* set Pn0 output N-ch open-drain mode */
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#define _00_POMn1_NCH_OFF (0x00U) /* set Pn1 output normal mode */
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#define _02_POMn1_NCH_ON (0x02U) /* set Pn1 output N-ch open-drain mode */
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#define _00_POMn2_NCH_OFF (0x00U) /* set Pn2 output normal mode */
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#define _04_POMn2_NCH_ON (0x04U) /* set Pn2 output N-ch open-drain mode */
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#define _00_POMn3_NCH_OFF (0x00U) /* set Pn3 output normal mode */
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#define _08_POMn3_NCH_ON (0x08U) /* set Pn3 output N-ch open-drain mode */
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#define _00_POMn4_NCH_OFF (0x00U) /* set Pn4 output normal mode */
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#define _10_POMn4_NCH_ON (0x10U) /* set Pn4 output N-ch open-drain mode */
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#define _00_POMn5_NCH_OFF (0x00U) /* set Pn5 output normal mode */
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#define _20_POMn5_NCH_ON (0x20U) /* set Pn5 output N-ch open-drain mode */
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#define _00_POMn6_NCH_OFF (0x00U) /* set Pn6 output normal mode */
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#define _40_POMn6_NCH_ON (0x40U) /* set Pn6 output N-ch open-drain mode */
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#define _00_POMn7_NCH_OFF (0x00U) /* set Pn7 output normal mode */
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#define _80_POMn7_NCH_ON (0x80U) /* set Pn7 output N-ch open-drain mode */
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/*
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Port Operation Mode Register (PMCm)
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*/
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/* Pmn pin digital input buffer selection (PMCmn) */
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#define _01_PMCn0_NOT_USE (0x01U) /* not use Pn0 digital input */
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#define _00_PMCn0_DI_ON (0x00U) /* enable Pn0 digital input */
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#define _02_PMCn1_NOT_USE (0x02U) /* not use Pn1 digital input */
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#define _00_PMCn1_DI_ON (0x00U) /* enable Pn1 digital input */
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#define _04_PMCn2_NOT_USE (0x04U) /* not use Pn2 digital input */
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#define _00_PMCn2_DI_ON (0x00U) /* enable Pn2 digital input */
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#define _08_PMCn3_NOT_USE (0x08U) /* not use Pn3 digital input */
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#define _00_PMCn3_DI_ON (0x00U) /* enable Pn3 digital input */
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#define _10_PMCn4_NOT_USE (0x10U) /* not use Pn4 digital input */
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#define _00_PMCn4_DI_ON (0x00U) /* enable Pn4 digital input */
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#define _20_PMCn5_NOT_USE (0x20U) /* not use Pn5 digital input */
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#define _00_PMCn5_DI_ON (0x00U) /* enable Pn5 digital input */
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#define _40_PMCn6_NOT_USE (0x40U) /* not use Pn6 digital input */
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#define _00_PMCn6_DI_ON (0x00U) /* enable Pn6 digital input */
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#define _80_PMCn7_NOT_USE (0x80U) /* not use Pn7 digital input */
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#define _00_PMCn7_DI_ON (0x00U) /* enable Pn7 digital input */
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/*
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AD port configuration register (ADPC)
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*/
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/* Analog input/digital input switching (ADPC3 - ADPC0) */
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#define _00_ADPC_DI_OFF (0x00U) /* use P20 - P23 as analog input */
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#define _04_ADPC_DI_ON (0x04U) /* use P23 as digital input */
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#define _03_ADPC_DI_ON (0x03U) /* use P22 - P23 as digital input */
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#define _02_ADPC_DI_ON (0x02U) /* use P21 - P23 as digital input */
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#define _01_ADPC_DI_ON (0x01U) /* use P20 - P23 as digital input */
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/***********************************************************************************************************************
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Macro definitions
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***********************************************************************************************************************/
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#define _E0_PM1_DEFAULT (0xE0U) /* PM1 default value */
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#define _F0_PM2_DEFAULT (0xF0U) /* PM2 default value */
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#define _F8_PM4_DEFAULT (0xF8U) /* PM4 default value */
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#define _FC_PM6_DEFAULT (0xFCU) /* PM6 default value */
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#define _E0_PMC1_DEFAULT (0xE0U) /* PMC1 default value */
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#define _F9_PMC4_DEFAULT (0xF9U) /* PMC4 default value */
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/***********************************************************************************************************************
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Typedef definitions
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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Global functions
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***********************************************************************************************************************/
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void R_PORT_Create(void);
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/* Start user code for function. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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#endif
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