180 lines
9.3 KiB
C
180 lines
9.3 KiB
C
/***********************************************************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
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* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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* applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
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* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
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* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
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* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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*
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* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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* File Name : r_cg_adc.h
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* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
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* Device(s) : R5F10268
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* Tool-Chain : CCRL
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* Description : This file implements device driver for ADC module.
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* Creation Date: 2023-10-05
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***********************************************************************************************************************/
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#ifndef ADC_H
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#define ADC_H
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/***********************************************************************************************************************
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Macro definitions (Register bit)
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***********************************************************************************************************************/
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/*
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Peripheral enable register 0 (PER0)
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*/
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/* Control of AD converter input clock (ADCEN) */
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#define _00_AD_CLOCK_STOP (0x00U) /* stop supply of input clock */
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#define _20_AD_CLOCK_SUPPLY (0x20U) /* supply input clock */
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/*
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AD converter mode register 0 (ADM0)
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*/
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#define _00_AD_ADM0_INITIALVALUE (0x00U)
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/* AD conversion operation control (ADCS) */
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#define _80_AD_CONVERSION_ENABLE (0x80U) /* enable AD conversion operation control */
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#define _00_AD_CONVERSION_DISABLE (0x00U) /* disable AD conversion operation control */
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/* Specification of AD conversion operation mode (ADMD) */
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#define _00_AD_OPERMODE_SELECT (0x00U) /* select operation mode */
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#define _40_AD_OPERMODE_SCAN (0x40U) /* scan operation mode */
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/* AD conversion clock selection (FR2 - FR0) */
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#define _00_AD_CONVERSION_CLOCK_64 (0x00U) /* fCLK/64 */
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#define _08_AD_CONVERSION_CLOCK_32 (0x08U) /* fCLK/32 */
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#define _10_AD_CONVERSION_CLOCK_16 (0x10U) /* fCLK/16 */
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#define _18_AD_CONVERSION_CLOCK_8 (0x18U) /* fCLK/8 */
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#define _20_AD_CONVERSION_CLOCK_6 (0x20U) /* fCLK/6 */
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#define _28_AD_CONVERSION_CLOCK_5 (0x28U) /* fCLK/5 */
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#define _30_AD_CONVERSION_CLOCK_4 (0x30U) /* fCLK/4 */
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#define _38_AD_CONVERSION_CLOCK_2 (0x38U) /* fCLK/2 */
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/* Specification AD conversion time mode (LV1, LV0) */
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#define _00_AD_TIME_MODE_NORMAL_1 (0x00U) /* normal 1 mode */
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#define _02_AD_TIME_MODE_NORMAL_2 (0x02U) /* normal 2 mode */
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#define _04_AD_TIME_MODE_LOWVOLTAGE_1 (0x04U) /* low-voltage 1 mode */
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#define _06_AD_TIME_MODE_LOWVOLTAGE_2 (0x06U) /* low-voltage 2 mode */
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/* AD comparator operation control (ADCE) */
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#define _01_AD_COMPARATOR_ENABLE (0x01U) /* enable comparator operation control */
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#define _00_AD_COMPARATOR_DISABLE (0x00U) /* disable comparator operation control */
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/*
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Analog input channel specification register (ADS)
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*/
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/* Specification of analog input channel (ADISS, ADS4 - ADS0) */
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/* Select mode */
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#define _00_AD_INPUT_CHANNEL_0 (0x00U) /* ANI0 */
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#define _01_AD_INPUT_CHANNEL_1 (0x01U) /* ANI1 */
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#define _02_AD_INPUT_CHANNEL_2 (0x02U) /* ANI2 */
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#define _03_AD_INPUT_CHANNEL_3 (0x03U) /* ANI3 */
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#define _10_AD_INPUT_CHANNEL_16 (0x10U) /* ANI16 */
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#define _11_AD_INPUT_CHANNEL_17 (0x11U) /* ANI17 */
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#define _12_AD_INPUT_CHANNEL_18 (0x12U) /* ANI18 */
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#define _13_AD_INPUT_CHANNEL_19 (0x13U) /* ANI19 */
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#define _14_AD_INPUT_CHANNEL_20 (0x14U) /* ANI20 */
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#define _15_AD_INPUT_CHANNEL_21 (0x15U) /* ANI21 */
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#define _16_AD_INPUT_CHANNEL_22 (0x16U) /* ANI22 */
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#define _80_AD_INPUT_TEMPERSENSOR_0 (0x80U) /* temperature sensor 0 output is used to be the input channel */
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#define _81_AD_INPUT_INTERREFVOLT (0x81U) /* internal reference voltage output is used to be the input channel */
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/* Scan mode */
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#define _00_AD_INPUT_CHANNEL_0_3 (0x00U) /* ANI0 - ANI3 */
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/*
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AD converter mode register 1 (ADM1)
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*/
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/* AD trigger mode selection (ADTMD1, ADTMD0) */
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#define _00_AD_TRIGGER_SOFTWARE (0x00U) /* software trigger mode */
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#define _80_AD_TRIGGER_HARDWARE_NOWAIT (0x80U) /* hardware trigger mode (no wait) */
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#define _C0_AD_TRIGGER_HARDWARE_WAIT (0xC0U) /* hardware trigger mode (wait) */
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/* AD convertion mode selection (ADSCM) */
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#define _00_AD_CONVMODE_CONSELECT (0x00U) /* continuous convertion mode */
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#define _20_AD_CONVMODE_ONESELECT (0x20U) /* oneshot convertion mode */
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/* Trigger signal selection (ADTRS1, ADTRS0) */
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#define _00_AD_TRIGGER_INTTM01 (0x00U) /* INTTM01 */
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#define _03_AD_TRIGGER_INTIT (0x03U) /* INTIT */
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/*
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AD converter mode register 2 (ADM2)
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*/
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/* AD VREF(+) selection (ADREFP1, ADREFP0) */
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#define _00_AD_POSITIVE_VDD (0x00U) /* use VDD as VREF(+) */
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#define _40_AD_POSITIVE_AVREFP (0x40U) /* use AVREFP as VREF(+) */
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#define _80_AD_POSITIVE_INTERVOLT (0x80U) /* use internal voltage as VREF(+) */
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/* AD VREF(-) selection (ADREFM) */
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#define _00_AD_NEGATIVE_VSS (0x00U) /* use VSS as VREF(-) */
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#define _20_AD_NEGATIVE_AVREFM (0x20U) /* use AVREFM as VREF(-) */
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/* AD conversion result upper/lower bound value selection (ADRCK) */
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#define _00_AD_AREA_MODE_1 (0x00U) /* generates INTAD when ADLL <= ADCRH <= ADUL */
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#define _08_AD_AREA_MODE_2_3 (0x08U) /* generates INTAD when ADUL < ADCRH or ADLL > ADCRH */
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/* AD wakeup function selection (AWC) */
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#define _00_AD_WAKEUP_OFF (0x00U) /* stop wakeup function */
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#define _04_AD_WAKEUP_ON (0x04U) /* use wakeup function */
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/* AD resolution selection (ADTYP) */
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#define _00_AD_RESOLUTION_10BIT (0x00U) /* 10 bits */
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#define _01_AD_RESOLUTION_8BIT (0x01U) /* 8 bits */
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/*
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AD test function register (ADTES)
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*/
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/* AD test mode signal (ADTES1, ADTES0) */
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#define _00_AD_NORMAL_INPUT (0x00U) /* normal mode */
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#define _02_AD_TEST_AVREFM (0x02U) /* use AVREFM as test signal */
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#define _03_AD_TEST_AVREFP (0x03U) /* use AVREFP as test signal */
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/*
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AD port configuration register (ADPC)
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*/
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/* Analog input/digital input switching (ADPC3 - ADPC0) */
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#define _00_AD_ADPC_4ANALOG (0x00U) /* ANI0 - ANI3 */
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#define _04_AD_ADPC_3ANALOG (0x04U) /* ANI0 - ANI2 */
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#define _03_AD_ADPC_2ANALOG (0x03U) /* ANI0 - ANI1 */
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#define _02_AD_ADPC_1ANALOG (0x02U) /* ANI0 */
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#define _01_AD_ADPC_0ANALOG (0x01U) /* ANI0 - ANI4 (all digital) */
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/***********************************************************************************************************************
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Macro definitions
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***********************************************************************************************************************/
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/* Upper bound (ADUL) value */
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#define _FF_AD_ADUL_VALUE (0xFFU)
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/* Upper bound (ADLL) value */
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#define _00_AD_ADLL_VALUE (0x00U)
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/***********************************************************************************************************************
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Typedef definitions
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***********************************************************************************************************************/
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typedef enum
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{
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ADCHANNEL0, ADCHANNEL1, ADCHANNEL2, ADCHANNEL3, ADCHANNEL16 = 16U,
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ADCHANNEL17, ADCHANNEL18, ADCHANNEL19, ADCHANNEL20, ADCHANNEL21,
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ADCHANNEL22, ADTEMPERSENSOR0 = 128U, ADINTERREFVOLT
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} ad_channel_t;
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typedef enum
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{
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ADNORMALINPUT,
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ADAVREFM = 2U,
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ADAVREFP
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} test_channel_t;
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/***********************************************************************************************************************
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Global functions
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***********************************************************************************************************************/
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void R_ADC_Create(void);
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void R_ADC_Start(void);
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void R_ADC_Stop(void);
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void R_ADC_Set_OperationOn(void);
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void R_ADC_Set_OperationOff(void);
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void R_ADC_Get_Result(uint16_t * const buffer);
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/* Start user code for function. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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#endif
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