SBC调试OK
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5
cva_bootloader_m0128/.vscode/settings.json
vendored
5
cva_bootloader_m0128/.vscode/settings.json
vendored
@ -16,5 +16,8 @@
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"command": "extension.execute",
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"command": "extension.execute",
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"priority": 4
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"priority": 4
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||||||
}
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}
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||||||
]
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],
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"files.associations": {
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||||||
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"segger_rtt.h": "c"
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}
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||||||
}
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}
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@ -362,6 +362,7 @@
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<state>$PROJ_DIR$\SDK\platform\devices\CVM012x</state>
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<state>$PROJ_DIR$\SDK\platform\devices\CVM012x</state>
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<state>$PROJ_DIR$\src\private_driver</state>
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<state>$PROJ_DIR$\src\private_driver</state>
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<state>$PROJ_DIR$\src\RTT</state>
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<state>$PROJ_DIR$\src\RTT</state>
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<state>$PROJ_DIR$\src\TLE9461</state>
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</option>
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</option>
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<option>
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<option>
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<name>CCStdIncCheck</name>
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<name>CCStdIncCheck</name>
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@ -1905,6 +1906,30 @@
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<name>$PROJ_DIR$\src\RTT\SEGGER_RTT_Syscalls_GCC.c</name>
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<name>$PROJ_DIR$\src\RTT\SEGGER_RTT_Syscalls_GCC.c</name>
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</file>
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</file>
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</group>
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</group>
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<group>
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<name>TLE9461</name>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\SBC_TLE94x1.h</name>
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</file>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\TLE94x1.c</name>
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</file>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\TLE94x1.h</name>
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</file>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\TLE94x1_DEFINES.h</name>
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</file>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\TLE94x1_ISR.h</name>
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</file>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.c</name>
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</file>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.h</name>
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</file>
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</group>
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<file>
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<file>
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<name>$PROJ_DIR$\src\main.c</name>
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<name>$PROJ_DIR$\src\main.c</name>
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</file>
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</file>
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@ -2175,6 +2175,30 @@
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<name>$PROJ_DIR$\src\RTT\SEGGER_RTT_Syscalls_GCC.c</name>
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<name>$PROJ_DIR$\src\RTT\SEGGER_RTT_Syscalls_GCC.c</name>
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</file>
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</file>
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</group>
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</group>
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<group>
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||||||
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<name>TLE9461</name>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\SBC_TLE94x1.h</name>
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</file>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\TLE94x1.c</name>
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</file>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\TLE94x1.h</name>
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</file>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\TLE94x1_DEFINES.h</name>
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</file>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\TLE94x1_ISR.h</name>
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</file>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.c</name>
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</file>
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<file>
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<name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.h</name>
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</file>
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</group>
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<file>
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<file>
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<name>$PROJ_DIR$\src\main.c</name>
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<name>$PROJ_DIR$\src\main.c</name>
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</file>
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</file>
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@ -16,13 +16,13 @@
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<MemConfigValue>E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0128.ddf</MemConfigValue>
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<MemConfigValue>E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0128.ddf</MemConfigValue>
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</PlDriver>
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</PlDriver>
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<JLinkDriver>
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<JLinkDriver>
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<LeaveTargetRunning>_ 0</LeaveTargetRunning>
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<CStepIntDis>_ 0</CStepIntDis>
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<jlinkResetStyle>12</jlinkResetStyle>
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<jlinkResetStyle>12</jlinkResetStyle>
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<jlinkResetStrategy>0</jlinkResetStrategy>
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<jlinkResetStrategy>0</jlinkResetStrategy>
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<TraceBufferSize>0x10000</TraceBufferSize>
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<TraceBufferSize>0x10000</TraceBufferSize>
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<TraceStallIfFIFOFull>0x0</TraceStallIfFIFOFull>
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<TraceStallIfFIFOFull>0x0</TraceStallIfFIFOFull>
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<TracePortSize>0x0</TracePortSize>
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<TracePortSize>0x0</TracePortSize>
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<LeaveTargetRunning>_ 0</LeaveTargetRunning>
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<CStepIntDis>_ 0</CStepIntDis>
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</JLinkDriver>
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</JLinkDriver>
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<ArmDriver>
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<ArmDriver>
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<EnableCache>0</EnableCache>
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<EnableCache>0</EnableCache>
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@ -65,17 +65,16 @@
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<Enabled>0</Enabled>
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<Enabled>0</Enabled>
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<ShowSource>0</ShowSource>
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<ShowSource>0</ShowSource>
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</Trace2>
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</Trace2>
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<DisassembleMode>
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<mode>0</mode>
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</DisassembleMode>
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<Breakpoints2>
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<Bp0>_ 1 "EMUL_CODE" "{$PROJ_DIR$\src\main.c}.652.13" 0 0 1 "" 0 "" 0</Bp0>
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<Count>1</Count>
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</Breakpoints2>
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<TermIOLog>
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<TermIOLog>
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<LoggingEnabled>_ 0</LoggingEnabled>
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<LoggingEnabled>_ 0</LoggingEnabled>
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<LogFile>_ ""</LogFile>
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<LogFile>_ ""</LogFile>
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</TermIOLog>
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</TermIOLog>
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<DisassembleMode>
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<mode>0</mode>
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</DisassembleMode>
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<Breakpoints2>
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<Count>0</Count>
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</Breakpoints2>
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<Aliases>
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<Aliases>
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<Count>0</Count>
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<Count>0</Count>
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||||||
<SuppressDialog>0</SuppressDialog>
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<SuppressDialog>0</SuppressDialog>
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File diff suppressed because one or more lines are too long
101
cva_bootloader_m0128/src/TLE9461/SBC_TLE94x1.h
Normal file
101
cva_bootloader_m0128/src/TLE9461/SBC_TLE94x1.h
Normal file
@ -0,0 +1,101 @@
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/**
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* @cond
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***********************************************************************************************************************
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*
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* Copyright (c) 2018, Infineon Technologies AG
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
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* following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
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* following disclaimer in the documentation and/or other materials provided with the distribution.
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*
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* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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**********************************************************************************************************************/
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#ifndef SBC_TLE94X1_H
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#define SBC_TLE94X1_H
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/* XML Version 0.0.6 */
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#define SBC_XML_VERSION (00006)
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#define CTRL_BUS_CTRL_0 (0x3) /*decimal 3*/
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#define CTRL_BUS_CTRL_3 (0x0) /*decimal 0*/
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#define CTRL_GPIO_CTRL (0x4) /*decimal 4*/
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#define CTRL_HW_CTRL_0 (0x40) /*decimal 64*/
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#define CTRL_HW_CTRL_1 (0x0) /*decimal 0*/
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#define CTRL_HW_CTRL_2 (0x40) /*decimal 64*/
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#define CTRL_HW_CTRL_3 (0x1) /*decimal 1*/
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#define CTRL_M_S_CTRL (0x13) /*decimal 19*/
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#define CTRL_PWM_CTRL (0x0) /*decimal 0*/
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#define CTRL_PWM_FREQ_CTRL (0x0) /*decimal 0*/
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#define CTRL_SWK_BTL0_CTRL (0x50) /*decimal 80*/
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#define CTRL_SWK_CAN_FD_CTRL (0x0) /*decimal 0*/
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#define CTRL_SWK_CDR_CTRL2 (0x1) /*decimal 1*/
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#define CTRL_SWK_CDR_LIMIT_HIGH_CTRL (0x54) /*decimal 84*/
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#define CTRL_SWK_CDR_LIMIT_LOW_CTRL (0x4C) /*decimal 76*/
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#define CTRL_SWK_DATA_H_CTRL 0x00000000
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#define CTRL_SWK_DATA_L_CTRL 0x00000000
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#define CTRL_SWK_DLC_CTRL (0x0) /*decimal 0*/
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#define CTRL_SWK_ID0_CTRL (0x0) /*decimal 0*/
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#define CTRL_SWK_IDx_CTRL 0x00000000
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#define CTRL_SWK_MASK_IDx_CTRL 0x00000000
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#define CTRL_TIMER_CTRL (0x0) /*decimal 0*/
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#define CTRL_WD_CTRL (0x15) /*decimal 21*/
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#define CTRL_WK_CTRL_0 (0x0) /*decimal 0*/
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#define CTRL_WK_CTRL_1 (0x0) /*decimal 0*/
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#define CTRL_WK_PUPD_CTRL (0x0) /*decimal 0*/
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#define LED_Math_extendedID (0x1) /*decimal 1*/
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#define LED_Math_extendedIDMsk (0x1) /*decimal 1*/
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#define MATH_Baudrate (0x2) /*decimal 2*/
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#define MATH_CDR_FrequencyMHz (0x28) /*decimal 40*/
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#define MATH_DoubleCDRFreq (0x0) /*decimal 0*/
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#define MATH_EN_PN (0x1) /*decimal 1*/
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#define MATH_PWM_DC (0.0)
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#endif /* SBC_TLE94X1_H */
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233
cva_bootloader_m0128/src/TLE9461/TLE9461.icwp
Normal file
233
cva_bootloader_m0128/src/TLE9461/TLE9461.icwp
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@ -0,0 +1,233 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<icwpxml version="2.6.4">
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<checksum>9e8e9087eecb39921ec31dfccce96b2a2efec664bafe2827aea4ddb51cb86761</checksum>
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<XmlFile>TLE94x1_Lib.xml</XmlFile>
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<XmlVersion>V0.0.6</XmlVersion>
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<ActiveElements>
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<CheckBox>
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<define>CTRL.HW_CTRL_2[4]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</CheckBox>
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<CheckBox>
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<define>CTRL.HW_CTRL_1[4]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</CheckBox>
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<ComboBox>
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<define>CTRL.WK_PUPD_CTRL[7:6]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</ComboBox>
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<ComboBox>
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<define>CTRL.PWM_FREQ_CTRL[1:0]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</ComboBox>
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<DoubleSpinBox>
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<define>MATH.PWM_DC</define>
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<value>0</value>
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<dispValue>0.0</dispValue>
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</DoubleSpinBox>
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<CheckBox>
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<define>CTRL.WK_CTRL_1[7]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</CheckBox>
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<CheckBox>
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<define>CTRL.HW_CTRL_0[0]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</CheckBox>
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<CheckBox>
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<define>CTRL.HW_CTRL_0[5]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</CheckBox>
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<CheckBox>
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<define>CTRL.BUS_CTRL_3[4]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</CheckBox>
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<ComboBox>
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<define>CTRL.WK_PUPD_CTRL[1:0]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</ComboBox>
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<CheckBox>
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<define>CTRL.WK_CTRL_0[6]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</CheckBox>
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<ComboBox>
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<define>CTRL.TIMER_CTRL[3:0]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</ComboBox>
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<ComboBox>
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<define>CTRL.TIMER_CTRL[6:4]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</ComboBox>
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<CheckBox>
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<define>CTRL.HW_CTRL_1[5]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</CheckBox>
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<CheckBox>
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<define>CTRL.HW_CTRL_3[2]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</CheckBox>
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<ButtonGroup>
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<define>CTRL.WD_CTRL[5]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</ButtonGroup>
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<CheckBox>
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<define>CTRL.HW_CTRL_0[2]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</CheckBox>
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<ComboBox>
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<define>CTRL.HW_CTRL_2[7:5]</define>
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<value>2</value>
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<dispValue>2</dispValue>
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</ComboBox>
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<ComboBox>
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<define>CTRL.HW_CTRL_2[3:2]</define>
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<value>0</value>
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<dispValue>0</dispValue>
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</ComboBox>
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<ComboBox>
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<define>CTRL.SWK_CAN_FD_CTRL[3:1]</define>
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<value>2</value>
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<dispValue>0</dispValue>
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</ComboBox>
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<ComboBox>
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<define>MATH.Baudrate</define>
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<value>2</value>
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||||||
|
<dispValue>2</dispValue>
|
||||||
|
</ComboBox>
|
||||||
|
<CheckBox>
|
||||||
|
<define>CTRL.SWK_ID0_CTRL[0]</define>
|
||||||
|
<value>0</value>
|
||||||
|
<dispValue>0</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<LineEdit>
|
||||||
|
<define>CTRL.SWK_MASK_IDx_CTRL</define>
|
||||||
|
<value>0x00000000</value>
|
||||||
|
<dispValue>0</dispValue>
|
||||||
|
</LineEdit>
|
||||||
|
<ComboBox>
|
||||||
|
<define>CTRL.SWK_DLC_CTRL[3:0]</define>
|
||||||
|
<value>0</value>
|
||||||
|
<dispValue>0</dispValue>
|
||||||
|
</ComboBox>
|
||||||
|
<LineEdit>
|
||||||
|
<define>CTRL.SWK_DATA_H_CTRL</define>
|
||||||
|
<value>0x00000000</value>
|
||||||
|
<dispValue>0x00000000</dispValue>
|
||||||
|
</LineEdit>
|
||||||
|
<LineEdit>
|
||||||
|
<define>CTRL.SWK_DATA_L_CTRL</define>
|
||||||
|
<value>0x00000000</value>
|
||||||
|
<dispValue>0x00000000</dispValue>
|
||||||
|
</LineEdit>
|
||||||
|
<CheckBox>
|
||||||
|
<define>CTRL.HW_CTRL_1[3]</define>
|
||||||
|
<value>0</value>
|
||||||
|
<dispValue>0</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<CheckBox>
|
||||||
|
<define>CTRL.HW_CTRL_2[0]</define>
|
||||||
|
<value>0</value>
|
||||||
|
<dispValue>0</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<ComboBox>
|
||||||
|
<define>CTRL.M_S_CTRL[4:3]</define>
|
||||||
|
<value>2</value>
|
||||||
|
<dispValue>2</dispValue>
|
||||||
|
</ComboBox>
|
||||||
|
<CheckBox>
|
||||||
|
<define>MATH.EN_PN</define>
|
||||||
|
<value>1</value>
|
||||||
|
<dispValue>1</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<ComboBox>
|
||||||
|
<define>CTRL.HW_CTRL_3[1:0]</define>
|
||||||
|
<value>1</value>
|
||||||
|
<dispValue>1</dispValue>
|
||||||
|
</ComboBox>
|
||||||
|
<CheckBox>
|
||||||
|
<define>CTRL.HW_CTRL_0[6]</define>
|
||||||
|
<value>1</value>
|
||||||
|
<dispValue>1</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<CheckBox>
|
||||||
|
<define>CTRL.SWK_CAN_FD_CTRL[0]</define>
|
||||||
|
<value>0</value>
|
||||||
|
<dispValue>0</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<CheckBox>
|
||||||
|
<define>MATH.DoubleCDRFreq</define>
|
||||||
|
<value>0</value>
|
||||||
|
<dispValue>0</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<LineEdit>
|
||||||
|
<define>CTRL.SWK_IDx_CTRL</define>
|
||||||
|
<value>0x00000000</value>
|
||||||
|
<dispValue>0</dispValue>
|
||||||
|
</LineEdit>
|
||||||
|
<ComboBox>
|
||||||
|
<define>CTRL.GPIO_CTRL[2:0]</define>
|
||||||
|
<value>4</value>
|
||||||
|
<dispValue>4</dispValue>
|
||||||
|
</ComboBox>
|
||||||
|
<CheckBox>
|
||||||
|
<define>CTRL.WK_CTRL_1[0]</define>
|
||||||
|
<value>0</value>
|
||||||
|
<dispValue>0</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<CheckBox>
|
||||||
|
<define>CTRL.WK_CTRL_1[5]</define>
|
||||||
|
<value>0</value>
|
||||||
|
<dispValue>0</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<CheckBox>
|
||||||
|
<define>CTRL.WK_CTRL_0[2];CTRL.WD_CTRL[6]</define>
|
||||||
|
<value>1</value>
|
||||||
|
<dispValue>1</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<CheckBox>
|
||||||
|
<define>CTRL.WD_CTRL[4]</define>
|
||||||
|
<value>1</value>
|
||||||
|
<dispValue>1</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<ComboBox>
|
||||||
|
<define>CTRL.WD_CTRL[2:0]</define>
|
||||||
|
<value>5</value>
|
||||||
|
<dispValue>5</dispValue>
|
||||||
|
</ComboBox>
|
||||||
|
<ComboBox>
|
||||||
|
<define>CTRL.M_S_CTRL[1:0]</define>
|
||||||
|
<value>3</value>
|
||||||
|
<dispValue>3</dispValue>
|
||||||
|
</ComboBox>
|
||||||
|
<CheckBox>
|
||||||
|
<define>CTRL.HW_CTRL_1[7]</define>
|
||||||
|
<value>0</value>
|
||||||
|
<dispValue>0</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<CheckBox>
|
||||||
|
<define>CTRL.M_S_CTRL[2]</define>
|
||||||
|
<value>0</value>
|
||||||
|
<dispValue>0</dispValue>
|
||||||
|
</CheckBox>
|
||||||
|
<ComboBox>
|
||||||
|
<define>CTRL.BUS_CTRL_0[2:0]</define>
|
||||||
|
<value>3</value>
|
||||||
|
<dispValue>3</dispValue>
|
||||||
|
</ComboBox>
|
||||||
|
</ActiveElements>
|
||||||
|
</icwpxml>
|
||||||
591
cva_bootloader_m0128/src/TLE9461/TLE94x1.c
Normal file
591
cva_bootloader_m0128/src/TLE9461/TLE94x1.c
Normal file
@ -0,0 +1,591 @@
|
|||||||
|
/*********************************************************************************************************************
|
||||||
|
* Copyright (c) 2019, Infineon Technologies AG
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Distributed under the Boost Software License, Version 1.0.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person or organization
|
||||||
|
* obtaining a copy of the software and accompanying documentation covered by
|
||||||
|
* this license (the "Software") to use, reproduce, display, distribute,
|
||||||
|
* execute, and transmit the Software, and to prepare derivative works of the
|
||||||
|
* Software, and to permit third-parties to whom the Software is furnished to
|
||||||
|
* do so, all subject to the following:
|
||||||
|
*
|
||||||
|
* The copyright notices in the Software and this entire statement, including
|
||||||
|
* the above license grant, this restriction and the following disclaimer,
|
||||||
|
* must be included in all copies of the Software, in whole or in part, and
|
||||||
|
* all derivative works of the Software, unless such copies or derivative
|
||||||
|
* works are solely in the form of machine-executable object code generated by
|
||||||
|
* a source language processor.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||||
|
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||||
|
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||||
|
* DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*********************************************************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************************//**
|
||||||
|
* @file TLE94x1.c
|
||||||
|
*
|
||||||
|
* @brief Implementation of main library functions
|
||||||
|
*
|
||||||
|
* @version V1.0.1
|
||||||
|
* @date 05. October 2020
|
||||||
|
* @author Markus Noll / markus.noll@infineon.com
|
||||||
|
* @author Yannek Micha Rixen / Yannek.Rixen@infineon.com
|
||||||
|
********************************************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* ============================ HEADER FILES ================================ */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
#include "TLE94x1.h"
|
||||||
|
#include "SBC_TLE94x1.h"
|
||||||
|
#include <stdio.h>
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* ============================== Variables ================================= */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
|
||||||
|
/* -------------------------------- ISR Handling --------------------------------- */
|
||||||
|
|
||||||
|
static SBC_Func_Callback SBC_ISR_Callbacks[30];
|
||||||
|
static uint32_t SBC_ISR_Vectors[30];
|
||||||
|
static uint8_t SBC_ISR_ReadOutRegs[30];
|
||||||
|
static uint8_t SBC_ISR_ReadOutVals[30];
|
||||||
|
static uint8_t SBC_RegisteredCallbacks = 0;
|
||||||
|
static uint8_t SBC_RegisteredRedoutRegs = 0;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* =========================== Library Functions ============================ */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
|
||||||
|
/* -------------------------------- Main Functions ------------------------------- */
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_WD_Trigger(void) {
|
||||||
|
/* Read WD config out of SBC and write back to trigger WD */
|
||||||
|
uint8_t WD_Data = (uint8_t)SBC_Read_Command(SBC_WD_CTRL);
|
||||||
|
return SBC_Write_Reg(SBC_WD_CTRL, WD_Data, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
uint16_t SBC_Read_Command(uint8_t SBC_Reg) {
|
||||||
|
/* Read and return data - Bit[15:8] = Status Information Field - Bit [7:0] Register data */
|
||||||
|
return SBC_SPI_TRANSFER16(SBC_Read_Mask & SBC_Reg, 0x00U);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
uint8_t SBC_Read_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos) {
|
||||||
|
uint8_t data = ((uint8_t)SBC_Read_Command(SBC_Reg)) & 0xFFU;
|
||||||
|
return (data & SBC_FieldMsk) >> SBC_FieldPos;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_Write_Reg(uint8_t SBC_Reg, uint8_t SBC_Val, uint16_t * returnval) {
|
||||||
|
SBC_ErrorCode errCode;
|
||||||
|
uint16_t returndata = SBC_SPI_TRANSFER16(SBC_Write_Bit | SBC_Reg, SBC_Val);
|
||||||
|
if(returnval != NULL) {
|
||||||
|
*returnval = returndata;
|
||||||
|
}
|
||||||
|
|
||||||
|
errCode.SBC_Register = SBC_Reg;
|
||||||
|
errCode.flippedBitsMask = ((uint8_t)SBC_Read_Command(SBC_Reg)) ^ SBC_Val;
|
||||||
|
errCode.expectedValue = SBC_Val;
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_Write_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos, uint8_t SBC_FieldVal, uint16_t * returnval) {
|
||||||
|
SBC_ErrorCode errCode;
|
||||||
|
|
||||||
|
/* Read data out of register to be manipulated */
|
||||||
|
uint16_t returndata = SBC_Read_Command(SBC_Reg);
|
||||||
|
if(returnval != NULL) {
|
||||||
|
*returnval = returndata;
|
||||||
|
}
|
||||||
|
uint8_t data = (uint8_t)returndata;
|
||||||
|
|
||||||
|
/* Set the used bit field to all 0 */
|
||||||
|
data &= ~(SBC_FieldMsk);
|
||||||
|
|
||||||
|
/* Configure new data to bit field */
|
||||||
|
data |= (SBC_FieldVal << SBC_FieldPos);
|
||||||
|
|
||||||
|
(void)SBC_SPI_TRANSFER16(SBC_Write_Bit | SBC_Reg, data);
|
||||||
|
|
||||||
|
errCode.SBC_Register = SBC_Reg;
|
||||||
|
errCode.expectedValue = (SBC_FieldVal << SBC_FieldPos);
|
||||||
|
uint8_t actualValue = ((uint8_t)SBC_Read_Command(SBC_Reg)) & SBC_FieldMsk;
|
||||||
|
errCode.flippedBitsMask = errCode.expectedValue ^ actualValue;
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_Init(void) {
|
||||||
|
SBC_ErrorCode errCode;
|
||||||
|
uint8_t WD_Checksum = CTRL_WD_CTRL;
|
||||||
|
uint8_t WD_CTRL = CTRL_WD_CTRL;
|
||||||
|
uint8_t SWK_ID3_CTRL, SWK_ID2_CTRL, SWK_ID1_CTRL, SWK_ID0_CTRL;
|
||||||
|
uint8_t SWK_MASK_ID3_CTRL, SWK_MASK_ID2_CTRL, SWK_MASK_ID1_CTRL, SWK_MASK_ID0_CTRL;
|
||||||
|
uint8_t SWK_CAN_FD_CTRL = CTRL_SWK_CAN_FD_CTRL;
|
||||||
|
|
||||||
|
/* Calculate checksum */
|
||||||
|
WD_Checksum = WD_Checksum ^ WD_Checksum >> 4;
|
||||||
|
WD_Checksum = WD_Checksum ^ WD_Checksum >> 2;
|
||||||
|
WD_Checksum = WD_Checksum ^ WD_Checksum >> 1;
|
||||||
|
|
||||||
|
if((WD_Checksum & 1) > 0) {
|
||||||
|
/* Set parity bit */
|
||||||
|
WD_CTRL = CTRL_WD_CTRL | 0x80U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check if ID is configured to be extended */
|
||||||
|
if((CTRL_SWK_ID0_CTRL & SBC_SWK_ID0_CTRL_IDE_Msk) == SBC_IDE_EXTENDED) {
|
||||||
|
/* extended ID */
|
||||||
|
uint32_t SWK_ID_CTRL = CTRL_SWK_IDx_CTRL << 3;
|
||||||
|
uint32_t SWK_MASK_ID_CTRL = CTRL_SWK_MASK_IDx_CTRL << 3;
|
||||||
|
|
||||||
|
SWK_ID3_CTRL = (uint8_t)(SWK_ID_CTRL >> 24);
|
||||||
|
SWK_ID2_CTRL = (uint8_t)(SWK_ID_CTRL >> 16);
|
||||||
|
SWK_ID1_CTRL = (uint8_t)(SWK_ID_CTRL >> 8);
|
||||||
|
SWK_ID0_CTRL = (((uint8_t)(SWK_ID_CTRL >> 1)) & SBC_SWK_ID0_CTRL_ID4_0_Msk) | SBC_IDE_EXTENDED;
|
||||||
|
SWK_MASK_ID3_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 24);
|
||||||
|
SWK_MASK_ID2_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 16);
|
||||||
|
SWK_MASK_ID1_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 8);
|
||||||
|
SWK_MASK_ID0_CTRL = (((uint8_t)(SWK_MASK_ID_CTRL >> 1)) & SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk);
|
||||||
|
} else {
|
||||||
|
/* Standard length ID */
|
||||||
|
uint16_t SWK_ID_CTRL = CTRL_SWK_IDx_CTRL;
|
||||||
|
uint32_t SWK_MASK_ID_CTRL = CTRL_SWK_MASK_IDx_CTRL;
|
||||||
|
|
||||||
|
SWK_ID3_CTRL = (uint8_t)(SWK_ID_CTRL >> 3);
|
||||||
|
SWK_ID2_CTRL = (uint8_t)(SWK_ID_CTRL << 5);
|
||||||
|
SWK_ID1_CTRL = 0x00U;
|
||||||
|
SWK_ID0_CTRL = 0x00U;
|
||||||
|
SWK_MASK_ID3_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 3);
|
||||||
|
SWK_MASK_ID2_CTRL = (uint8_t)(SWK_MASK_ID_CTRL << 5);
|
||||||
|
SWK_MASK_ID1_CTRL = 0x00U;
|
||||||
|
SWK_MASK_ID0_CTRL = 0x00U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* DIS_ERR_CNT is set only when FD Tolerance is set. */
|
||||||
|
if((CTRL_SWK_CAN_FD_CTRL & SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk) == SBC_CAN_FD_EN_ENABLED) {
|
||||||
|
SWK_CAN_FD_CTRL &= SBC_DIS_ERR_CNT_DISABLED << SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Describes initialization sequence */
|
||||||
|
uint8_t initSequence[39][2] = {
|
||||||
|
{SBC_WD_CTRL, WD_CTRL},
|
||||||
|
{SBC_M_S_CTRL, CTRL_M_S_CTRL},
|
||||||
|
{SBC_HW_CTRL_0, CTRL_HW_CTRL_0},
|
||||||
|
{SBC_HW_CTRL_3, CTRL_HW_CTRL_3},
|
||||||
|
{SBC_BUS_CTRL_3, CTRL_BUS_CTRL_3},
|
||||||
|
{SBC_WK_CTRL_0, CTRL_WK_CTRL_0},
|
||||||
|
{SBC_WK_CTRL_1, CTRL_WK_CTRL_1},
|
||||||
|
{SBC_WK_PUPD_CTRL, CTRL_WK_PUPD_CTRL},
|
||||||
|
{SBC_TIMER_CTRL, CTRL_TIMER_CTRL},
|
||||||
|
{SBC_PWM_FREQ_CTRL, CTRL_PWM_FREQ_CTRL}, /* The desired duty cycle should be set first before GPIO is enabled as PWM HS or PWM LS. */
|
||||||
|
{SBC_PWM_CTRL, CTRL_PWM_CTRL},
|
||||||
|
{SBC_GPIO_CTRL, CTRL_GPIO_CTRL},
|
||||||
|
{SBC_HW_CTRL_1, CTRL_HW_CTRL_1}, /* May lock configuration (CFG_LOCK_0) */
|
||||||
|
{SBC_HW_CTRL_2, CTRL_HW_CTRL_2}, /* May lock configuration (CFG_LOCK_1) */
|
||||||
|
{SBC_BUS_CTRL_0, CTRL_BUS_CTRL_0},
|
||||||
|
|
||||||
|
/* -------------------------- SELECTIVE WAKE REGISTERS --------------------------- */
|
||||||
|
|
||||||
|
/* Configuring CDR */
|
||||||
|
{SBC_SWK_CDR_CTRL2, CTRL_SWK_CDR_CTRL2},
|
||||||
|
{SBC_SWK_BTL0_CTRL, CTRL_SWK_BTL0_CTRL},
|
||||||
|
{SBC_SWK_CDR_LIMIT_HIGH_CTRL, CTRL_SWK_CDR_LIMIT_HIGH_CTRL},
|
||||||
|
{SBC_SWK_CDR_LIMIT_LOW_CTRL, CTRL_SWK_CDR_LIMIT_LOW_CTRL},
|
||||||
|
{SBC_SWK_CDR_CTRL1, (SBC_SEL_FILT_TC16 << SBC_SWK_CDR_CTRL1_SEL_FILT_Pos) | (SBC_CDR_EN_ENABLED << SBC_SWK_CDR_CTRL1_CDR_EN_Pos)},
|
||||||
|
|
||||||
|
|
||||||
|
/* Set ID */
|
||||||
|
{SBC_SWK_ID3_CTRL, SWK_ID3_CTRL},
|
||||||
|
{SBC_SWK_ID2_CTRL, SWK_ID2_CTRL},
|
||||||
|
{SBC_SWK_ID1_CTRL, SWK_ID1_CTRL},
|
||||||
|
{SBC_SWK_ID0_CTRL, SWK_ID0_CTRL},
|
||||||
|
|
||||||
|
/* Set Mask */
|
||||||
|
{SBC_SWK_MASK_ID3_CTRL, SWK_MASK_ID3_CTRL},
|
||||||
|
{SBC_SWK_MASK_ID2_CTRL, SWK_MASK_ID2_CTRL},
|
||||||
|
{SBC_SWK_MASK_ID1_CTRL, SWK_MASK_ID1_CTRL},
|
||||||
|
{SBC_SWK_MASK_ID0_CTRL, SWK_MASK_ID0_CTRL},
|
||||||
|
|
||||||
|
/* Set Data */
|
||||||
|
{SBC_SWK_DATA7_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 24)},
|
||||||
|
{SBC_SWK_DATA6_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 16)},
|
||||||
|
{SBC_SWK_DATA5_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 8)},
|
||||||
|
{SBC_SWK_DATA4_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 0)},
|
||||||
|
{SBC_SWK_DATA3_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 24)},
|
||||||
|
{SBC_SWK_DATA2_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 16)},
|
||||||
|
{SBC_SWK_DATA1_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 8)},
|
||||||
|
{SBC_SWK_DATA0_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 0)},
|
||||||
|
|
||||||
|
/* Set DLC */
|
||||||
|
{SBC_SWK_DLC_CTRL, CTRL_SWK_DLC_CTRL},
|
||||||
|
|
||||||
|
{SBC_SWK_CAN_FD_CTRL, SWK_CAN_FD_CTRL},
|
||||||
|
|
||||||
|
/* End Configuration */
|
||||||
|
{0x00U, 0x00U}
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Call SPI Init */
|
||||||
|
if(SBC_SPI_INIT() != 0) {
|
||||||
|
errCode.SBC_Register = 0x00;
|
||||||
|
errCode.flippedBitsMask = 0xFF;
|
||||||
|
errCode.expectedValue = 0x00;
|
||||||
|
return errCode;
|
||||||
|
};
|
||||||
|
|
||||||
|
uint8_t i = 0;
|
||||||
|
|
||||||
|
/* Write all initialization items to Lite SBC */
|
||||||
|
while(initSequence[i][0] != 0x00U || initSequence[i][1] != 0x00U) {
|
||||||
|
errCode = SBC_Write_Reg(initSequence[i][0], initSequence[i][1], NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
i++;
|
||||||
|
}
|
||||||
|
|
||||||
|
errCode.SBC_Register = 0x00;
|
||||||
|
errCode.flippedBitsMask = 0x00;
|
||||||
|
errCode.expectedValue = 0x00;
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* -------------------------------- ISR Functions -------------------------------- */
|
||||||
|
|
||||||
|
|
||||||
|
void SBC_Register_Callback(uint32_t ISR_Vector, void (*Callback_Handler)(uint8_t callbackHandler)) {
|
||||||
|
/* Save callback */
|
||||||
|
SBC_ISR_Callbacks[SBC_RegisteredCallbacks] = Callback_Handler;
|
||||||
|
|
||||||
|
/* Save callback vector */
|
||||||
|
SBC_ISR_Vectors[SBC_RegisteredCallbacks] = ISR_Vector;
|
||||||
|
|
||||||
|
/* Check if the register will be readout already to avoid double-readout later */
|
||||||
|
uint8_t RegFound = 0;
|
||||||
|
for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) {
|
||||||
|
if (SBC_ISR_ReadOutRegs[i] == (ISR_Vector >> 24)) {
|
||||||
|
RegFound = 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* If readout status-reg was not found, register in the readout list */
|
||||||
|
if (RegFound == 0) {
|
||||||
|
SBC_ISR_ReadOutRegs[SBC_RegisteredRedoutRegs] = (uint8_t)(ISR_Vector >> 24);
|
||||||
|
SBC_RegisteredRedoutRegs++;
|
||||||
|
}
|
||||||
|
|
||||||
|
SBC_RegisteredCallbacks++;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_ISR(void) {
|
||||||
|
SBC_ErrorCode errCode;
|
||||||
|
|
||||||
|
/* Readout all registered status-registers */
|
||||||
|
for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) {
|
||||||
|
SBC_ISR_ReadOutVals[i] = (uint8_t) SBC_Read_Command(SBC_ISR_ReadOutRegs[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Handle all interrupts */
|
||||||
|
for (uint8_t i = 0; i < SBC_RegisteredCallbacks; i++) {
|
||||||
|
/* Decode ISR Vector */
|
||||||
|
uint8_t Compare = (uint8_t)SBC_ISR_Vectors[i];
|
||||||
|
uint8_t FieldPos = (uint8_t)(SBC_ISR_Vectors[i] >> 8);
|
||||||
|
uint8_t FieldMsk = (uint8_t)(SBC_ISR_Vectors[i] >> 16);
|
||||||
|
uint8_t RegAddr = (uint8_t)(SBC_ISR_Vectors[i] >> 24);
|
||||||
|
|
||||||
|
/* Readback of associated status-bit */
|
||||||
|
uint8_t ReadBack = 0;
|
||||||
|
for (uint8_t j = 0; j < SBC_RegisteredRedoutRegs; j++) {
|
||||||
|
if (SBC_ISR_ReadOutRegs[j] == RegAddr) {
|
||||||
|
ReadBack = SBC_ISR_ReadOutVals[j];
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* If compare-values matched -> proceed callback and clear field */
|
||||||
|
if (((ReadBack & FieldMsk) >> FieldPos) == Compare) {
|
||||||
|
SBC_ISR_Callbacks[i](ReadBack);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear all ISR related registers */
|
||||||
|
for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) {
|
||||||
|
errCode = SBC_Write_Reg(SBC_ISR_ReadOutRegs[i], 0x00U, NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
errCode.SBC_Register = 0x00U;
|
||||||
|
errCode.flippedBitsMask = 0x00U;
|
||||||
|
errCode.expectedValue = 0x00U;
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* -------------------------------- API Calls ----------------------------------- */
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_Mode_Normal(void) {
|
||||||
|
return SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_NORMAL, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_Mode_Stop(void) {
|
||||||
|
return SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_STOP, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_Mode_Sleep(void) {
|
||||||
|
uint8_t registerReadOut;
|
||||||
|
|
||||||
|
SBC_ErrorCode errCode;
|
||||||
|
|
||||||
|
/* If CAN PN is configured */
|
||||||
|
if(MATH_EN_PN != 0) {
|
||||||
|
|
||||||
|
/* Reading value of SWK_STAT. */
|
||||||
|
registerReadOut = (uint8_t)SBC_Read_Command(SBC_SWK_STAT);
|
||||||
|
|
||||||
|
/* CAN Protocol Handler in sync? The selective wake routine should be aborted if sync is not set. Note: for SYNC to be set the transceiver must have been in Normal Mode and a valid CAN communication must have been sent on the bus by any node. */
|
||||||
|
if((registerReadOut & SBC_SWK_STAT_SYNC_Msk) >> SBC_SWK_STAT_SYNC_Pos != SBC_SYNC_VALID_FRAME_RECEIVED) {
|
||||||
|
errCode.SBC_Register = SBC_SWK_STAT;
|
||||||
|
errCode.flippedBitsMask = SBC_SWK_STAT_SYNC_Msk;
|
||||||
|
errCode.expectedValue = SBC_SYNC_VALID_FRAME_RECEIVED << SBC_SWK_STAT_SYNC_Pos;
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set SWK Configuration valid */
|
||||||
|
errCode = SBC_Write_RegField(SBC_SWK_CTRL, SBC_SWK_CTRL_CFG_VAL_Msk, SBC_SWK_CTRL_CFG_VAL_Pos, SBC_CFG_VAL_VALID, NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* Clear SYSERR bit */
|
||||||
|
errCode = SBC_Write_RegField(SBC_BUS_STAT, SBC_BUS_STAT_SYSERR_Msk, SBC_BUS_STAT_SYSERR_Pos, 0x00, NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set CAN Mode to off and once again to desired configuration */
|
||||||
|
errCode = SBC_Write_Reg(SBC_BUS_CTRL_0, 0x03, NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
errCode = SBC_Write_Reg(SBC_BUS_CTRL_0, CTRL_BUS_CTRL_0, NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check SWK_STAT for SYNC == 1 && SWK_SET == 1 && WUF == 0 && WUP == 0. Ignore CANSIL */
|
||||||
|
registerReadOut = (uint8_t)SBC_Read_Command(SBC_SWK_STAT);
|
||||||
|
if( ((SBC_SWK_STAT_SYNC_Msk & registerReadOut) == SBC_SWK_STAT_SYNC_Msk)
|
||||||
|
&& ((SBC_SWK_STAT_SWK_SET_Msk & registerReadOut) == SBC_SWK_STAT_SWK_SET_Msk)
|
||||||
|
&& ((SBC_SWK_STAT_WUP_Msk & registerReadOut) != SBC_SWK_STAT_WUP_Msk)
|
||||||
|
&& ((SBC_SWK_STAT_WUF_Msk & registerReadOut) != SBC_SWK_STAT_WUF_Msk)) {
|
||||||
|
/* Empty */
|
||||||
|
} else {
|
||||||
|
errCode.SBC_Register = SBC_SWK_STAT;
|
||||||
|
errCode.expectedValue = 0b01000100U;
|
||||||
|
errCode.flippedBitsMask = errCode.expectedValue ^ registerReadOut;
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Clear Wake Status Registers, so that SBC can sleep. */
|
||||||
|
errCode = SBC_Write_Reg(SBC_WK_STAT_0, 0x00, NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
errCode = SBC_Write_Reg(SBC_WK_STAT_1, 0x00, NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Select sleep mode */
|
||||||
|
(void)SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_SLEEP, NULL);
|
||||||
|
registerReadOut = (uint8_t)SBC_Read_Command(SBC_M_S_CTRL);
|
||||||
|
|
||||||
|
/* This piece of code is ideally never reached as the microcontroller should be already turned off then */
|
||||||
|
if(registerReadOut != 0) {
|
||||||
|
errCode.SBC_Register = SBC_M_S_CTRL;
|
||||||
|
errCode.flippedBitsMask = registerReadOut;
|
||||||
|
errCode.expectedValue = 0x00U;
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
errCode.SBC_Register = 0x00U;
|
||||||
|
errCode.flippedBitsMask = 0x00U;
|
||||||
|
errCode.expectedValue = 0x00U;
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_Set_DutyCycle_PWM (uint8_t PWM_DC) {
|
||||||
|
return SBC_Write_Reg(SBC_PWM_CTRL, PWM_DC, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_Set_Timer_On (uint8_t OnTime) {
|
||||||
|
return SBC_Write_RegField(SBC_TIMER_CTRL, SBC_TIMER_CTRL_TIMER_ON_Msk, SBC_TIMER_CTRL_TIMER_ON_Pos, OnTime, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_Set_Timer_Period (uint8_t Period) {
|
||||||
|
return SBC_Write_RegField(SBC_TIMER_CTRL, SBC_TIMER_CTRL_TIMER_PER_Msk, SBC_TIMER_CTRL_TIMER_PER_Pos, Period, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_FO_Test_On(void) {
|
||||||
|
return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_FO_ON_Msk, SBC_HW_CTRL_0_FO_ON_Pos, SBC_FO_ON_ACTIVE, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_FO_Test_Off(void) {
|
||||||
|
return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_FO_ON_Msk, SBC_HW_CTRL_0_FO_ON_Pos, SBC_FO_ON_NOT_ACTIVE, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_CP_On(void) {
|
||||||
|
return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_CP_EN_Msk, SBC_HW_CTRL_0_CP_EN_Pos, SBC_CP_EN_ON, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_CP_Off(void) {
|
||||||
|
return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_CP_EN_Msk, SBC_HW_CTRL_0_CP_EN_Pos, SBC_CP_EN_OFF, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_WK_MEAS_On(void) {
|
||||||
|
return SBC_Write_RegField(SBC_WK_CTRL_1, SBC_WK_CTRL_1_WK_MEAS_Msk, SBC_WK_CTRL_1_WK_MEAS_Pos, SBC_WK_MEAS_WK_AS_VOLTAGESENSING, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_WK_MEAS_Off(void) {
|
||||||
|
return SBC_Write_RegField(SBC_WK_CTRL_1, SBC_WK_CTRL_1_WK_MEAS_Msk, SBC_WK_CTRL_1_WK_MEAS_Pos, SBC_WK_MEAS_WK_AS_WAKEUP, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_TIMER_WK_EN_On(void) {
|
||||||
|
return SBC_Write_RegField(SBC_WK_CTRL_0, SBC_WK_CTRL_0_TIMER_WK_EN_Msk, SBC_WK_CTRL_0_TIMER_WK_EN_Pos, WK_CTRL_0_TIMER_WK_EN_WAKESOURCE, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_TIMER_WK_EN_Off(void) {
|
||||||
|
return SBC_Write_RegField(SBC_WK_CTRL_0, SBC_WK_CTRL_0_TIMER_WK_EN_Msk, SBC_WK_CTRL_0_TIMER_WK_EN_Pos, WK_CTRL_0_TIMER_WK_EN_WAKEUP_DISABLED, NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
uint16_t SBC_SYS_STAT_Read(void) {
|
||||||
|
uint16_t systemStatus = 0;
|
||||||
|
uint16_t returndata = SBC_Read_Command(SBC_SYS_STATUS_CTRL_0);
|
||||||
|
systemStatus = returndata & 0x00FFU;
|
||||||
|
systemStatus |= SBC_Read_Command(SBC_SYS_STATUS_CTRL_1) << 8;
|
||||||
|
return systemStatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_SYS_STAT_Write(uint16_t SystemStatus) {
|
||||||
|
SBC_ErrorCode errCode;
|
||||||
|
|
||||||
|
/* Write lower bits */
|
||||||
|
errCode = SBC_Write_Reg(SBC_SYS_STATUS_CTRL_0, (uint8_t)SystemStatus, NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Write higher bits */
|
||||||
|
return SBC_Write_Reg(SBC_SYS_STATUS_CTRL_1, (uint8_t)(SystemStatus >> 8), NULL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_Lock_Configuration(void) {
|
||||||
|
SBC_ErrorCode errCode;
|
||||||
|
|
||||||
|
/* Lock CP_EN and GPIO cannot be modified */
|
||||||
|
errCode = SBC_Write_RegField(SBC_HW_CTRL_1, SBC_HW_CTRL_1_CFG_LOCK_0_Msk, SBC_HW_CTRL_1_CFG_LOCK_0_Pos, SBC_CFG_LOCK_0_LOCKED, NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Lock Bits with bit type ‘rwl’ (except CP_EN and GPIO) until next device power-up. */
|
||||||
|
errCode = SBC_Write_RegField(SBC_HW_CTRL_2, SBC_HW_CTRL_2_CFG_LOCK_1_Msk, SBC_HW_CTRL_2_CFG_LOCK_1_Pos, SBC_CFG_LOCK_1_LOCKED, NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
errCode.SBC_Register = 0x00;
|
||||||
|
errCode.flippedBitsMask = 0x00;
|
||||||
|
errCode.expectedValue = 0x00;
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_Unlock_Configuration(void) {
|
||||||
|
SBC_ErrorCode errCode;
|
||||||
|
|
||||||
|
/* Unlock CP_EN and GPIO configuration. */
|
||||||
|
errCode = SBC_Write_RegField(SBC_HW_CTRL_1, SBC_HW_CTRL_1_CFG_LOCK_0_Msk, SBC_HW_CTRL_1_CFG_LOCK_0_Pos, SBC_CFG_LOCK_0_NOTLOCKED, NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Unlock Bits with bit type ‘rwl’ (except CP_EN and GPIO). */
|
||||||
|
errCode = SBC_Write_RegField(SBC_HW_CTRL_2, SBC_HW_CTRL_2_CFG_LOCK_1_Msk, SBC_HW_CTRL_2_CFG_LOCK_1_Pos, SBC_CFG_LOCK_1_NOTLOCKED, NULL);
|
||||||
|
if(errCode.flippedBitsMask > 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
errCode.SBC_Register = 0x00;
|
||||||
|
errCode.flippedBitsMask = 0x00;
|
||||||
|
errCode.expectedValue = 0x00;
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
|
||||||
|
SBC_ErrorCode SBC_Clear_Wake_Status(void) {
|
||||||
|
SBC_ErrorCode errCode = SBC_Write_Reg(SBC_WK_STAT_0, 0x00, NULL);
|
||||||
|
if(errCode.flippedBitsMask != 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
errCode = SBC_Write_Reg(SBC_WK_STAT_1, 0x00, NULL);
|
||||||
|
if(errCode.flippedBitsMask != 0) {
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
|
errCode.SBC_Register = 0x00;
|
||||||
|
errCode.flippedBitsMask = 0x00;
|
||||||
|
errCode.expectedValue = 0x00;
|
||||||
|
return errCode;
|
||||||
|
}
|
||||||
393
cva_bootloader_m0128/src/TLE9461/TLE94x1.h
Normal file
393
cva_bootloader_m0128/src/TLE9461/TLE94x1.h
Normal file
@ -0,0 +1,393 @@
|
|||||||
|
/*********************************************************************************************************************
|
||||||
|
* Copyright (c) 2019, Infineon Technologies AG
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Distributed under the Boost Software License, Version 1.0.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person or organization
|
||||||
|
* obtaining a copy of the software and accompanying documentation covered by
|
||||||
|
* this license (the "Software") to use, reproduce, display, distribute,
|
||||||
|
* execute, and transmit the Software, and to prepare derivative works of the
|
||||||
|
* Software, and to permit third-parties to whom the Software is furnished to
|
||||||
|
* do so, all subject to the following:
|
||||||
|
*
|
||||||
|
* The copyright notices in the Software and this entire statement, including
|
||||||
|
* the above license grant, this restriction and the following disclaimer,
|
||||||
|
* must be included in all copies of the Software, in whole or in part, and
|
||||||
|
* all derivative works of the Software, unless such copies or derivative
|
||||||
|
* works are solely in the form of machine-executable object code generated by
|
||||||
|
* a source language processor.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||||
|
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||||
|
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||||
|
* DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*********************************************************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************************//**
|
||||||
|
* @file TLE94x1.h
|
||||||
|
*
|
||||||
|
* @brief Main header declaration file for TLE94x1 SBC family device
|
||||||
|
*
|
||||||
|
* @version V1.0.0
|
||||||
|
* @date 15. April 2019
|
||||||
|
* @author Markus Noll / markus.noll@infineon.com
|
||||||
|
* @author Yannek Micha Rixen / Yannek.Rixen@infineon.com
|
||||||
|
*******************************************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef TLE94x1_H
|
||||||
|
#define TLE94x1_H
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* ============================ HEADER FILES ================================ */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#include "TLE94x1_DEFINES.h"
|
||||||
|
#include "TLE94x1_ISR.h"
|
||||||
|
#include "TLE94x1_SPI.h"
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* ================================ MACROS ================================== */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @def SBC_Write_Bit
|
||||||
|
*
|
||||||
|
* @brief This bit has to be set in order to write to a register.
|
||||||
|
*/
|
||||||
|
#define SBC_Write_Bit (0x80U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @def SBC_Read_Mask
|
||||||
|
*
|
||||||
|
* @brief A mask to prevent the user from accidentally writing to a register.
|
||||||
|
*/
|
||||||
|
#define SBC_Read_Mask (0x7FU)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* =========================== Library Functions ============================ */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
struct __SBC_ErrorCode;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief A structure for simple error readout.
|
||||||
|
*
|
||||||
|
* flippedBitsMask is greater than 0 if the value read from the register at SBC_Register differs from expectedValue.
|
||||||
|
*/
|
||||||
|
typedef struct __SBC_ErrorCode {
|
||||||
|
uint8_t SBC_Register; //!< The register where an error occurred.
|
||||||
|
uint8_t flippedBitsMask; //!< Masks the bits that differ from the expected value. Is 0 if readout is as expected.
|
||||||
|
uint8_t expectedValue; //!< Expected readout of the register.
|
||||||
|
} SBC_ErrorCode;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Typedef for interrupt callbacks.
|
||||||
|
*/
|
||||||
|
typedef void (*SBC_Func_Callback)(uint8_t callbackHandler);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* -------------------------------- Main Functions ------------------------------- */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This method will trigger the watchdog.
|
||||||
|
*
|
||||||
|
* The function must be called periodically according to the configured watchdog-time.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_WD_Trigger(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This method will proceed a readout of a register.
|
||||||
|
*
|
||||||
|
* @param SBC_Reg Address of the register to be read out. See TLE94x1_DEFINES.h for definitions
|
||||||
|
* @retval A 16 bit value will be returned.
|
||||||
|
* Bit[15:8] is the Status-Information-Field, Bit [7:0] is the read register-value.
|
||||||
|
* For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet.
|
||||||
|
*/
|
||||||
|
uint16_t SBC_Read_Command(uint8_t SBC_Reg);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This method will proceed a readout of a dedicated bitfield within a register
|
||||||
|
*
|
||||||
|
* @param SBC_Reg Address of the register to be readout. See TLE94x1_DEFINES.h for definitions
|
||||||
|
* @param SBC_FieldMsk Bit mask of the field to be readout. See TLE94x1_DEFINES.h for definitions
|
||||||
|
* @param SBC_FieldPos Bit position of the field to be readout. See TLE94x1_DEFINES.h for definitions
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* @retval A 8 bit value will be returned and includes the data of the bitfield to be read out *
|
||||||
|
*/
|
||||||
|
uint8_t SBC_Read_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes a whole byte to a register and verifies it.
|
||||||
|
*
|
||||||
|
* @param SBC_Reg Address of the register to be manipulated. See TLE94x1_DEFINES.h for definitions
|
||||||
|
* @param SBC_Val Byte to write to SBC_Reg
|
||||||
|
* @param *returnval A 16 bit value will be returned.
|
||||||
|
* Bit[15:8] is the Status-Information-Field, Bit [7:0] is the value of the manipulated register before write
|
||||||
|
* For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet.
|
||||||
|
*
|
||||||
|
* @retval See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_Write_Reg(uint8_t SBC_Reg, uint8_t SBC_Val, uint16_t * returnval);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This method can be used for manipulating a single bit-field in a control-register.
|
||||||
|
*
|
||||||
|
* It will readout the old value of the registers, manipulate the desired bit-field and keep
|
||||||
|
* the other bit-configuration as it was.
|
||||||
|
* For usage examples have a look at the implementations of different API calls below.
|
||||||
|
*
|
||||||
|
* @param SBC_Reg Address of the register to be manipulated. See TLE94x1_DEFINES.h for definitions
|
||||||
|
* @param SBC_FieldMsk Bit mask of the field to manipulate. See TLE94x1_DEFINES.h for definitions
|
||||||
|
* @param SBC_FieldPos Bit position of the field to manipulate. See TLE94x1_DEFINES.h for definitions
|
||||||
|
* @param SBC_FieldVal New value which will be written to the bit-field. See TLE94x1_DEFINES.h for enumerations
|
||||||
|
* @param *returnval A 16 bit value will be returned.
|
||||||
|
* Bit[15:8] is the Status-Information-Field, Bit [7:0] is the value of the manipulated register before write
|
||||||
|
* For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_Write_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos, uint8_t SBC_FieldVal, uint16_t * returnval);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This method must be called one time at startup of the microcontroller.
|
||||||
|
*
|
||||||
|
* This method will initialize all registers of the SBC with the configuration-data of SBC_TLE94x1.h.
|
||||||
|
* After this, the SBC can be used as normal.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_Init(void);
|
||||||
|
|
||||||
|
/* -------------------------------- ISR Functions -------------------------------- */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function can register a self-defined function to a specific interrupt-event of the SBC.
|
||||||
|
*
|
||||||
|
* Everytime the SBC_ISR() method is called and the associated status-bit is set, it will consider to
|
||||||
|
* proceed a callback to this function later.
|
||||||
|
* See all the possible ISR_Vectors in the TLE94x1_ISR.h
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* @param ISR_Vector Definition of the interrupt event. See all possible events in TLE94x1_ISR.h
|
||||||
|
*
|
||||||
|
* @param *Callback_Handler Pointer to the function which will be called back.
|
||||||
|
* The function must accept a uint8_t as first argument.
|
||||||
|
*/
|
||||||
|
void SBC_Register_Callback(uint32_t ISR_Vector, void (*Callback_Handler)(uint8_t callbackHandler));
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Interrupt Service Routine for handling interrupts.
|
||||||
|
*
|
||||||
|
* This method must be called automatically everytime a rising-edge on the INTN pin is recognized.
|
||||||
|
* In case, the INTN pin is not connected, this method can also be called periodically by the user during runtime.
|
||||||
|
* The ISR will proceed a readout of all registered interrupts. If a status-bit of a registered interrupt is set,
|
||||||
|
* it will initiate a callback to the registered function and give the registered function the status-register value
|
||||||
|
* as a parameter.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_ISR(void);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* -------------------------------- API Calls ----------------------------------- */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enters SBC normal mode
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_Mode_Normal(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enters SBC stop mode
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_Mode_Stop(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears all wake status registers and enter SBC sleep mode. Depending on configuration also the selective-wake feature will be initialized
|
||||||
|
* before entering sleep mode. In case, the SWK option is enabled and the internal CAN protocol handler is not in sync when calling this function,
|
||||||
|
* the sleep mode will be not entered.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_Mode_Sleep(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the duty-cycle of the internal PWM generator
|
||||||
|
*
|
||||||
|
* @param PWM_DC Set the duty-cycle with values of 0-255 for 0% to 100%
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_Set_DutyCycle_PWM(uint8_t PWM_DC);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the OnTime of the internal timer.
|
||||||
|
*
|
||||||
|
* @param OnTime On time which will be configured to the timer. See TLE94x1_DEFINES.h for enumerations.
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_Set_Timer_On(uint8_t OnTime);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Sets the Period time of the internal timer
|
||||||
|
*
|
||||||
|
* @param Period Period time which will be configured to the timer. See TLE94x1_DEFINES.h for enumerations.
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_Set_Timer_Period(uint8_t Period);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief FO output activated by software for testing. Only working if FO/GPIO is configured as FO
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_FO_Test_On(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief FO output deactivated by software for testing. Only working if FO/GPIO is configured as FO
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_FO_Test_Off(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Charge-Pump (VCP-Pin) is enabled. See chapter 5.3 in datasheet.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_CP_On(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Charge-Pump (VCP-Pin) is disabled. See chapter 5.3 in datasheet.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_CP_Off(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Voltage Sensing. No wake-up events are generated. See chapter 9.2.4 in datasheet.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_WK_MEAS_On(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Voltage Sensing and enable wake-up functionality. See chapter 9.2.4 in datasheet.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_WK_MEAS_Off(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief WK is enabled as wake source. See chapter 5.2.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_TIMER_WK_EN_On(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief WK wake-up disabled. See chapter 5.2.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_TIMER_WK_EN_Off(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reads System Status Control, both lower and higher bits. See page 138 in datasheet.
|
||||||
|
*
|
||||||
|
* @retval Upper 8 bit are read from register SBC_SYS_STATUS_CTRL_1 and the lower 8 bit from SBC_SYS_STATUS_CTRL_0
|
||||||
|
*/
|
||||||
|
uint16_t SBC_SYS_STAT_Read(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Writes System Status Control, both lower and higher bits. See page 138 in datasheet.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_SYS_STAT_Write(uint16_t SystemStatus);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Locks CP_EN, GPIO configuration and 'rwl'-bits.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_Lock_Configuration(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Unlocks CP_EN, GPIO configuration and 'rwl'-bits.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_Unlock_Configuration(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clears both Wake Status registers.
|
||||||
|
*
|
||||||
|
* @retval SBC_ErrorCode See description of SBC_ErrorCode.
|
||||||
|
*/
|
||||||
|
SBC_ErrorCode SBC_Clear_Wake_Status(void);
|
||||||
|
|
||||||
|
#endif /*TLE94x1_H*/
|
||||||
3248
cva_bootloader_m0128/src/TLE9461/TLE94x1_DEFINES.h
Normal file
3248
cva_bootloader_m0128/src/TLE9461/TLE94x1_DEFINES.h
Normal file
File diff suppressed because it is too large
Load Diff
127
cva_bootloader_m0128/src/TLE9461/TLE94x1_ISR.h
Normal file
127
cva_bootloader_m0128/src/TLE9461/TLE94x1_ISR.h
Normal file
@ -0,0 +1,127 @@
|
|||||||
|
/*********************************************************************************************************************
|
||||||
|
* Copyright (c) 2019, Infineon Technologies AG
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Distributed under the Boost Software License, Version 1.0.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person or organization
|
||||||
|
* obtaining a copy of the software and accompanying documentation covered by
|
||||||
|
* this license (the "Software") to use, reproduce, display, distribute,
|
||||||
|
* execute, and transmit the Software, and to prepare derivative works of the
|
||||||
|
* Software, and to permit third-parties to whom the Software is furnished to
|
||||||
|
* do so, all subject to the following:
|
||||||
|
*
|
||||||
|
* The copyright notices in the Software and this entire statement, including
|
||||||
|
* the above license grant, this restriction and the following disclaimer,
|
||||||
|
* must be included in all copies of the Software, in whole or in part, and
|
||||||
|
* all derivative works of the Software, unless such copies or derivative
|
||||||
|
* works are solely in the form of machine-executable object code generated by
|
||||||
|
* a source language processor.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||||
|
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||||
|
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||||
|
* DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*********************************************************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************************//**
|
||||||
|
* @file TLE94x1_ISR.h
|
||||||
|
*
|
||||||
|
* @brief Declaration file for ISR-Vectors and ISR related functions
|
||||||
|
*
|
||||||
|
* @version V1.0.0
|
||||||
|
* @date 15. April 2019
|
||||||
|
* @author Markus Noll / markus.noll@infineon.com
|
||||||
|
* @author Yannek Micha Rixen / Yannek.Rixen@infineon.com
|
||||||
|
*******************************************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef TLE94x1_ISR_H
|
||||||
|
#define TLE94x1_ISR_H
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* ============================ HEADER FILES ================================== */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
#include "TLE94x1_DEFINES.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* ================================ MACROS ==================================== */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @def SBC_ISR_VECTOR
|
||||||
|
*
|
||||||
|
* @brief Vector defining the handling of interrupts.
|
||||||
|
*
|
||||||
|
* Vectors of this type have to be registered by the SBC_Register_Callback method.
|
||||||
|
*/
|
||||||
|
#define SBC_ISR_VECTOR(REG,MASK,POS,COMPARE) ((((uint32_t)REG) << 24) | (((uint32_t)MASK) << 16) | (((uint32_t)POS) << 8) | ((uint32_t)COMPARE))
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* ======================= General Interrupt Defines ========================== */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupts based on WK_STAT_0 and WK_STAT_1 register are always available */
|
||||||
|
#define SBC_ISR_CAN_WU SBC_ISR_VECTOR(SBC_WK_STAT_0, SBC_WK_STAT_0_CAN_WU_Msk, SBC_WK_STAT_0_CAN_WU_Pos, SBC_CAN_WU_EVENT)
|
||||||
|
#define SBC_ISR_TIMER_WU SBC_ISR_VECTOR(SBC_WK_STAT_0, SBC_WK_STAT_0_TIMER_WU_Msk, SBC_WK_STAT_0_TIMER_WU_Pos, SBC_TIMER_WU_EVENT)
|
||||||
|
#define SBC_ISR_WK_WU SBC_ISR_VECTOR(SBC_WK_STAT_0, SBC_WK_STAT_0_WK_WU_Msk, SBC_WK_STAT_0_WK_WU_Pos, SBC_WK_WU_EVENT)
|
||||||
|
#define SBC_ISR_GPIO_WK_WU SBC_ISR_VECTOR(SBC_WK_STAT_1, SBC_WK_STAT_1_GPIO_WK_WU_Msk, SBC_WK_STAT_1_GPIO_WK_WU_Pos, SBC_GPIO_WK_WU_EVENT)
|
||||||
|
|
||||||
|
|
||||||
|
/* Following interrupts only usable if INT_GLOBAL bit is set to '1' */
|
||||||
|
#define SBC_ISR_VS_UV SBC_ISR_VECTOR(SBC_SUP_STAT_1, SBC_SUP_STAT_1_VS_UV_Msk, SBC_SUP_STAT_1_VS_UV_Pos, SBC_VS_UV_EVENT)
|
||||||
|
#define SBC_ISR_VS_OV SBC_ISR_VECTOR(SBC_SUP_STAT_1, SBC_SUP_STAT_1_VS_OV_Msk, SBC_SUP_STAT_1_VS_OV_Pos, SBC_VS_OV_EVENT)
|
||||||
|
#define SBC_ISR_VCC1_OV SBC_ISR_VECTOR(SBC_SUP_STAT_1, SBC_SUP_STAT_1_VCC1_OV_Msk, SBC_SUP_STAT_1_VCC1_OV_Pos, SBC_VCC1_OV_EVENT)
|
||||||
|
#define SBC_ISR_VCC1_UV_PREWARN SBC_ISR_VECTOR(SBC_SUP_STAT_1, SBC_SUP_STAT_1_VCC1_WARN_Msk, SBC_SUP_STAT_1_VCC1_WARN_Pos, SBC_VCC1_UV_PREWARN_EVENT)
|
||||||
|
#define SBC_ISR_VCC2_OT SBC_ISR_VECTOR(SBC_SUP_STAT_0, SBC_SUP_STAT_0_VCC2_OT_Msk, SBC_SUP_STAT_0_VCC2_OT_Pos, SBC_VCC2_OT_EVENT)
|
||||||
|
#define SBC_ISR_VCC2_UV SBC_ISR_VECTOR(SBC_SUP_STAT_0, SBC_SUP_STAT_0_VCC2_UV_Msk, SBC_SUP_STAT_0_VCC2_UV_Pos, SBC_VCC2_UV_EVENT)
|
||||||
|
#define SBC_ISR_VCC1_UV SBC_ISR_VECTOR(SBC_SUP_STAT_0, SBC_SUP_STAT_0_VCC1_UV_Msk, SBC_SUP_STAT_0_VCC1_UV_Pos, SBC_VCC1_UV_EVENT)
|
||||||
|
#define SBC_ISR_TSD2_SAFESTATE SBC_ISR_VECTOR(SBC_THERM_STAT, SBC_THERM_STAT_TSD2_SAFE_Msk, SBC_THERM_STAT_TSD2_SAFE_Pos, SBC_TSD2_SAFE_SAFESTATE_DETECTED)
|
||||||
|
#define SBC_ISR_TSD1 SBC_ISR_VECTOR(SBC_THERM_STAT, SBC_THERM_STAT_TSD1_Msk, SBC_THERM_STAT_TSD1_Pos, SBC_TSD1_EVENT)
|
||||||
|
#define SBC_ISR_TPW SBC_ISR_VECTOR(SBC_THERM_STAT, SBC_THERM_STAT_TPW_Msk, SBC_THERM_STAT_TPW_Pos, SBC_TPW_EVENT)
|
||||||
|
#define SBC_ISR_RESTART_AFTER_FAIL SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_DEV_STAT_Msk, SBC_DEV_STAT_DEV_STAT_Pos, SBC_DEV_STAT_RESTART_AFTER_FAIL)
|
||||||
|
#define SBC_ISR_FROM_SLEEPMODE SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_DEV_STAT_Msk, SBC_DEV_STAT_DEV_STAT_Pos, SBC_DEV_STAT_SLEEP_MODE)
|
||||||
|
#define SBC_ISR_WD_FAIL_1 SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_WD_FAIL_Msk, SBC_DEV_STAT_WD_FAIL_Pos, SBC_WD_FAIL_1FAIL)
|
||||||
|
#define SBC_ISR_WD_FAIL_2 SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_WD_FAIL_Msk, SBC_DEV_STAT_WD_FAIL_Pos, SBC_WD_FAIL_2FAIL)
|
||||||
|
#define SBC_ISR_FAILURE SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_FAILURE_Msk, SBC_DEV_STAT_FAILURE_Pos, SBC_FAILURE_EVENT)
|
||||||
|
#define SBC_ISR_CAN_TSD SBC_ISR_VECTOR(SBC_BUS_STAT, SBC_BUS_STAT_CAN_FAIL_Msk, SBC_BUS_STAT_CAN_FAIL_Pos, SBC_CAN_FAIL_TSD)
|
||||||
|
#define SBC_ISR_CAN_TXD_DOM_TO SBC_ISR_VECTOR(SBC_BUS_STAT, SBC_BUS_STAT_CAN_FAIL_Msk, SBC_BUS_STAT_CAN_FAIL_Pos, SBC_CAN_FAIL_TXD_DOM_TO)
|
||||||
|
#define SBC_ISR_CAN_BUS_DOM_TO SBC_ISR_VECTOR(SBC_BUS_STAT, SBC_BUS_STAT_CAN_FAIL_Msk, SBC_BUS_STAT_CAN_FAIL_Pos, SBC_CAN_FAIL_BUS_DOM_TO)
|
||||||
|
#define SBC_ISR_VCAN_UV SBC_ISR_VECTOR(SBC_BUS_STAT, SBC_BUS_STAT_VCAN_UV_Msk, SBC_BUS_STAT_VCAN_UV_Pos, SBC_VCAN_UV_EVENT)
|
||||||
|
#define SBC_ISR_GPIO_OC SBC_ISR_VECTOR(SBC_GPIO_OC_STAT, SBC_GPIO_OC_STAT_GPIO_OC_Msk, SBC_GPIO_OC_STAT_GPIO_OC_Pos, SBC_GPIO_OC_EVENT)
|
||||||
|
#define SBC_ISR_GPIO_OL SBC_ISR_VECTOR(SBC_GPIO_OL_STAT, SBC_GPIO_OL_STAT_GPIO_OL_Msk, SBC_GPIO_OL_STAT_GPIO_OL_Pos, SBC_GPIO_OL_EVENT)
|
||||||
|
|
||||||
|
|
||||||
|
#endif /*TLE94x1_ISR_H*/
|
||||||
156
cva_bootloader_m0128/src/TLE9461/TLE94x1_SPI.c
Normal file
156
cva_bootloader_m0128/src/TLE9461/TLE94x1_SPI.c
Normal file
@ -0,0 +1,156 @@
|
|||||||
|
/*********************************************************************************************************************
|
||||||
|
* Copyright (c) 2019, Infineon Technologies AG
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Distributed under the Boost Software License, Version 1.0.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person or organization
|
||||||
|
* obtaining a copy of the software and accompanying documentation covered by
|
||||||
|
* this license (the "Software") to use, reproduce, display, distribute,
|
||||||
|
* execute, and transmit the Software, and to prepare derivative works of the
|
||||||
|
* Software, and to permit third-parties to whom the Software is furnished to
|
||||||
|
* do so, all subject to the following:
|
||||||
|
*
|
||||||
|
* The copyright notices in the Software and this entire statement, including
|
||||||
|
* the above license grant, this restriction and the following disclaimer,
|
||||||
|
* must be included in all copies of the Software, in whole or in part, and
|
||||||
|
* all derivative works of the Software, unless such copies or derivative
|
||||||
|
* works are solely in the form of machine-executable object code generated by
|
||||||
|
* a source language processor.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||||
|
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||||
|
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||||
|
* DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*********************************************************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************************//**
|
||||||
|
* @file TLE94x1_SPI.c
|
||||||
|
*
|
||||||
|
* @brief Implementation of all SPI related functions
|
||||||
|
*
|
||||||
|
* @version V1.0.0
|
||||||
|
* @date 15. April 2019
|
||||||
|
* @author Markus Noll / markus.noll@infineon.com
|
||||||
|
* @author Yannek Micha Rixen / Yannek.Rixen@infineon.com
|
||||||
|
*******************************************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* ============================ HEADER FILES ================================ */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
#include "TLE94x1_SPI.h"
|
||||||
|
#include "mcu.h"
|
||||||
|
|
||||||
|
void SPI_PortInit(void);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* ======================= SPI communication functions ====================== */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
|
||||||
|
uint8_t spitxbuf[10],spirxbuf[10];
|
||||||
|
extern McuType mcu;
|
||||||
|
uint8_t SBC_SPI_INIT(void) {
|
||||||
|
SpiDrv_InitCfgType masterCfg;
|
||||||
|
|
||||||
|
SPI_PortInit();
|
||||||
|
|
||||||
|
SpiDrv_GetDefaultConfig(&masterCfg);
|
||||||
|
masterCfg.basicParameters.isMasterNode = true;
|
||||||
|
masterCfg.basicParameters.baudRate = 1000000ul;
|
||||||
|
masterCfg.basicParameters.pcsSelection = SPIDRV_PCS_SEL_PCS0;
|
||||||
|
//masterCfg.basicParameters.clockPolarity = SPIDRV_CLK_POLARITY_IDLE_IN_HIGH;
|
||||||
|
masterCfg.basicParameters.clockPhase = SPIDRV_CLK_PHASE_DATA_SAMPLE_ON_TRAILING_EDGE;
|
||||||
|
|
||||||
|
while(ClockDrv_GetFreq(&mcu.clockDrv, CLOCKDRV_SPI0, &masterCfg.basicParameters.busClockFreq) == false)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
SpiDrv_SetConfig(&mcu.spiDrv0, &masterCfg);
|
||||||
|
|
||||||
|
SpiDrv_SetRxFifoWaterMask(&mcu.spiDrv0, 0);
|
||||||
|
//SpiDrv_SetIsrConfig(&mcu.spiDrv0, SPIDRV_ISR_SRC_RX_DATA, true);
|
||||||
|
|
||||||
|
/* Enable the SPI interrupts */
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
uint16_t SBC_SPI_TRANSFER16(uint8_t Upper, uint8_t Lower) {
|
||||||
|
uint16_t ret;
|
||||||
|
//LPSPI_DRV_SetPcs(LPSPICOM1,LPSPI_PCS0,LPSPI_ACTIVE_LOW);
|
||||||
|
spitxbuf[0] = Upper;
|
||||||
|
spitxbuf[1] = Lower;
|
||||||
|
|
||||||
|
SpiDrv_MasterSyncTransfer(&mcu.spiDrv0,SPIDRV_FRAME_SIZE_BIT_TYPE_BYTE,2,spitxbuf,spirxbuf);
|
||||||
|
//LPSPI_DRV_MasterTransferBlocking(LPSPICOM1,spitxbuf,spirxbuf,2,10);
|
||||||
|
ret = spirxbuf[0];
|
||||||
|
ret <<= 8;
|
||||||
|
ret |= spirxbuf[1];
|
||||||
|
//LPSPI_DRV_SetPcs(LPSPICOM1,LPSPI_PCS0,LPSPI_ACTIVE_HIGH);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/********************CVA SPI DRV**********************/
|
||||||
|
|
||||||
|
void SPI0_Handler(void)
|
||||||
|
{
|
||||||
|
if(SpiDrv_GetStatus(&mcu.spiDrv0, SPIDRV_STATUS_RX_DATA) == true && SpiDrv_GetIsrConfig(&mcu.spiDrv0, SPIDRV_ISR_SRC_RX_DATA) == true)
|
||||||
|
{
|
||||||
|
//spi0IrqCnt++;
|
||||||
|
//uint8_t len = SpiDrv_AsyncReceive(&mcu.spiDrv0, (void *)masterRxBuff, true);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void SPI_PortInit(void)
|
||||||
|
{
|
||||||
|
/* SPI CS */
|
||||||
|
PinsDrv_SetMuxModeSel(&mcu.pta, 12, PINSDRV_MUX_ALT7);
|
||||||
|
/* Strength driver */
|
||||||
|
PortReg_SetPcrDrvStr(mcu.pta.port, 12, 1);
|
||||||
|
/* fast slew rate */
|
||||||
|
PortReg_SetPcrSr(mcu.pta.port, 12, 1);
|
||||||
|
|
||||||
|
/* SPI CLK */
|
||||||
|
PinsDrv_SetMuxModeSel(&mcu.pta, 11, PINSDRV_MUX_ALT7);
|
||||||
|
/* Strength driver */
|
||||||
|
PortReg_SetPcrDrvStr(mcu.pta.port, 11, 1);
|
||||||
|
/* fast slew rate */
|
||||||
|
PortReg_SetPcrSr(mcu.pta.port, 11, 1);
|
||||||
|
|
||||||
|
/* SPI SIN */
|
||||||
|
PinsDrv_SetMuxModeSel(&mcu.pta, 10, PINSDRV_MUX_ALT7);
|
||||||
|
/* Strength driver */
|
||||||
|
PortReg_SetPcrDrvStr(mcu.pta.port, 10, 1);
|
||||||
|
/* fast slew rate */
|
||||||
|
PortReg_SetPcrSr(mcu.pta.port, 10, 1);
|
||||||
|
|
||||||
|
/* SPI SOUT */
|
||||||
|
PinsDrv_SetMuxModeSel(&mcu.pta, 9, PINSDRV_MUX_ALT7);
|
||||||
|
/* Strength driver */
|
||||||
|
PortReg_SetPcrDrvStr(mcu.pta.port, 9, 1);
|
||||||
|
/* fast slew rate */
|
||||||
|
PortReg_SetPcrSr(mcu.pta.port, 9, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
void SPI_TEST_TASK(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
}
|
||||||
95
cva_bootloader_m0128/src/TLE9461/TLE94x1_SPI.h
Normal file
95
cva_bootloader_m0128/src/TLE9461/TLE94x1_SPI.h
Normal file
@ -0,0 +1,95 @@
|
|||||||
|
/*********************************************************************************************************************
|
||||||
|
* Copyright (c) 2019, Infineon Technologies AG
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Distributed under the Boost Software License, Version 1.0.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Boost Software License - Version 1.0 - August 17th, 2003
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person or organization
|
||||||
|
* obtaining a copy of the software and accompanying documentation covered by
|
||||||
|
* this license (the "Software") to use, reproduce, display, distribute,
|
||||||
|
* execute, and transmit the Software, and to prepare derivative works of the
|
||||||
|
* Software, and to permit third-parties to whom the Software is furnished to
|
||||||
|
* do so, all subject to the following:
|
||||||
|
*
|
||||||
|
* The copyright notices in the Software and this entire statement, including
|
||||||
|
* the above license grant, this restriction and the following disclaimer,
|
||||||
|
* must be included in all copies of the Software, in whole or in part, and
|
||||||
|
* all derivative works of the Software, unless such copies or derivative
|
||||||
|
* works are solely in the form of machine-executable object code generated by
|
||||||
|
* a source language processor.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
|
||||||
|
* SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
|
||||||
|
* FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
|
||||||
|
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||||
|
* DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
*********************************************************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
/****************************************************************************************************//**
|
||||||
|
* @file TLE94x1_SPI.h
|
||||||
|
*
|
||||||
|
* @brief Declaration file for TLE94x1 SBC family device SPI functions
|
||||||
|
*
|
||||||
|
* @version V1.0.0
|
||||||
|
* @date 15. April 2019
|
||||||
|
* @author Markus Noll / markus.noll@infineon.com
|
||||||
|
* @author Yannek Micha Rixen / Yannek.Rixen@infineon.com
|
||||||
|
*******************************************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef TLE94x1_SPI_H
|
||||||
|
#define TLE94x1_SPI_H
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* ============================ HEADER FILES ================================ */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ================================================================================ */
|
||||||
|
/* ============================= SPI Functions ============================== */
|
||||||
|
/* ================================================================================ */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief IMPORTANT! THIS METHOD HAS TO BE DEFINED BY THE USER
|
||||||
|
*
|
||||||
|
* The function has to initialze the SPI of the uC and will be called once during SBC_Init().
|
||||||
|
* In case, the SPI hardware is already initialized by some other code before, it can be left blank.
|
||||||
|
*
|
||||||
|
* @retval Method has to return 0 if initialization was successful.
|
||||||
|
*/
|
||||||
|
uint8_t SBC_SPI_INIT(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief IMPORTANT! THIS METHOD HAS TO BE DEFINED BY THE USER
|
||||||
|
*
|
||||||
|
* The function will be called by the library everytime when a SPI communication is needed.
|
||||||
|
* The function proceeds a bidirectional 16-bit transfer to/from the SBC .
|
||||||
|
* As some UCs only supports 8-Bit transfers, the input arguments are split in two 8-bit arguments.
|
||||||
|
* For further implementation details have a look at datasheet chapter 13.1 or at the Arduino-examples.
|
||||||
|
*
|
||||||
|
* @param Upper The first 8 bit to transmit to the SBC.
|
||||||
|
* @param Lower The second 8 bit to transmit to the SBC.
|
||||||
|
* @retval The function will return all 16 bits received from the SBC.
|
||||||
|
* Bit[15:8] are the first 8 bits received (Status-Information-Field).
|
||||||
|
* Bit[7:0] is the data-field transmitted of the SBC.
|
||||||
|
*/
|
||||||
|
uint16_t SBC_SPI_TRANSFER16(uint8_t Upper, uint8_t Lower);
|
||||||
|
|
||||||
|
#endif /* TLE94x1_SPI_H */
|
||||||
@ -29,7 +29,7 @@
|
|||||||
#include "fls.h"
|
#include "fls.h"
|
||||||
#include "private_driver/uds/user/uds_user.h"
|
#include "private_driver/uds/user/uds_user.h"
|
||||||
#include "SEGGER_RTT.h"
|
#include "SEGGER_RTT.h"
|
||||||
|
#include "TLE94x1.h"
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* the defines
|
* the defines
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
@ -94,7 +94,7 @@ static uint32_t sBootloader_Req ;
|
|||||||
|
|
||||||
#pragma location = ".bootloaderInfo"
|
#pragma location = ".bootloaderInfo"
|
||||||
const Bootloade_CfgInfoType sBootloader_Version __attribute__((used, section(".bootloaderInfo"))) = {
|
const Bootloade_CfgInfoType sBootloader_Version __attribute__((used, section(".bootloaderInfo"))) = {
|
||||||
.HWVersion = "HW01",
|
.HWVersion = "DV02",
|
||||||
.BLVersion = "BL0101",
|
.BLVersion = "BL0101",
|
||||||
.bootBuildDate = __DATE__,
|
.bootBuildDate = __DATE__,
|
||||||
.bootBuildTime = __TIME__,
|
.bootBuildTime = __TIME__,
|
||||||
@ -807,7 +807,7 @@ uint8_t flashCfgSecInfo[40] =
|
|||||||
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
|
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
|
||||||
0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
|
0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
|
||||||
};
|
};
|
||||||
|
uint8_t testdata[8] = {0,0,0,0, 0,0,0,0,};
|
||||||
int main(void)
|
int main(void)
|
||||||
{
|
{
|
||||||
uint32_t temp;
|
uint32_t temp;
|
||||||
@ -845,6 +845,18 @@ int main(void)
|
|||||||
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTB, &clockConfig);
|
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTB, &clockConfig);
|
||||||
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTC, &clockConfig);
|
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTC, &clockConfig);
|
||||||
|
|
||||||
|
|
||||||
|
/* Setup the SPI clock */
|
||||||
|
clockConfig.gating = true;
|
||||||
|
clockConfig.source = CLOCKDRV_PLL_DIV;
|
||||||
|
ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_SPI0, &clockConfig);
|
||||||
|
|
||||||
|
uint32_t tTcr = SpiReg_GetTcr((const SpiRegType *)&mcu.spiDrv0.reg);
|
||||||
|
SpiDrv_SetPrescaler(&tTcr,0x02);
|
||||||
|
|
||||||
|
SBC_SPI_INIT();
|
||||||
|
SBC_Init();
|
||||||
|
|
||||||
/* get CAN controller default configuration */
|
/* get CAN controller default configuration */
|
||||||
FlexCanDrv_GetDefaultCfg(&flexCanCfg);
|
FlexCanDrv_GetDefaultCfg(&flexCanCfg);
|
||||||
flexCanCfg.msgNum = sizeof(msgCfgObj) / sizeof(FlexCanDrv_MsgCfgType);
|
flexCanCfg.msgNum = sizeof(msgCfgObj) / sizeof(FlexCanDrv_MsgCfgType);
|
||||||
@ -888,7 +900,20 @@ int main(void)
|
|||||||
gSystick1msEvent = 0;
|
gSystick1msEvent = 0;
|
||||||
gSystick1msCnt++;
|
gSystick1msCnt++;
|
||||||
|
|
||||||
if(gSystick1msCnt >= 500)
|
if (gSystick1msCnt % 10 == 0)
|
||||||
|
{
|
||||||
|
SBC_WD_Trigger();
|
||||||
|
}
|
||||||
|
if (gSystick1msCnt % 1000 == 0)
|
||||||
|
{
|
||||||
|
uint16_t ret = SBC_Read_Command(SBC_WD_CTRL);
|
||||||
|
//SEGGER_RTT_printf(0,"%04d : SBC_WD_CTRL = %x\n",rollingcounter++,ret);
|
||||||
|
testdata[4] = 0x01;
|
||||||
|
testdata[5] = ret>>8;
|
||||||
|
testdata[6] = ret&0xff;
|
||||||
|
FlexCanBoot_TxMessage(UDS_TEXT_TX_MSG_ID,testdata,8);
|
||||||
|
}
|
||||||
|
if(gSystick1msCnt >= 5000)
|
||||||
{
|
{
|
||||||
gSystick1msCnt = 0;
|
gSystick1msCnt = 0;
|
||||||
/* Test Io */
|
/* Test Io */
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user