diff --git a/cva_bootloader_m0128/.vscode/settings.json b/cva_bootloader_m0128/.vscode/settings.json
index 0ce7a27..5e85b8b 100644
--- a/cva_bootloader_m0128/.vscode/settings.json
+++ b/cva_bootloader_m0128/.vscode/settings.json
@@ -16,5 +16,8 @@
             "command": "extension.execute",
             "priority": 4
         }
-    ]
+    ],
+    "files.associations": {
+        "segger_rtt.h": "c"
+    }
 }
\ No newline at end of file
diff --git a/cva_bootloader_m0128/cva_bootloader_m0128.ewp b/cva_bootloader_m0128/cva_bootloader_m0128.ewp
index f873dba..0084e37 100644
--- a/cva_bootloader_m0128/cva_bootloader_m0128.ewp
+++ b/cva_bootloader_m0128/cva_bootloader_m0128.ewp
@@ -362,6 +362,7 @@
                     <state>$PROJ_DIR$\SDK\platform\devices\CVM012x</state>
                     <state>$PROJ_DIR$\src\private_driver</state>
                     <state>$PROJ_DIR$\src\RTT</state>
+                    <state>$PROJ_DIR$\src\TLE9461</state>
                 </option>
                 <option>
                     <name>CCStdIncCheck</name>
@@ -1905,6 +1906,30 @@
                 <name>$PROJ_DIR$\src\RTT\SEGGER_RTT_Syscalls_GCC.c</name>
             </file>
         </group>
+        <group>
+            <name>TLE9461</name>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\SBC_TLE94x1.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1_DEFINES.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1_ISR.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.h</name>
+            </file>
+        </group>
         <file>
             <name>$PROJ_DIR$\src\main.c</name>
         </file>
diff --git a/cva_bootloader_m0128/cva_bootloader_m0128.ewt b/cva_bootloader_m0128/cva_bootloader_m0128.ewt
index df717e6..59f9392 100644
--- a/cva_bootloader_m0128/cva_bootloader_m0128.ewt
+++ b/cva_bootloader_m0128/cva_bootloader_m0128.ewt
@@ -2175,6 +2175,30 @@
                 <name>$PROJ_DIR$\src\RTT\SEGGER_RTT_Syscalls_GCC.c</name>
             </file>
         </group>
+        <group>
+            <name>TLE9461</name>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\SBC_TLE94x1.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1_DEFINES.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1_ISR.h</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\src\TLE9461\TLE94x1_SPI.h</name>
+            </file>
+        </group>
         <file>
             <name>$PROJ_DIR$\src\main.c</name>
         </file>
diff --git a/cva_bootloader_m0128/settings/cva_bootloader_m0128.dnx b/cva_bootloader_m0128/settings/cva_bootloader_m0128.dnx
index 7bb051c..a35edb7 100644
--- a/cva_bootloader_m0128/settings/cva_bootloader_m0128.dnx
+++ b/cva_bootloader_m0128/settings/cva_bootloader_m0128.dnx
@@ -16,13 +16,13 @@
         <MemConfigValue>E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0128.ddf</MemConfigValue>
     </PlDriver>
     <JLinkDriver>
-        <LeaveTargetRunning>_ 0</LeaveTargetRunning>
-        <CStepIntDis>_ 0</CStepIntDis>
         <jlinkResetStyle>12</jlinkResetStyle>
         <jlinkResetStrategy>0</jlinkResetStrategy>
         <TraceBufferSize>0x10000</TraceBufferSize>
         <TraceStallIfFIFOFull>0x0</TraceStallIfFIFOFull>
         <TracePortSize>0x0</TracePortSize>
+        <LeaveTargetRunning>_ 0</LeaveTargetRunning>
+        <CStepIntDis>_ 0</CStepIntDis>
     </JLinkDriver>
     <ArmDriver>
         <EnableCache>0</EnableCache>
@@ -65,17 +65,16 @@
         <Enabled>0</Enabled>
         <ShowSource>0</ShowSource>
     </Trace2>
-    <DisassembleMode>
-        <mode>0</mode>
-    </DisassembleMode>
-    <Breakpoints2>
-        <Bp0>_ 1 "EMUL_CODE" "{$PROJ_DIR$\src\main.c}.652.13" 0 0 1 "" 0 "" 0</Bp0>
-        <Count>1</Count>
-    </Breakpoints2>
     <TermIOLog>
         <LoggingEnabled>_ 0</LoggingEnabled>
         <LogFile>_ ""</LogFile>
     </TermIOLog>
+    <DisassembleMode>
+        <mode>0</mode>
+    </DisassembleMode>
+    <Breakpoints2>
+        <Count>0</Count>
+    </Breakpoints2>
     <Aliases>
         <Count>0</Count>
         <SuppressDialog>0</SuppressDialog>
diff --git a/cva_bootloader_m0128/settings/cva_bootloader_m0128.wsdt b/cva_bootloader_m0128/settings/cva_bootloader_m0128.wsdt
index 2d696a2..ef1af79 100644
--- a/cva_bootloader_m0128/settings/cva_bootloader_m0128.wsdt
+++ b/cva_bootloader_m0128/settings/cva_bootloader_m0128.wsdt
@@ -75,7 +75,7 @@
                     <item>_I0</item>
                 </col-names>
                 <col-widths>
-                    <item>1220</item>
+                    <item>1503</item>
                     <item>20</item>
                 </col-widths>
                 <DebugLogLevel>2</DebugLogLevel>
@@ -87,9 +87,6 @@
                 <NodeDict>
                     <ExpandedNode>cva_bootloader_m0128</ExpandedNode>
                     <ExpandedNode>cva_bootloader_m0128/src</ExpandedNode>
-                    <ExpandedNode>cva_bootloader_m0128/src/drivers</ExpandedNode>
-                    <ExpandedNode>cva_bootloader_m0128/src/drivers/cpu</ExpandedNode>
-                    <ExpandedNode>cva_bootloader_m0128/src/drivers/cpu/startup</ExpandedNode>
                 </NodeDict>
             </IarPane-34063>
             <ControlBarVersion>
@@ -104,11 +101,11 @@
                 <RecentlyUsedMenus>1</RecentlyUsedMenus>
                 <MenuShadows>1</MenuShadows>
                 <ShowAllMenusAfterDelay>1</ShowAllMenusAfterDelay>
-                <CommandsUsage>650000000F00108600000300000048810000010000005F860000020000000F8100000200000020810000010000000C8100003D0000005686000002000000558400000D0000001F810000010000000E8100001400000028970000010000000B81000002000000148600000100000011860000030000004681000001000000</CommandsUsage>
+                <CommandsUsage>6E0000000F00108600000300000048810000010000005F860000020000000F8100000200000020810000010000000C810000460000005686000002000000558400000D0000001F810000010000000E8100001400000028970000010000000B81000002000000148600000100000011860000030000004681000001000000</CommandsUsage>
             </MFCToolBarParameters>
             <CommandManager>
                 <CommandsWithoutImages>3A000D8400000F84000008840000FFFFFFFF54840000328100001C810000098400000C8400003384000078840000118400002DDE00001FDE000020DE000021DE000026DE000028DE000023DE000022DE000024DE000027DE000025DE0000209200002892000029920000379200003892000034920000339200001E9200001D9200002CDE000008800000098000000A8000000B8000000C800000158000000A81000001E80000D6840000D7840000D8840000D9840000DA840000DB840000DC840000DD840000DE840000DF840000E0840000E1840000E9840000EA840000248100004881000053840000</CommandsWithoutImages>
-                <MenuUserImages>3E002497000050010000139700004D010000048400004D0000001097000048010000048100001B050000268100002C0500001E9700004A01000031840000AD01000020810000830100000F8100007B0100000090000058050000299700003A0100003A970000670100000C810000780100000797000089010000269700005E010000159700004C010000098100001D050000068400004F0000001A8F0000060000003497000062010000239700005301000003840000A50100001297000047010000319700005F01000000840000A20100000F9700004601000025920000590000000C9700007001000030840000530000000E84000051000000449200000C0500002B9700003C0100003C970000690100001F810000820100000E8100007A0100001F920000090500002897000039010000399700006601000017970000510100000B8100001E0000002D9200000B050000259700005D010000D18400003001000005840000A7010000149700004F01000002840000A4010000119700004B010000058100001C05000010840000AB01000032840000AE0100000E970000450100002A9700003B0100004C970000380100003B970000680100000A840000A90100000D8100002000000002E100003B05000035E1000045050000279700005401000016970000520100002C9200000A050000</MenuUserImages>
+                <MenuUserImages>3E002497000050010000139700004D01000004840000DA0800001097000048010000048100001B050000268100002C0500001E9700004A01000031840000AD01000020810000830100000F8100007B0100000090000058050000299700003A0100003A970000670100000C810000780100000797000089010000269700005E010000159700004C010000098100001D05000006840000DC0800001A8F0000060000003497000062010000239700005301000003840000A50100001297000047010000319700005F01000000840000A20100000F9700004601000025920000590000000C9700007001000030840000E00800000E840000DE080000449200000C0500002B9700003C0100003C970000690100001F810000820100000E8100007A0100001F920000090500002897000039010000399700006601000017970000510100000B8100002E0900002D9200000B050000259700005D010000D18400003001000005840000A7010000149700004F01000002840000A4010000119700004B010000058100001C05000010840000AB01000032840000AE0100000E970000450100002A9700003B0100004C970000380100003B970000680100000A840000A90100000D8100003009000002E100003B05000035E1000045050000279700005401000016970000520100002C9200000A050000</MenuUserImages>
             </CommandManager>
             <Pane-59393>
                 <ID>0</ID>
@@ -465,7 +462,7 @@
             </DockingManager-256>
             <MFCToolBar-34048>
                 <Name>CMSIS-Pack</Name>
-                <Buttons>00200000010000000100FFFF01001100434D4643546F6F6C426172427574746F6ED184000002000000E6080000FFFEFF00000000000000000000000000010000000100000000000000FFFEFF0A43004D005300490053002D005000610063006B0018000000</Buttons>
+                <Buttons>00200000010000000100FFFF01001100434D4643546F6F6C426172427574746F6ED18400000200000058090000FFFEFF00000000000000000000000000010000000100000000000000FFFEFF0A43004D005300490053002D005000610063006B0018000000</Buttons>
             </MFCToolBar-34048>
             <Pane-34048>
                 <ID>34048</ID>
@@ -482,7 +479,7 @@
             </BasePane-34048>
             <MFCToolBar-34049>
                 <Name>Main</Name>
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             <Pane-34049>
                 <ID>34049</ID>
@@ -500,7 +497,7 @@
         </Desktop>
         <MDIWindows>
             <MDIClientArea-0>
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             </MDIClientArea-0>
         </MDIWindows>
     </WindowStorage>
diff --git a/cva_bootloader_m0128/src/TLE9461/SBC_TLE94x1.h b/cva_bootloader_m0128/src/TLE9461/SBC_TLE94x1.h
new file mode 100644
index 0000000..146c2cc
--- /dev/null
+++ b/cva_bootloader_m0128/src/TLE9461/SBC_TLE94x1.h
@@ -0,0 +1,101 @@
+/**
+ * @cond
+ ***********************************************************************************************************************
+ *
+ * Copyright (c) 2018, Infineon Technologies AG
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
+ * following conditions are met:
+ *
+ *   Redistributions of source code must retain the above copyright notice, this list of conditions and the  following
+ *   disclaimer.
+ *
+ *   Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
+ *   following disclaimer in the documentation and/or other materials provided with the distribution.
+ *
+ *   Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
+ *   products derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE  FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  OF THE
+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ **********************************************************************************************************************/
+#ifndef SBC_TLE94X1_H
+#define SBC_TLE94X1_H
+
+/* XML Version 0.0.6 */
+#define SBC_XML_VERSION (00006)
+
+#define CTRL_BUS_CTRL_0 (0x3) /*decimal 3*/
+
+#define CTRL_BUS_CTRL_3 (0x0) /*decimal 0*/
+
+#define CTRL_GPIO_CTRL (0x4) /*decimal 4*/
+
+#define CTRL_HW_CTRL_0 (0x40) /*decimal 64*/
+
+#define CTRL_HW_CTRL_1 (0x0) /*decimal 0*/
+
+#define CTRL_HW_CTRL_2 (0x40) /*decimal 64*/
+
+#define CTRL_HW_CTRL_3 (0x1) /*decimal 1*/
+
+#define CTRL_M_S_CTRL (0x13) /*decimal 19*/
+
+#define CTRL_PWM_CTRL (0x0) /*decimal 0*/
+
+#define CTRL_PWM_FREQ_CTRL (0x0) /*decimal 0*/
+
+#define CTRL_SWK_BTL0_CTRL (0x50) /*decimal 80*/
+
+#define CTRL_SWK_CAN_FD_CTRL (0x0) /*decimal 0*/
+
+#define CTRL_SWK_CDR_CTRL2 (0x1) /*decimal 1*/
+
+#define CTRL_SWK_CDR_LIMIT_HIGH_CTRL (0x54) /*decimal 84*/
+
+#define CTRL_SWK_CDR_LIMIT_LOW_CTRL (0x4C) /*decimal 76*/
+
+#define CTRL_SWK_DATA_H_CTRL 0x00000000
+
+#define CTRL_SWK_DATA_L_CTRL 0x00000000
+
+#define CTRL_SWK_DLC_CTRL (0x0) /*decimal 0*/
+
+#define CTRL_SWK_ID0_CTRL (0x0) /*decimal 0*/
+
+#define CTRL_SWK_IDx_CTRL 0x00000000
+
+#define CTRL_SWK_MASK_IDx_CTRL 0x00000000
+
+#define CTRL_TIMER_CTRL (0x0) /*decimal 0*/
+
+#define CTRL_WD_CTRL (0x15) /*decimal 21*/
+
+#define CTRL_WK_CTRL_0 (0x0) /*decimal 0*/
+
+#define CTRL_WK_CTRL_1 (0x0) /*decimal 0*/
+
+#define CTRL_WK_PUPD_CTRL (0x0) /*decimal 0*/
+
+#define LED_Math_extendedID (0x1) /*decimal 1*/
+
+#define LED_Math_extendedIDMsk (0x1) /*decimal 1*/
+
+#define MATH_Baudrate (0x2) /*decimal 2*/
+
+#define MATH_CDR_FrequencyMHz (0x28) /*decimal 40*/
+
+#define MATH_DoubleCDRFreq (0x0) /*decimal 0*/
+
+#define MATH_EN_PN (0x1) /*decimal 1*/
+
+#define MATH_PWM_DC (0.0)
+
+#endif /* SBC_TLE94X1_H */
diff --git a/cva_bootloader_m0128/src/TLE9461/TLE9461.icwp b/cva_bootloader_m0128/src/TLE9461/TLE9461.icwp
new file mode 100644
index 0000000..5a043c4
--- /dev/null
+++ b/cva_bootloader_m0128/src/TLE9461/TLE9461.icwp
@@ -0,0 +1,233 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<icwpxml version="2.6.4">
+    <checksum>9e8e9087eecb39921ec31dfccce96b2a2efec664bafe2827aea4ddb51cb86761</checksum>
+    <XmlFile>TLE94x1_Lib.xml</XmlFile>
+    <XmlVersion>V0.0.6</XmlVersion>
+    <ActiveElements>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_2[4]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_1[4]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.WK_PUPD_CTRL[7:6]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <ComboBox>
+            <define>CTRL.PWM_FREQ_CTRL[1:0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <DoubleSpinBox>
+            <define>MATH.PWM_DC</define>
+            <value>0</value>
+            <dispValue>0.0</dispValue>
+        </DoubleSpinBox>
+        <CheckBox>
+            <define>CTRL.WK_CTRL_1[7]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_0[0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_0[5]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.BUS_CTRL_3[4]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.WK_PUPD_CTRL[1:0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>CTRL.WK_CTRL_0[6]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.TIMER_CTRL[3:0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <ComboBox>
+            <define>CTRL.TIMER_CTRL[6:4]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_1[5]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_3[2]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ButtonGroup>
+            <define>CTRL.WD_CTRL[5]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ButtonGroup>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_0[2]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.HW_CTRL_2[7:5]</define>
+            <value>2</value>
+            <dispValue>2</dispValue>
+        </ComboBox>
+        <ComboBox>
+            <define>CTRL.HW_CTRL_2[3:2]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <ComboBox>
+            <define>CTRL.SWK_CAN_FD_CTRL[3:1]</define>
+            <value>2</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <ComboBox>
+            <define>MATH.Baudrate</define>
+            <value>2</value>
+            <dispValue>2</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>CTRL.SWK_ID0_CTRL[0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <LineEdit>
+            <define>CTRL.SWK_MASK_IDx_CTRL</define>
+            <value>0x00000000</value>
+            <dispValue>0</dispValue>
+        </LineEdit>
+        <ComboBox>
+            <define>CTRL.SWK_DLC_CTRL[3:0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </ComboBox>
+        <LineEdit>
+            <define>CTRL.SWK_DATA_H_CTRL</define>
+            <value>0x00000000</value>
+            <dispValue>0x00000000</dispValue>
+        </LineEdit>
+        <LineEdit>
+            <define>CTRL.SWK_DATA_L_CTRL</define>
+            <value>0x00000000</value>
+            <dispValue>0x00000000</dispValue>
+        </LineEdit>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_1[3]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_2[0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.M_S_CTRL[4:3]</define>
+            <value>2</value>
+            <dispValue>2</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>MATH.EN_PN</define>
+            <value>1</value>
+            <dispValue>1</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.HW_CTRL_3[1:0]</define>
+            <value>1</value>
+            <dispValue>1</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_0[6]</define>
+            <value>1</value>
+            <dispValue>1</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.SWK_CAN_FD_CTRL[0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>MATH.DoubleCDRFreq</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <LineEdit>
+            <define>CTRL.SWK_IDx_CTRL</define>
+            <value>0x00000000</value>
+            <dispValue>0</dispValue>
+        </LineEdit>
+        <ComboBox>
+            <define>CTRL.GPIO_CTRL[2:0]</define>
+            <value>4</value>
+            <dispValue>4</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>CTRL.WK_CTRL_1[0]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.WK_CTRL_1[5]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.WK_CTRL_0[2];CTRL.WD_CTRL[6]</define>
+            <value>1</value>
+            <dispValue>1</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.WD_CTRL[4]</define>
+            <value>1</value>
+            <dispValue>1</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.WD_CTRL[2:0]</define>
+            <value>5</value>
+            <dispValue>5</dispValue>
+        </ComboBox>
+        <ComboBox>
+            <define>CTRL.M_S_CTRL[1:0]</define>
+            <value>3</value>
+            <dispValue>3</dispValue>
+        </ComboBox>
+        <CheckBox>
+            <define>CTRL.HW_CTRL_1[7]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <CheckBox>
+            <define>CTRL.M_S_CTRL[2]</define>
+            <value>0</value>
+            <dispValue>0</dispValue>
+        </CheckBox>
+        <ComboBox>
+            <define>CTRL.BUS_CTRL_0[2:0]</define>
+            <value>3</value>
+            <dispValue>3</dispValue>
+        </ComboBox>
+    </ActiveElements>
+</icwpxml>
\ No newline at end of file
diff --git a/cva_bootloader_m0128/src/TLE9461/TLE94x1.c b/cva_bootloader_m0128/src/TLE9461/TLE94x1.c
new file mode 100644
index 0000000..73428d2
--- /dev/null
+++ b/cva_bootloader_m0128/src/TLE9461/TLE94x1.c
@@ -0,0 +1,591 @@
+/*********************************************************************************************************************
+ * Copyright (c) 2019, Infineon Technologies AG
+ *
+ * 
+ * Distributed under the Boost Software License, Version 1.0.
+ * 
+ * 
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ * 
+ * Permission is hereby granted, free of charge, to any person or organization
+ * obtaining a copy of the software and accompanying documentation covered by
+ * this license (the "Software") to use, reproduce, display, distribute,
+ * execute, and transmit the Software, and to prepare derivative works of the
+ * Software, and to permit third-parties to whom the Software is furnished to
+ * do so, all subject to the following:
+ * 
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer,
+ * must be included in all copies of the Software, in whole or in part, and
+ * all derivative works of the Software, unless such copies or derivative
+ * works are solely in the form of machine-executable object code generated by
+ * a source language processor.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ *********************************************************************************************************************/
+
+
+/****************************************************************************************************//**
+ * @file         TLE94x1.c
+ *
+ * @brief        Implementation of main library functions
+ *
+ * @version     V1.0.1
+ * @date        05. October 2020
+ * @author      Markus Noll / markus.noll@infineon.com
+ * @author      Yannek Micha Rixen / Yannek.Rixen@infineon.com
+ ********************************************************************************************************/
+
+
+
+/* ================================================================================ */
+/* ============================   HEADER FILES     ================================ */
+/* ================================================================================ */
+
+#include "TLE94x1.h"
+#include "SBC_TLE94x1.h"
+#include <stdio.h>
+
+
+/* ================================================================================ */
+/* ==============================   Variables     ================================= */
+/* ================================================================================ */
+
+
+/* --------------------------------  ISR Handling --------------------------------- */
+
+static    SBC_Func_Callback                 SBC_ISR_Callbacks[30];
+static    uint32_t                          SBC_ISR_Vectors[30];
+static    uint8_t                           SBC_ISR_ReadOutRegs[30];
+static    uint8_t                           SBC_ISR_ReadOutVals[30];
+static    uint8_t                           SBC_RegisteredCallbacks = 0;
+static    uint8_t                           SBC_RegisteredRedoutRegs = 0;
+
+
+
+/* ================================================================================ */
+/* ===========================   Library Functions     ============================ */
+/* ================================================================================ */
+
+
+/* --------------------------------  Main Functions ------------------------------- */
+
+
+SBC_ErrorCode SBC_WD_Trigger(void) {
+    /* Read WD config out of SBC and write back to trigger WD */
+    uint8_t WD_Data = (uint8_t)SBC_Read_Command(SBC_WD_CTRL);
+    return SBC_Write_Reg(SBC_WD_CTRL, WD_Data, NULL);
+}
+
+
+uint16_t SBC_Read_Command(uint8_t SBC_Reg) {
+    /* Read and return data - Bit[15:8] = Status Information Field - Bit [7:0] Register data */
+    return  SBC_SPI_TRANSFER16(SBC_Read_Mask & SBC_Reg, 0x00U);
+}
+
+
+uint8_t SBC_Read_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos) {
+    uint8_t data = ((uint8_t)SBC_Read_Command(SBC_Reg)) & 0xFFU;
+    return (data & SBC_FieldMsk) >> SBC_FieldPos;
+}
+
+
+SBC_ErrorCode SBC_Write_Reg(uint8_t SBC_Reg, uint8_t SBC_Val, uint16_t * returnval) {
+    SBC_ErrorCode errCode;
+    uint16_t returndata = SBC_SPI_TRANSFER16(SBC_Write_Bit | SBC_Reg, SBC_Val);
+    if(returnval != NULL) {
+        *returnval = returndata;
+    }
+
+    errCode.SBC_Register = SBC_Reg;
+    errCode.flippedBitsMask = ((uint8_t)SBC_Read_Command(SBC_Reg)) ^ SBC_Val;
+    errCode.expectedValue = SBC_Val;
+    return errCode;
+}
+
+
+SBC_ErrorCode SBC_Write_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos, uint8_t SBC_FieldVal, uint16_t * returnval) {
+    SBC_ErrorCode errCode;
+
+    /* Read data out of register to be manipulated */
+    uint16_t returndata = SBC_Read_Command(SBC_Reg);
+    if(returnval != NULL) {
+        *returnval = returndata;
+    }
+    uint8_t data = (uint8_t)returndata; 
+
+    /* Set the used bit field to all 0 */
+    data &= ~(SBC_FieldMsk);
+
+    /* Configure new data to bit field */
+    data |= (SBC_FieldVal << SBC_FieldPos);
+
+    (void)SBC_SPI_TRANSFER16(SBC_Write_Bit | SBC_Reg, data);
+
+    errCode.SBC_Register = SBC_Reg;
+    errCode.expectedValue = (SBC_FieldVal << SBC_FieldPos);
+    uint8_t actualValue = ((uint8_t)SBC_Read_Command(SBC_Reg)) & SBC_FieldMsk;
+    errCode.flippedBitsMask = errCode.expectedValue ^ actualValue;
+    return errCode;
+}
+
+
+SBC_ErrorCode SBC_Init(void) {
+    SBC_ErrorCode errCode;
+    uint8_t WD_Checksum = CTRL_WD_CTRL;
+    uint8_t WD_CTRL = CTRL_WD_CTRL;
+    uint8_t SWK_ID3_CTRL, SWK_ID2_CTRL, SWK_ID1_CTRL, SWK_ID0_CTRL;
+    uint8_t SWK_MASK_ID3_CTRL, SWK_MASK_ID2_CTRL, SWK_MASK_ID1_CTRL, SWK_MASK_ID0_CTRL;
+    uint8_t SWK_CAN_FD_CTRL = CTRL_SWK_CAN_FD_CTRL;
+
+    /* Calculate checksum */
+    WD_Checksum = WD_Checksum ^ WD_Checksum >> 4;
+    WD_Checksum = WD_Checksum ^ WD_Checksum >> 2;
+    WD_Checksum = WD_Checksum ^ WD_Checksum >> 1;
+
+    if((WD_Checksum & 1) > 0) {
+        /* Set parity bit */
+        WD_CTRL = CTRL_WD_CTRL | 0x80U;
+    }
+
+    /* Check if ID is configured to be extended */
+    if((CTRL_SWK_ID0_CTRL & SBC_SWK_ID0_CTRL_IDE_Msk) == SBC_IDE_EXTENDED) {
+        /* extended ID */
+        uint32_t SWK_ID_CTRL = CTRL_SWK_IDx_CTRL << 3;
+        uint32_t SWK_MASK_ID_CTRL = CTRL_SWK_MASK_IDx_CTRL << 3;
+
+        SWK_ID3_CTRL = (uint8_t)(SWK_ID_CTRL >> 24);
+        SWK_ID2_CTRL = (uint8_t)(SWK_ID_CTRL >> 16);
+        SWK_ID1_CTRL = (uint8_t)(SWK_ID_CTRL >> 8);
+        SWK_ID0_CTRL = (((uint8_t)(SWK_ID_CTRL >> 1)) & SBC_SWK_ID0_CTRL_ID4_0_Msk) | SBC_IDE_EXTENDED;
+        SWK_MASK_ID3_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 24);
+        SWK_MASK_ID2_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 16);
+        SWK_MASK_ID1_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 8);
+        SWK_MASK_ID0_CTRL = (((uint8_t)(SWK_MASK_ID_CTRL >> 1)) & SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk);
+    } else {
+        /* Standard length ID */
+        uint16_t SWK_ID_CTRL = CTRL_SWK_IDx_CTRL;
+        uint32_t SWK_MASK_ID_CTRL = CTRL_SWK_MASK_IDx_CTRL;
+
+        SWK_ID3_CTRL = (uint8_t)(SWK_ID_CTRL >> 3);
+        SWK_ID2_CTRL = (uint8_t)(SWK_ID_CTRL << 5);
+        SWK_ID1_CTRL = 0x00U;
+        SWK_ID0_CTRL = 0x00U;
+        SWK_MASK_ID3_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 3);
+        SWK_MASK_ID2_CTRL = (uint8_t)(SWK_MASK_ID_CTRL << 5);
+        SWK_MASK_ID1_CTRL = 0x00U;
+        SWK_MASK_ID0_CTRL = 0x00U;
+    }
+
+    /* DIS_ERR_CNT is set only when FD Tolerance is set. */
+    if((CTRL_SWK_CAN_FD_CTRL & SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk) == SBC_CAN_FD_EN_ENABLED) {
+        SWK_CAN_FD_CTRL &= SBC_DIS_ERR_CNT_DISABLED << SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos;
+    }
+
+    /* Describes initialization sequence */
+    uint8_t initSequence[39][2] = {
+        {SBC_WD_CTRL, WD_CTRL},
+        {SBC_M_S_CTRL, CTRL_M_S_CTRL},
+        {SBC_HW_CTRL_0, CTRL_HW_CTRL_0},
+        {SBC_HW_CTRL_3, CTRL_HW_CTRL_3},
+        {SBC_BUS_CTRL_3, CTRL_BUS_CTRL_3},
+        {SBC_WK_CTRL_0, CTRL_WK_CTRL_0},
+        {SBC_WK_CTRL_1, CTRL_WK_CTRL_1},
+        {SBC_WK_PUPD_CTRL, CTRL_WK_PUPD_CTRL},
+        {SBC_TIMER_CTRL, CTRL_TIMER_CTRL},
+        {SBC_PWM_FREQ_CTRL, CTRL_PWM_FREQ_CTRL}, /* The desired duty cycle should be set first before GPIO is enabled as PWM HS or PWM LS. */
+        {SBC_PWM_CTRL, CTRL_PWM_CTRL},
+        {SBC_GPIO_CTRL, CTRL_GPIO_CTRL},
+        {SBC_HW_CTRL_1, CTRL_HW_CTRL_1}, /* May lock configuration (CFG_LOCK_0) */
+        {SBC_HW_CTRL_2, CTRL_HW_CTRL_2}, /* May lock configuration (CFG_LOCK_1) */
+        {SBC_BUS_CTRL_0, CTRL_BUS_CTRL_0},
+
+        /* -------------------------- SELECTIVE WAKE REGISTERS --------------------------- */
+
+        /* Configuring CDR */
+        {SBC_SWK_CDR_CTRL2, CTRL_SWK_CDR_CTRL2},
+        {SBC_SWK_BTL0_CTRL, CTRL_SWK_BTL0_CTRL},
+        {SBC_SWK_CDR_LIMIT_HIGH_CTRL, CTRL_SWK_CDR_LIMIT_HIGH_CTRL},
+        {SBC_SWK_CDR_LIMIT_LOW_CTRL, CTRL_SWK_CDR_LIMIT_LOW_CTRL},
+        {SBC_SWK_CDR_CTRL1, (SBC_SEL_FILT_TC16 << SBC_SWK_CDR_CTRL1_SEL_FILT_Pos) | (SBC_CDR_EN_ENABLED << SBC_SWK_CDR_CTRL1_CDR_EN_Pos)},
+
+
+        /* Set ID */
+        {SBC_SWK_ID3_CTRL, SWK_ID3_CTRL},
+        {SBC_SWK_ID2_CTRL, SWK_ID2_CTRL},
+        {SBC_SWK_ID1_CTRL, SWK_ID1_CTRL},
+        {SBC_SWK_ID0_CTRL, SWK_ID0_CTRL},
+
+        /* Set Mask */
+        {SBC_SWK_MASK_ID3_CTRL, SWK_MASK_ID3_CTRL},
+        {SBC_SWK_MASK_ID2_CTRL, SWK_MASK_ID2_CTRL},
+        {SBC_SWK_MASK_ID1_CTRL, SWK_MASK_ID1_CTRL},
+        {SBC_SWK_MASK_ID0_CTRL, SWK_MASK_ID0_CTRL},
+
+        /* Set Data */
+        {SBC_SWK_DATA7_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 24)},
+        {SBC_SWK_DATA6_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 16)},
+        {SBC_SWK_DATA5_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 8)},
+        {SBC_SWK_DATA4_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 0)},
+        {SBC_SWK_DATA3_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 24)},
+        {SBC_SWK_DATA2_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 16)},
+        {SBC_SWK_DATA1_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 8)},
+        {SBC_SWK_DATA0_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 0)},
+
+         /* Set DLC */
+        {SBC_SWK_DLC_CTRL, CTRL_SWK_DLC_CTRL},
+
+        {SBC_SWK_CAN_FD_CTRL, SWK_CAN_FD_CTRL},
+
+        /* End Configuration */
+        {0x00U, 0x00U}
+    };
+
+    /* Call SPI Init */
+    if(SBC_SPI_INIT() != 0) {
+        errCode.SBC_Register = 0x00;
+        errCode.flippedBitsMask = 0xFF;
+        errCode.expectedValue = 0x00;
+        return errCode;
+    };
+
+    uint8_t i = 0;
+
+    /* Write all initialization items to Lite SBC */
+    while(initSequence[i][0] != 0x00U || initSequence[i][1] != 0x00U) {
+        errCode = SBC_Write_Reg(initSequence[i][0], initSequence[i][1], NULL);
+        if(errCode.flippedBitsMask > 0) {
+            return errCode;
+        }
+        i++;
+    }
+
+    errCode.SBC_Register = 0x00;
+    errCode.flippedBitsMask = 0x00;
+    errCode.expectedValue = 0x00;
+    return errCode;
+}
+
+
+
+/* --------------------------------  ISR Functions -------------------------------- */
+
+
+void SBC_Register_Callback(uint32_t ISR_Vector, void (*Callback_Handler)(uint8_t callbackHandler)) {
+    /* Save callback */
+    SBC_ISR_Callbacks[SBC_RegisteredCallbacks] = Callback_Handler;
+
+    /* Save callback vector */
+    SBC_ISR_Vectors[SBC_RegisteredCallbacks] = ISR_Vector;
+
+    /* Check if the register will be readout already to avoid double-readout later */
+    uint8_t RegFound = 0;
+    for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) {
+        if (SBC_ISR_ReadOutRegs[i] == (ISR_Vector >> 24)) {
+            RegFound = 1;
+        }
+    }
+
+    /* If readout status-reg was not found, register in the readout list */
+    if (RegFound == 0) {
+        SBC_ISR_ReadOutRegs[SBC_RegisteredRedoutRegs] = (uint8_t)(ISR_Vector >> 24);
+        SBC_RegisteredRedoutRegs++;
+    }
+
+    SBC_RegisteredCallbacks++;
+}
+
+
+SBC_ErrorCode SBC_ISR(void) {
+    SBC_ErrorCode errCode;
+
+    /* Readout all registered status-registers */
+    for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) {
+        SBC_ISR_ReadOutVals[i] = (uint8_t) SBC_Read_Command(SBC_ISR_ReadOutRegs[i]);
+    }
+
+    /* Handle all interrupts */
+    for (uint8_t i = 0; i < SBC_RegisteredCallbacks; i++) {
+        /* Decode ISR Vector */
+        uint8_t Compare = (uint8_t)SBC_ISR_Vectors[i];
+        uint8_t FieldPos = (uint8_t)(SBC_ISR_Vectors[i] >> 8);
+        uint8_t FieldMsk = (uint8_t)(SBC_ISR_Vectors[i] >> 16);
+        uint8_t RegAddr = (uint8_t)(SBC_ISR_Vectors[i] >> 24);
+
+        /* Readback of associated status-bit */
+        uint8_t ReadBack = 0;
+        for (uint8_t j = 0; j < SBC_RegisteredRedoutRegs; j++) {
+            if (SBC_ISR_ReadOutRegs[j] == RegAddr) {
+                ReadBack = SBC_ISR_ReadOutVals[j];
+                break;
+          }
+        }
+
+        /* If compare-values matched -> proceed callback and clear field */
+        if (((ReadBack & FieldMsk) >> FieldPos) == Compare) {
+            SBC_ISR_Callbacks[i](ReadBack);
+        }
+    }
+
+    /* Clear all ISR related registers */
+    for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) {
+        errCode = SBC_Write_Reg(SBC_ISR_ReadOutRegs[i], 0x00U, NULL);
+        if(errCode.flippedBitsMask > 0) {
+            return errCode;
+        }
+    }
+
+    errCode.SBC_Register = 0x00U;
+    errCode.flippedBitsMask = 0x00U;
+    errCode.expectedValue = 0x00U;
+    return errCode;
+}
+
+
+
+/* --------------------------------  API Calls  ----------------------------------- */
+
+SBC_ErrorCode SBC_Mode_Normal(void) {
+    return SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_NORMAL, NULL);
+}
+
+
+SBC_ErrorCode SBC_Mode_Stop(void) {
+    return SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_STOP, NULL);
+}
+
+
+SBC_ErrorCode SBC_Mode_Sleep(void) {
+    uint8_t registerReadOut;
+
+    SBC_ErrorCode errCode;
+
+    /* If CAN PN is configured */
+    if(MATH_EN_PN != 0) {
+
+        /* Reading value of SWK_STAT. */
+        registerReadOut = (uint8_t)SBC_Read_Command(SBC_SWK_STAT);
+
+        /* CAN Protocol Handler in sync? The selective wake routine should be aborted if sync is not set. Note: for SYNC to be set the transceiver must have been in Normal Mode and a valid CAN communication must have been sent on the bus by any node. */
+        if((registerReadOut & SBC_SWK_STAT_SYNC_Msk) >> SBC_SWK_STAT_SYNC_Pos != SBC_SYNC_VALID_FRAME_RECEIVED) {
+            errCode.SBC_Register = SBC_SWK_STAT;
+            errCode.flippedBitsMask = SBC_SWK_STAT_SYNC_Msk;
+            errCode.expectedValue = SBC_SYNC_VALID_FRAME_RECEIVED << SBC_SWK_STAT_SYNC_Pos;
+            return errCode;
+        }
+
+        /* Set SWK Configuration valid */
+        errCode = SBC_Write_RegField(SBC_SWK_CTRL, SBC_SWK_CTRL_CFG_VAL_Msk, SBC_SWK_CTRL_CFG_VAL_Pos, SBC_CFG_VAL_VALID, NULL);
+        if(errCode.flippedBitsMask > 0) {
+            return errCode;
+        }
+		
+		
+		/* Clear SYSERR bit */
+        errCode = SBC_Write_RegField(SBC_BUS_STAT, SBC_BUS_STAT_SYSERR_Msk, SBC_BUS_STAT_SYSERR_Pos, 0x00, NULL);
+        if(errCode.flippedBitsMask > 0) {
+            return errCode;
+        }	
+
+        /* Set CAN Mode to off and once again to desired configuration */
+        errCode = SBC_Write_Reg(SBC_BUS_CTRL_0, 0x03, NULL);
+        if(errCode.flippedBitsMask > 0) {
+            return errCode;
+        }
+		
+        errCode = SBC_Write_Reg(SBC_BUS_CTRL_0, CTRL_BUS_CTRL_0, NULL);
+        if(errCode.flippedBitsMask > 0) {
+            return errCode;
+        }
+
+		 /* Check SWK_STAT for SYNC == 1 && SWK_SET == 1 && WUF == 0 && WUP == 0. Ignore CANSIL */
+		registerReadOut = (uint8_t)SBC_Read_Command(SBC_SWK_STAT);
+        if(        ((SBC_SWK_STAT_SYNC_Msk & registerReadOut) == SBC_SWK_STAT_SYNC_Msk)
+            && ((SBC_SWK_STAT_SWK_SET_Msk & registerReadOut) == SBC_SWK_STAT_SWK_SET_Msk)
+            && ((SBC_SWK_STAT_WUP_Msk & registerReadOut) != SBC_SWK_STAT_WUP_Msk)
+            && ((SBC_SWK_STAT_WUF_Msk & registerReadOut) != SBC_SWK_STAT_WUF_Msk)) {
+        /* Empty */
+        } else {
+            errCode.SBC_Register = SBC_SWK_STAT;
+            errCode.expectedValue = 0b01000100U;
+            errCode.flippedBitsMask = errCode.expectedValue ^ registerReadOut;
+            return errCode;
+        }
+		
+		
+		
+    }
+
+	
+
+    /* Clear Wake Status Registers, so that SBC can sleep. */
+    errCode = SBC_Write_Reg(SBC_WK_STAT_0, 0x00, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+    errCode = SBC_Write_Reg(SBC_WK_STAT_1, 0x00, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+	
+    /* Select sleep mode */
+    (void)SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_SLEEP, NULL);
+    registerReadOut = (uint8_t)SBC_Read_Command(SBC_M_S_CTRL);
+
+    /* This piece of code is ideally never reached as the microcontroller should be already turned off then */
+    if(registerReadOut != 0) {
+        errCode.SBC_Register = SBC_M_S_CTRL;
+        errCode.flippedBitsMask = registerReadOut;
+        errCode.expectedValue = 0x00U;
+        return errCode;
+    }
+
+    errCode.SBC_Register = 0x00U;
+    errCode.flippedBitsMask = 0x00U;
+    errCode.expectedValue = 0x00U;
+    return errCode;
+}
+
+
+SBC_ErrorCode SBC_Set_DutyCycle_PWM (uint8_t PWM_DC) {
+    return SBC_Write_Reg(SBC_PWM_CTRL, PWM_DC, NULL);
+}
+
+
+SBC_ErrorCode SBC_Set_Timer_On (uint8_t OnTime) {
+    return SBC_Write_RegField(SBC_TIMER_CTRL, SBC_TIMER_CTRL_TIMER_ON_Msk, SBC_TIMER_CTRL_TIMER_ON_Pos, OnTime, NULL);
+}
+
+
+SBC_ErrorCode SBC_Set_Timer_Period (uint8_t Period) {
+    return SBC_Write_RegField(SBC_TIMER_CTRL, SBC_TIMER_CTRL_TIMER_PER_Msk, SBC_TIMER_CTRL_TIMER_PER_Pos, Period, NULL);
+}
+
+
+SBC_ErrorCode SBC_FO_Test_On(void) {
+    return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_FO_ON_Msk, SBC_HW_CTRL_0_FO_ON_Pos, SBC_FO_ON_ACTIVE, NULL);
+}
+
+
+SBC_ErrorCode SBC_FO_Test_Off(void) {
+    return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_FO_ON_Msk, SBC_HW_CTRL_0_FO_ON_Pos, SBC_FO_ON_NOT_ACTIVE, NULL);
+}
+
+
+SBC_ErrorCode SBC_CP_On(void) {
+    return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_CP_EN_Msk, SBC_HW_CTRL_0_CP_EN_Pos, SBC_CP_EN_ON, NULL);
+}
+
+
+SBC_ErrorCode SBC_CP_Off(void) {
+    return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_CP_EN_Msk, SBC_HW_CTRL_0_CP_EN_Pos, SBC_CP_EN_OFF, NULL);
+}
+
+
+SBC_ErrorCode SBC_WK_MEAS_On(void) {
+    return SBC_Write_RegField(SBC_WK_CTRL_1, SBC_WK_CTRL_1_WK_MEAS_Msk, SBC_WK_CTRL_1_WK_MEAS_Pos, SBC_WK_MEAS_WK_AS_VOLTAGESENSING, NULL);
+}
+
+
+SBC_ErrorCode SBC_WK_MEAS_Off(void) {
+    return SBC_Write_RegField(SBC_WK_CTRL_1, SBC_WK_CTRL_1_WK_MEAS_Msk, SBC_WK_CTRL_1_WK_MEAS_Pos, SBC_WK_MEAS_WK_AS_WAKEUP, NULL);
+}
+
+
+SBC_ErrorCode SBC_TIMER_WK_EN_On(void) {
+    return SBC_Write_RegField(SBC_WK_CTRL_0, SBC_WK_CTRL_0_TIMER_WK_EN_Msk, SBC_WK_CTRL_0_TIMER_WK_EN_Pos, WK_CTRL_0_TIMER_WK_EN_WAKESOURCE, NULL);
+}
+
+
+SBC_ErrorCode SBC_TIMER_WK_EN_Off(void) {
+    return SBC_Write_RegField(SBC_WK_CTRL_0, SBC_WK_CTRL_0_TIMER_WK_EN_Msk, SBC_WK_CTRL_0_TIMER_WK_EN_Pos, WK_CTRL_0_TIMER_WK_EN_WAKEUP_DISABLED, NULL);
+}
+
+
+uint16_t SBC_SYS_STAT_Read(void) {
+    uint16_t systemStatus = 0;
+    uint16_t returndata = SBC_Read_Command(SBC_SYS_STATUS_CTRL_0);
+    systemStatus = returndata & 0x00FFU;
+    systemStatus |= SBC_Read_Command(SBC_SYS_STATUS_CTRL_1) << 8;
+    return systemStatus;
+}
+
+
+SBC_ErrorCode SBC_SYS_STAT_Write(uint16_t SystemStatus) {
+    SBC_ErrorCode errCode;
+
+    /* Write lower bits */
+    errCode = SBC_Write_Reg(SBC_SYS_STATUS_CTRL_0, (uint8_t)SystemStatus, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+
+    /* Write higher bits */
+    return SBC_Write_Reg(SBC_SYS_STATUS_CTRL_1, (uint8_t)(SystemStatus >> 8), NULL);
+}
+
+
+SBC_ErrorCode SBC_Lock_Configuration(void) {
+    SBC_ErrorCode errCode;
+
+    /* Lock CP_EN and GPIO cannot be modified */
+    errCode = SBC_Write_RegField(SBC_HW_CTRL_1, SBC_HW_CTRL_1_CFG_LOCK_0_Msk, SBC_HW_CTRL_1_CFG_LOCK_0_Pos, SBC_CFG_LOCK_0_LOCKED, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+
+    /* Lock Bits with bit type ‘rwl’ (except CP_EN and GPIO) until next device power-up. */
+    errCode = SBC_Write_RegField(SBC_HW_CTRL_2, SBC_HW_CTRL_2_CFG_LOCK_1_Msk, SBC_HW_CTRL_2_CFG_LOCK_1_Pos, SBC_CFG_LOCK_1_LOCKED, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+
+    errCode.SBC_Register = 0x00;
+    errCode.flippedBitsMask = 0x00;
+    errCode.expectedValue = 0x00;
+    return errCode;
+}
+
+
+SBC_ErrorCode SBC_Unlock_Configuration(void) {
+    SBC_ErrorCode errCode;
+
+    /* Unlock CP_EN and GPIO configuration. */
+    errCode = SBC_Write_RegField(SBC_HW_CTRL_1, SBC_HW_CTRL_1_CFG_LOCK_0_Msk, SBC_HW_CTRL_1_CFG_LOCK_0_Pos, SBC_CFG_LOCK_0_NOTLOCKED, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+
+    /* Unlock Bits with bit type ‘rwl’ (except CP_EN and GPIO). */
+    errCode = SBC_Write_RegField(SBC_HW_CTRL_2, SBC_HW_CTRL_2_CFG_LOCK_1_Msk, SBC_HW_CTRL_2_CFG_LOCK_1_Pos, SBC_CFG_LOCK_1_NOTLOCKED, NULL);
+    if(errCode.flippedBitsMask > 0) {
+        return errCode;
+    }
+
+    errCode.SBC_Register = 0x00;
+    errCode.flippedBitsMask = 0x00;
+    errCode.expectedValue = 0x00;
+    return errCode;
+}
+
+SBC_ErrorCode SBC_Clear_Wake_Status(void) {
+    SBC_ErrorCode errCode = SBC_Write_Reg(SBC_WK_STAT_0, 0x00, NULL);
+    if(errCode.flippedBitsMask != 0) {
+        return errCode;
+    }
+    errCode = SBC_Write_Reg(SBC_WK_STAT_1, 0x00, NULL);
+    if(errCode.flippedBitsMask != 0) {
+        return errCode;
+    }
+    errCode.SBC_Register = 0x00;
+    errCode.flippedBitsMask = 0x00;
+    errCode.expectedValue = 0x00;
+    return errCode;
+}
diff --git a/cva_bootloader_m0128/src/TLE9461/TLE94x1.h b/cva_bootloader_m0128/src/TLE9461/TLE94x1.h
new file mode 100644
index 0000000..a434389
--- /dev/null
+++ b/cva_bootloader_m0128/src/TLE9461/TLE94x1.h
@@ -0,0 +1,393 @@
+/*********************************************************************************************************************
+ * Copyright (c) 2019, Infineon Technologies AG
+ *
+ * 
+ * Distributed under the Boost Software License, Version 1.0.
+ * 
+ * 
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ * 
+ * Permission is hereby granted, free of charge, to any person or organization
+ * obtaining a copy of the software and accompanying documentation covered by
+ * this license (the "Software") to use, reproduce, display, distribute,
+ * execute, and transmit the Software, and to prepare derivative works of the
+ * Software, and to permit third-parties to whom the Software is furnished to
+ * do so, all subject to the following:
+ * 
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer,
+ * must be included in all copies of the Software, in whole or in part, and
+ * all derivative works of the Software, unless such copies or derivative
+ * works are solely in the form of machine-executable object code generated by
+ * a source language processor.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ *********************************************************************************************************************/
+
+
+/****************************************************************************************************//**
+ * @file        TLE94x1.h
+ *
+ * @brief       Main header declaration file for TLE94x1 SBC family device
+ *
+ * @version     V1.0.0
+ * @date        15. April 2019
+ * @author      Markus Noll / markus.noll@infineon.com
+ * @author      Yannek Micha Rixen / Yannek.Rixen@infineon.com
+ *******************************************************************************************************/
+
+
+
+ 
+#ifndef TLE94x1_H
+#define TLE94x1_H
+ 
+
+
+
+
+
+/* ================================================================================ */
+/* ============================   HEADER FILES     ================================ */
+/* ================================================================================ */ 
+
+
+ 
+#include "TLE94x1_DEFINES.h"
+#include "TLE94x1_ISR.h"
+#include "TLE94x1_SPI.h"
+#include <stdint.h>
+
+
+
+
+/* ================================================================================ */
+/* ================================   MACROS     ================================== */
+/* ================================================================================ */ 
+
+
+/**
+ * @def     SBC_Write_Bit
+ * 
+ * @brief   This bit has to be set in order to write to a register.
+ */
+#define SBC_Write_Bit   (0x80U)
+
+/**
+ * @def     SBC_Read_Mask
+ * 
+ * @brief   A mask to prevent the user from accidentally writing to a register.
+ */
+#define SBC_Read_Mask   (0x7FU)
+
+
+
+
+/* ================================================================================ */
+/* ===========================   Library Functions     ============================ */
+/* ================================================================================ */ 
+
+struct __SBC_ErrorCode;
+
+/**
+ * @brief  A structure for simple error readout.
+ * 
+ *         flippedBitsMask is greater than 0 if the value read from the register at SBC_Register differs from expectedValue.
+ */
+typedef struct __SBC_ErrorCode {
+    uint8_t SBC_Register;       //!< The register where an error occurred.
+    uint8_t flippedBitsMask;    //!< Masks the bits that differ from the expected value. Is 0 if readout is as expected.
+    uint8_t expectedValue;      //!< Expected readout of the register.
+} SBC_ErrorCode;
+
+/**
+ * @brief   Typedef for interrupt callbacks.
+ */
+typedef void (*SBC_Func_Callback)(uint8_t callbackHandler);
+
+
+
+
+
+
+/* --------------------------------  Main Functions ------------------------------- */
+
+
+/**
+ * @brief   This method will trigger the watchdog.
+ * 
+ *          The function must be called periodically according to the configured watchdog-time.
+ */
+SBC_ErrorCode SBC_WD_Trigger(void);
+
+
+/**
+ * @brief   This method will proceed a readout of a register.
+ * 
+ * @param   SBC_Reg     Address of the register to be read out. See TLE94x1_DEFINES.h for definitions
+ * @retval  A 16 bit value will be returned.
+ *          Bit[15:8] is the Status-Information-Field, Bit [7:0] is the read register-value.
+ *          For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet.
+ */
+uint16_t SBC_Read_Command(uint8_t SBC_Reg);
+
+
+/**
+ * @brief   This method will proceed a readout of a dedicated bitfield within a register
+ * 
+ * @param   SBC_Reg         Address of the register to be readout. See TLE94x1_DEFINES.h for definitions
+ * @param   SBC_FieldMsk    Bit mask of the field to be readout. See TLE94x1_DEFINES.h for definitions
+ * @param   SBC_FieldPos    Bit position of the field to be readout. See TLE94x1_DEFINES.h for definitions
+ * 
+ * 
+ * @retval  A 8 bit value will be returned and includes the data of the bitfield to be read out *
+ */
+uint8_t SBC_Read_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos);
+
+
+
+/**
+ * @brief   Writes a whole byte to a register and verifies it.
+ * 
+ * @param   SBC_Reg         Address of the register to be manipulated. See TLE94x1_DEFINES.h for definitions
+ * @param   SBC_Val         Byte to write to SBC_Reg
+ * @param   *returnval      A 16 bit value will be returned.
+ *                          Bit[15:8] is the Status-Information-Field, Bit [7:0] is the value of the manipulated register before write
+ *                          For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet.
+ * 
+ * @retval  See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Write_Reg(uint8_t SBC_Reg, uint8_t SBC_Val, uint16_t * returnval);
+
+
+/**
+ * @brief   This method can be used for manipulating a single bit-field in a control-register.
+ *
+ *          It will readout the old value of the registers, manipulate the desired bit-field and keep
+ *          the other bit-configuration as it was.
+ *          For usage examples have a look at the implementations of different API calls below.
+ * 
+ * @param   SBC_Reg         Address of the register to be manipulated. See TLE94x1_DEFINES.h for definitions
+ * @param   SBC_FieldMsk    Bit mask of the field to manipulate. See TLE94x1_DEFINES.h for definitions
+ * @param   SBC_FieldPos    Bit position of the field to manipulate. See TLE94x1_DEFINES.h for definitions
+ * @param   SBC_FieldVal    New value which will be written to the bit-field. See TLE94x1_DEFINES.h for enumerations
+ * @param   *returnval      A 16 bit value will be returned.
+ *                          Bit[15:8] is the Status-Information-Field, Bit [7:0] is the value of the manipulated register before write
+ *                          For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet.
+ * 
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ *
+ */
+SBC_ErrorCode SBC_Write_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos, uint8_t SBC_FieldVal, uint16_t * returnval);
+
+
+/**
+ * @brief   This method must be called one time at startup of the microcontroller.
+ *
+ *          This method will initialize all registers of the SBC with the configuration-data of SBC_TLE94x1.h.
+ *          After this, the SBC can be used as normal.
+ * 
+ * @retval  SBC_ErrorCode    See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Init(void);
+
+/* --------------------------------  ISR Functions -------------------------------- */
+
+
+/**
+ * @brief   This function can register a self-defined function to a specific interrupt-event of the SBC.
+ * 
+ *          Everytime the SBC_ISR() method is called and the associated status-bit is set, it will consider to
+ *          proceed a callback to this function later.
+ *          See all the possible ISR_Vectors in the TLE94x1_ISR.h
+ *
+ * 
+ * @param   ISR_Vector   Definition of the interrupt event. See all possible events in TLE94x1_ISR.h
+ * 
+ * @param   *Callback_Handler Pointer to the function which will be called back.
+ *          The function must accept a uint8_t as first argument.
+ */
+void SBC_Register_Callback(uint32_t ISR_Vector, void (*Callback_Handler)(uint8_t callbackHandler));
+
+
+/**
+ * @brief   Interrupt Service Routine for handling interrupts.
+ * 
+ *          This method must be called automatically everytime a rising-edge on the INTN pin is recognized.
+ *          In case, the INTN pin is not connected, this method can also be called periodically by the user during runtime.
+ *          The ISR will proceed a readout of all registered interrupts. If a status-bit of a registered interrupt is set,
+ *          it will initiate a callback to the registered function and give the registered function the status-register value
+ *          as a parameter.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_ISR(void);
+
+
+
+/* --------------------------------  API Calls  ----------------------------------- */
+
+/**
+ * @brief   Enters SBC normal mode
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Mode_Normal(void);
+
+
+/**
+ * @brief   Enters SBC stop mode
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Mode_Stop(void);
+
+
+/**
+ * @brief   Clears all wake status registers and enter SBC sleep mode. Depending on configuration also the selective-wake feature will be initialized
+ *          before entering sleep mode. In case, the SWK option is enabled and the internal CAN protocol handler is not in sync when calling this function,
+ *          the sleep mode will be not entered.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Mode_Sleep(void);
+
+
+/**
+ * @brief   Sets the duty-cycle of the internal PWM generator
+ * 
+ * @param   PWM_DC Set the duty-cycle with values of 0-255 for 0% to 100%
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Set_DutyCycle_PWM(uint8_t PWM_DC);
+
+
+/**
+ * @brief   Sets the OnTime of the internal timer.
+ * 
+ * @param   OnTime	On time which will be configured to the timer. See TLE94x1_DEFINES.h for enumerations.
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Set_Timer_On(uint8_t OnTime);
+
+/**
+ * @brief   Sets the Period time of the internal timer
+ * 
+ * @param   Period  Period time which will be configured to the timer. See TLE94x1_DEFINES.h for enumerations.
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Set_Timer_Period(uint8_t Period);
+
+
+/**
+ * @brief   FO output activated by software for testing. Only working if FO/GPIO is configured as FO
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_FO_Test_On(void);
+
+
+/**
+ * @brief   FO output deactivated by software for testing. Only working if FO/GPIO is configured as FO
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_FO_Test_Off(void);
+
+
+/**
+ * @brief   Charge-Pump (VCP-Pin) is enabled. See chapter 5.3 in datasheet.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_CP_On(void);
+
+
+/**
+ * @brief   Charge-Pump (VCP-Pin) is disabled. See chapter 5.3 in datasheet.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_CP_Off(void);
+
+
+/**
+ * @brief   Enable Voltage Sensing. No wake-up events are generated. See chapter 9.2.4 in datasheet.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_WK_MEAS_On(void);
+
+
+/**
+ * @brief   Disable Voltage Sensing and enable wake-up functionality. See chapter 9.2.4 in datasheet.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_WK_MEAS_Off(void);
+
+
+/**
+ * @brief   WK is enabled as wake source. See chapter 5.2.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_TIMER_WK_EN_On(void);
+
+
+/**
+ * @brief   WK wake-up disabled. See chapter 5.2.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_TIMER_WK_EN_Off(void);
+
+
+/**
+ * @brief   Reads System Status Control, both lower and higher bits. See page 138 in datasheet.
+ * 
+ * @retval  Upper 8 bit are read from register SBC_SYS_STATUS_CTRL_1 and the lower 8 bit from SBC_SYS_STATUS_CTRL_0
+ */
+uint16_t SBC_SYS_STAT_Read(void);
+
+
+/**
+ * @brief   Writes System Status Control, both lower and higher bits. See page 138 in datasheet.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_SYS_STAT_Write(uint16_t SystemStatus);
+
+
+/**
+ * @brief   Locks CP_EN, GPIO configuration and 'rwl'-bits.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Lock_Configuration(void);
+
+
+/**
+ * @brief   Unlocks CP_EN, GPIO configuration and 'rwl'-bits.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Unlock_Configuration(void);
+
+
+/**
+ * @brief   Clears both Wake Status registers.
+ * 
+ * @retval  SBC_ErrorCode   See description of SBC_ErrorCode.
+ */
+SBC_ErrorCode SBC_Clear_Wake_Status(void);
+
+#endif  /*TLE94x1_H*/
diff --git a/cva_bootloader_m0128/src/TLE9461/TLE94x1_DEFINES.h b/cva_bootloader_m0128/src/TLE9461/TLE94x1_DEFINES.h
new file mode 100644
index 0000000..57d8ab2
--- /dev/null
+++ b/cva_bootloader_m0128/src/TLE9461/TLE94x1_DEFINES.h
@@ -0,0 +1,3248 @@
+/*********************************************************************************************************************
+ * Copyright (c) 2019, Infineon Technologies AG
+ *
+ * 
+ * Distributed under the Boost Software License, Version 1.0.
+ * 
+ * 
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ * 
+ * Permission is hereby granted, free of charge, to any person or organization
+ * obtaining a copy of the software and accompanying documentation covered by
+ * this license (the "Software") to use, reproduce, display, distribute,
+ * execute, and transmit the Software, and to prepare derivative works of the
+ * Software, and to permit third-parties to whom the Software is furnished to
+ * do so, all subject to the following:
+ * 
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer,
+ * must be included in all copies of the Software, in whole or in part, and
+ * all derivative works of the Software, unless such copies or derivative
+ * works are solely in the form of machine-executable object code generated by
+ * a source language processor.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ *********************************************************************************************************************/
+
+
+/****************************************************************************************************//**
+ * @file        TLE94x1_DEFINES.h
+ *
+ * @brief       Main header declaration file for TLE94x1 SBC family device
+ *
+ * @version     V1.0.0
+ * @date        15. April 2019
+ * @author      Markus Noll / markus.noll@infineon.com
+ * @author      Yannek Micha Rixen / Yannek.Rixen@infineon.com
+ *******************************************************************************************************/
+
+
+
+#ifndef TLE94x1_DEFINES_H
+#define TLE94x1_DEFINES_H
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================           General Control Registers            ================ */
+/* ================================================================================ */
+
+
+
+/**
+ * @def     SBC_M_S_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_M_S_CTRL                            (0b00000001U)
+
+/**
+ * @def     SBC_HW_CTRL_0
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_HW_CTRL_0                           (0b00000010U)
+
+/**
+ * @def     SBC_WD_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_WD_CTRL                             (0b00000011U)
+
+/**
+ * @def     SBC_BUS_CTRL_0
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_BUS_CTRL_0                          (0b00000100U)
+
+/**
+ * @def     SBC_WK_CTRL_0
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_WK_CTRL_0                           (0b00000110U)
+
+/**
+ * @def     SBC_WK_CTRL_1
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_WK_CTRL_1                           (0b00000111U)
+
+/**
+ * @def     SBC_WK_PUPD_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_WK_PUPD_CTRL                        (0b00001000U)
+
+/**
+ * @def     SBC_BUS_CTRL_3
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_BUS_CTRL_3                          (0b00001011U)
+
+/**
+ * @def     SBC_TIMER_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_TIMER_CTRL                          (0b00001100U)
+
+/**
+ * @def     SBC_HW_CTRL_1
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_HW_CTRL_1                           (0b00001110U)
+
+/**
+ * @def     SBC_HW_CTRL_2
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_HW_CTRL_2                           (0b00001111U)
+
+/**
+ * @def     SBC_GPIO_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_GPIO_CTRL                           (0b00010111U)
+
+/**
+ * @def     SBC_PWM_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_PWM_CTRL                            (0b00011000U)
+
+/**
+ * @def     SBC_PWM_FREQ_CTRL
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_PWM_FREQ_CTRL                       (0b00011100U)
+
+/**
+ * @def     SBC_HW_CTRL_3
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_HW_CTRL_3                           (0b00011101U)
+
+/**
+ * @def     SBC_SYS_STATUS_CTRL_0
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_SYS_STATUS_CTRL_0                   (0b00011110U)
+
+/**
+ * @def     SBC_SYS_STATUS_CTRL_1
+ * 
+ * @brief   Control register address.
+ */
+#define SBC_SYS_STATUS_CTRL_1                   (0b00011111U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================        Selective Wake Control Registers        ================ */
+/* ================================================================================ */
+
+
+
+/**
+ * @def     SBC_SWK_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_CTRL                            (0b00100000U)
+
+/**
+ * @def     SBC_SWK_BTL0_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_BTL0_CTRL                       (0b00100001U)
+
+/**
+ * @def     SBC_SWK_BTL1_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_BTL1_CTRL                       (0b00100010U)
+
+/**
+ * @def     SBC_SWK_ID3_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_ID3_CTRL                        (0b00100011U)
+
+/**
+ * @def     SBC_SWK_ID2_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_ID2_CTRL                        (0b00100100U)
+
+/**
+ * @def     SBC_SWK_ID1_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_ID1_CTRL                        (0b00100101U)
+
+/**
+ * @def     SBC_SWK_ID0_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_ID0_CTRL                        (0b00100110U)
+
+/**
+ * @def     SBC_SWK_MASK_ID3_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_MASK_ID3_CTRL                   (0b00100111U)
+
+/**
+ * @def     SBC_SWK_MASK_ID2_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_MASK_ID2_CTRL                   (0b00101000U)
+
+/**
+ * @def     SBC_SWK_MASK_ID1_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_MASK_ID1_CTRL                   (0b00101001U)
+
+/**
+ * @def     SBC_SWK_MASK_ID0_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_MASK_ID0_CTRL                   (0b00101010U)
+
+/**
+ * @def     SBC_SWK_DLC_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DLC_CTRL                        (0b00101011U)
+
+/**
+ * @def     SBC_SWK_DATA7_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA7_CTRL                      (0b00101100U)
+
+/**
+ * @def     SBC_SWK_DATA6_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA6_CTRL                      (0b00101101U)
+
+/**
+ * @def     SBC_SWK_DATA5_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA5_CTRL                      (0b00101110U)
+
+/**
+ * @def     SBC_SWK_DATA4_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA4_CTRL                      (0b00101111U)
+
+/**
+ * @def     SBC_SWK_DATA3_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA3_CTRL                      (0b00110000U)
+
+/**
+ * @def     SBC_SWK_DATA2_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA2_CTRL                      (0b00110001U)
+
+/**
+ * @def     SBC_SWK_DATA1_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA1_CTRL                      (0b00110010U)
+
+/**
+ * @def     SBC_SWK_DATA0_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_DATA0_CTRL                      (0b00110011U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_CAN_FD_CTRL                     (0b00110100U)
+
+/**
+ * @def     SBC_SWK_OSC_TRIM_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_OSC_TRIM_CTRL                   (0b00111000U)
+
+/**
+ * @def     SBC_SWK_OPT_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_OPT_CTRL                        (0b00111001U)
+
+/**
+ * @def     SBC_SWK_OSC_CAL_H_STAT
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_OSC_CAL_H_STAT                  (0b00111010U)
+
+/**
+ * @def     SBC_SWK_OSC_CAL_L_STAT
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_OSC_CAL_L_STAT                  (0b00111011U)
+
+/**
+ * @def     SBC_SWK_CDR_CTRL1
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_CDR_CTRL1                       (0b00111100U)
+
+/**
+ * @def     SBC_SWK_CDR_CTRL2
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_CDR_CTRL2                       (0b00111101U)
+
+/**
+ * @def     SBC_SWK_CDR_LIMIT_HIGH_CTRL
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_CDR_LIMIT_HIGH_CTRL             (0b00111110U)
+
+/**
+ * @def     SBC_SWK_CDR_LIMIT_LOW_CTRL 
+ * 
+ * @brief   Selective wake register address.
+ */
+#define SBC_SWK_CDR_LIMIT_LOW_CTRL              (0b00111111U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================            General Status Registers            ================ */
+/* ================================================================================ */
+
+
+
+
+/**
+ * @def     SBC_SUP_STAT_1
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_SUP_STAT_1                          (0b01000000U)
+
+/**
+ * @def     SBC_SUP_STAT_0
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_SUP_STAT_0                          (0b01000001U)
+
+/**
+ * @def     SBC_THERM_STAT
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_THERM_STAT                          (0b01000010U)
+
+/**
+ * @def     SBC_DEV_STAT
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_DEV_STAT                            (0b01000011U)
+
+/**
+ * @def     SBC_BUS_STAT
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_BUS_STAT                            (0b01000100U)
+
+/**
+ * @def     SBC_WK_STAT_0
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_WK_STAT_0                           (0b01000110U)
+
+/**
+ * @def     SBC_WK_STAT_1
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_WK_STAT_1                           (0b01000111U)
+
+/**
+ * @def     SBC_WK_LVL_STAT 
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_WK_LVL_STAT                         (0b01001000U)
+
+/**
+ * @def     SBC_GPIO_OC_STAT
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_GPIO_OC_STAT                        (0b01010100U)
+
+/**
+ * @def     SBC_GPIO_OL_STAT
+ * 
+ * @brief   Status register address.
+ */
+#define SBC_GPIO_OL_STAT                        (0b01010101U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================        Selective Wake Status Registers         ================ */
+/* ================================================================================ */
+
+
+
+
+/**
+ * @def     SBC_SWK_STAT
+ * 
+ * @brief   Selective wake status register address.
+ */
+#define SBC_SWK_STAT                            (0b01110000U)
+
+/**
+ * @def     SBC_SWK_ECNT_STAT
+ * 
+ * @brief   Selective wake status register address.
+ */
+#define SBC_SWK_ECNT_STAT                       (0b01110001U)
+
+/**
+ * @def     SBC_SWK_CDR_STAT1
+ * 
+ * @brief   Selective wake status register address.
+ */
+#define SBC_SWK_CDR_STAT1                       (0b01110010U)
+
+/**
+ * @def     SBC_SWK_CDR_STAT2
+ * 
+ * @brief   Selective wake status register address.
+ */
+#define SBC_SWK_CDR_STAT2                       (0b01110011U)
+
+/**
+ * @def     SBC_FAM_PROD_STAT
+ * 
+ * @brief   Selective wake status register address.
+ */
+#define SBC_FAM_PROD_STAT                       (0b01111110U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ============   General Control Registers Position & Mask        ================ */
+/* ================================================================================ */
+
+
+
+/* --------------------------------  M_S_CTRL  ------------------------------------ */
+
+/**
+ * @def     SBC_M_S_CTRL_MODE_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_M_S_CTRL_MODE_Pos                   (6U)
+/**
+ * @def     SBC_M_S_CTRL_MODE_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_M_S_CTRL_MODE_Msk                   (0b11000000U)
+/**
+ * @def     SBC_M_S_CTRL_VCC2_ON_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_M_S_CTRL_VCC2_ON_Pos                (3U)
+/**
+ * @def     SBC_M_S_CTRL_VCC2_ON_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_M_S_CTRL_VCC2_ON_Msk                (0b00011000U)
+/**
+ * @def     SBC_M_S_CTRL_VCC1_OV_RST_Pos 
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_M_S_CTRL_VCC1_OV_RST_Pos            (2U)
+/**
+ * @def     SBC_M_S_CTRL_VCC1_OV_RST_Msk 
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_M_S_CTRL_VCC1_OV_RST_Msk            (0b00000100U)
+/**
+ * @def     SBC_M_S_CTRL_VCC1_RT_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_M_S_CTRL_VCC1_RT_Pos                (0U)
+/**
+ * @def     SBC_M_S_CTRL_VCC1_RT_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_M_S_CTRL_VCC1_RT_Msk                (0b00000011U)
+
+
+/* --------------------------------  HW_CTRL_0  ----------------------------------- */
+
+
+/**
+ * @def     SBC_HW_CTRL_0_SOFT_RESET_RST_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_0_SOFT_RESET_RST_Pos        (6U)
+
+/**
+ * @def     SBC_HW_CTRL_0_SOFT_RESET_RST_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_0_SOFT_RESET_RST_Msk        (0b01000000U)
+
+/**
+ * @def     SBC_HW_CTRL_0_FO_ON_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_0_FO_ON_Pos                 (5U)
+
+/**
+ * @def     SBC_HW_CTRL_0_FO_ON_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_0_FO_ON_Msk                 (0b00100000U)
+
+/**
+ * @def     SBC_HW_CTRL_0_CP_EN_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_0_CP_EN_Pos                 (2U)
+
+/**
+ * @def     SBC_HW_CTRL_0_CP_EN_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_0_CP_EN_Msk                 (0b00000100U)
+
+/**
+ * @def     SBC_HW_CTRL_0_CFG1_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_0_CFG1_Pos                  (0U)
+
+/**
+ * @def     SBC_HW_CTRL_0_CFG1_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_0_CFG1_Msk                  (0b00000001U)
+
+
+/* --------------------------------  WD_CTRL    ----------------------------------- */
+
+
+/**
+ * @def     SBC_WD_CTRL_CHECKSUM_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WD_CTRL_CHECKSUM_Pos                (7U)
+
+/**
+ * @def     SBC_WD_CTRL_CHECKSUM_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WD_CTRL_CHECKSUM_Msk                (0b10000000U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_STM_EN_0_Pos 
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WD_CTRL_WD_STM_EN_0_Pos             (6U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_STM_EN_0_Msk 
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WD_CTRL_WD_STM_EN_0_Msk             (0b01000000U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_WIN_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WD_CTRL_WD_WIN_Pos                  (5U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_WIN_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WD_CTRL_WD_WIN_Msk                  (0b00100000U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_EN_WK_BUS_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WD_CTRL_WD_EN_WK_BUS_Pos            (4U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_EN_WK_BUS_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WD_CTRL_WD_EN_WK_BUS_Msk            (0b00010000U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_TIMER_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WD_CTRL_WD_TIMER_Pos                (0U)
+
+/**
+ * @def     SBC_WD_CTRL_WD_TIMER_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WD_CTRL_WD_TIMER_Msk                (0b00000111U)
+
+
+/* --------------------------------  BUS_CTRL_0  ---------------------------------- */
+
+/**
+ * @def     SBC_BUS_CTRL_0_CAN_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_BUS_CTRL_0_CAN_Pos                  (0U)
+
+/**
+ * @def     SBC_BUS_CTRL_0_CAN_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_BUS_CTRL_0_CAN_Msk                  (0b00000111U)
+
+
+/* --------------------------------  WK_CTRL_0  ----------------------------------- */
+
+/**
+ * @def     SBC_WK_CTRL_0_TIMER_WK_EN_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_CTRL_0_TIMER_WK_EN_Pos           (6U)
+
+/**
+ * @def     SBC_WK_CTRL_0_TIMER_WK_EN_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_CTRL_0_TIMER_WK_EN_Msk           (0b01000000U)
+
+/**
+ * @def     SBC_WK_CTRL_0_WD_STM_EN_1_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_CTRL_0_WD_STM_EN_1_Pos           (2U)
+
+/**
+ * @def     SBC_WK_CTRL_0_WD_STM_EN_1_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_CTRL_0_WD_STM_EN_1_Msk           (0b00000100U)
+
+
+/* --------------------------------  WK_CTRL_1  ----------------------------------- */
+
+
+/**
+ * @def     SBC_WK_CTRL_1_INT_GLOBAL_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_CTRL_1_INT_GLOBAL_Pos            (7U)
+
+/**
+ * @def     SBC_WK_CTRL_1_INT_GLOBAL_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_CTRL_1_INT_GLOBAL_Msk            (0b10000000U)
+
+/**
+ * @def     SBC_WK_CTRL_1_WK_MEAS_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_CTRL_1_WK_MEAS_Pos               (5U)
+
+/**
+ * @def     SBC_WK_CTRL_1_WK_MEAS_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_CTRL_1_WK_MEAS_Msk               (0b00100000U)
+
+/**
+ * @def     SBC_WK_CTRL_1_WK_EN_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_CTRL_1_WK_EN_Pos                 (0U)
+
+/**
+ * @def     SBC_WK_CTRL_1_WK_EN_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_CTRL_1_WK_EN_Msk                 (0b00000001U)
+
+
+/* --------------------------------  WK_PUPD_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Pos       (6U)
+
+/**
+ * @def     SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Msk       (0b11000000U)
+
+/**
+ * @def     SBC_WK_PUPD_CTRL_WK_PUPD_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_WK_PUPD_CTRL_WK_PUPD_Pos            (0U)
+
+/**
+ * @def     SBC_WK_PUPD_CTRL_WK_PUPD_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_WK_PUPD_CTRL_WK_PUPD_Msk            (0b00000011U)
+
+
+/* -------------------------------   BUS_CTRL_3  ---------------------------------- */
+
+/**
+ * @def     SBC_BUS_CTRL_3_CAN_FLASH_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_BUS_CTRL_3_CAN_FLASH_Pos            (4U)
+
+/**
+ * @def     SBC_BUS_CTRL_3_CAN_FLASH_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_BUS_CTRL_3_CAN_FLASH_Msk            (0b00010000U)
+
+
+/* -------------------------------   TIMER_CTRL  ---------------------------------- */
+
+
+/**
+ * @def     SBC_TIMER_CTRL_TIMER_ON_Pos 
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_TIMER_CTRL_TIMER_ON_Pos             (4U)
+
+/**
+ * @def     SBC_TIMER_CTRL_TIMER_ON_Msk 
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_TIMER_CTRL_TIMER_ON_Msk             (0b01110000U)
+
+/**
+ * @def     SBC_TIMER_CTRL_TIMER_PER_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_TIMER_CTRL_TIMER_PER_Pos            (0U)
+
+/**
+ * @def     SBC_TIMER_CTRL_TIMER_PER_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_TIMER_CTRL_TIMER_PER_Msk            (0b00001111U)
+
+
+/* --------------------------------  HW_CTRL_1  ----------------------------------- */
+
+
+/**
+ * @def     SBC_HW_CTRL_1_RSTN_HYS_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_1_RSTN_HYS_Pos              (7U)
+
+/**
+ * @def     SBC_HW_CTRL_1_RSTN_HYS_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_1_RSTN_HYS_Msk              (0b10000000U)
+
+/**
+ * @def     SBC_HW_CTRL_1_TSD2_DEL_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_1_TSD2_DEL_Pos              (5U)
+
+/**
+ * @def     SBC_HW_CTRL_1_TSD2_DEL_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_1_TSD2_DEL_Msk              (0b00100000U)
+
+/**
+ * @def     SBC_HW_CTRL_1_RSTN_DEL_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_1_RSTN_DEL_Pos              (4U)
+
+/**
+ * @def     SBC_HW_CTRL_1_RSTN_DEL_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_1_RSTN_DEL_Msk              (0b00010000U)
+
+/**
+ * @def     SBC_HW_CTRL_1_CFG_LOCK_0_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_1_CFG_LOCK_0_Pos            (3U)
+
+/**
+ * @def     SBC_HW_CTRL_1_CFG_LOCK_0_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_1_CFG_LOCK_0_Msk            (0b00001000U)
+
+
+/* --------------------------------  HW_CTRL_2  ----------------------------------- */
+
+
+/**
+ * @def     SBC_HW_CTRL_2_2MHZ_FREQ_Pos 
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_2_2MHZ_FREQ_Pos             (5U)
+
+/**
+ * @def     SBC_HW_CTRL_2_2MHZ_FREQ_Msk 
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_2_2MHZ_FREQ_Msk             (0b11100000U)
+
+/**
+ * @def     SBC_HW_CTRL_2_I_PEAK_TH_Pos 
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_2_I_PEAK_TH_Pos             (4U)
+
+/**
+ * @def     SBC_HW_CTRL_2_I_PEAK_TH_Msk 
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_2_I_PEAK_TH_Msk             (0b00010000U)
+
+/**
+ * @def     SBC_HW_CTRL_2_SS_MOD_FR_Pos 
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_2_SS_MOD_FR_Pos             (2U)
+
+/**
+ * @def     SBC_HW_CTRL_2_SS_MOD_FR_Msk 
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_2_SS_MOD_FR_Msk             (0b00001100U)
+
+/**
+ * @def     SBC_HW_CTRL_2_CFG_LOCK_1_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_2_CFG_LOCK_1_Pos            (0U)
+
+/**
+ * @def     SBC_HW_CTRL_2_CFG_LOCK_1_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_2_CFG_LOCK_1_Msk            (0b00000001U)
+
+
+/* --------------------------------  GPIO_CTRL  ----------------------------------- */
+
+/**
+ * @def     SBC_GPIO_CTRL_GPIO_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_GPIO_CTRL_GPIO_Pos                  (0U)
+
+/**
+ * @def     SBC_GPIO_CTRL_GPIO_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_GPIO_CTRL_GPIO_Msk                  (0b00000111U)
+
+
+/* --------------------------------  PWM_CTRL  -------------------------------------- */
+
+/**
+ * @def     SBC_PWM_DC_PWM_DC_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_PWM_CTRL_PWM_DC_Pos                   (0U)
+
+/**
+ * @def     SBC_PWM_DC_PWM_DC_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_PWM_CTRL_PWM_DC_Msk                   (0b11111111U)
+
+
+/* --------------------------------  PWM_FREQ_CTRL  -------------------------------------- */
+
+/**
+ * @def     SBC_PWM_FREQ_CTRL_PWM_FREQ_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_PWM_FREQ_CTRL_PWM_FREQ_Pos            (0U)
+
+
+/**
+ * @def     SBC_PWM_FREQ_CTRL_PWM_FREQ_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_PWM_FREQ_CTRL_PWM_FREQ_Msk            (0b00000011U)
+
+
+/* --------------------------------  HW_CTRL_3  ----------------------------------- */
+
+
+/**
+ * @def     SBC_HW_CTRL_3_TSD_THR_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_3_TSD_THR_Pos               (2U)
+
+/**
+ * @def     SBC_HW_CTRL_3_TSD_THR_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_3_TSD_THR_Msk               (0b00000100U)
+
+/**
+ * @def     SBC_HW_CTRL_3_ICC1_LIM_ADJ_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_HW_CTRL_3_ICC1_LIM_ADJ_Pos          (0U)
+
+/**
+ * @def     SBC_HW_CTRL_3_ICC1_LIM_ADJ_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_HW_CTRL_3_ICC1_LIM_ADJ_Msk          (0b00000011U)
+
+
+/* --------------------------------  SYS_STATUS_CTRL_0  --------------------------- */
+
+/**
+ * @def     SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Pos    (0U)
+
+/**
+ * @def     SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Msk    (0b11111111U)
+
+
+/* --------------------------------  SYS_STATUS_CTRL_1  --------------------------- */
+
+
+/**
+ * @def     SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Pos
+ * 
+ * @brief   Control register bit position.
+ */
+#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Pos    (0U)
+
+/**
+ * @def     SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Msk
+ * 
+ * @brief   Control register bit mask.
+ */
+#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Msk    (0b11111111U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ========   Selective Wake Control Registers Position & Mask        ============= */
+/* ================================================================================ */
+
+
+
+/* --------------------------------  SWK_CTRL  ------------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_CTRL_OSC_CAL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CTRL_OSC_CAL_Pos                (7U)
+
+/**
+ * @def     SBC_SWK_CTRL_OSC_CAL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CTRL_OSC_CAL_Msk                (0b10000000U)
+
+/**
+ * @def     SBC_SWK_CTRL_TRIM_EN_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CTRL_TRIM_EN_Pos                (5U)
+
+/**
+ * @def     SBC_SWK_CTRL_TRIM_EN_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CTRL_TRIM_EN_Msk                (0b01100000U)
+
+/**
+ * @def     SBC_SWK_CTRL_CANTO_MASK_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CTRL_CANTO_MASK_Pos             (4U)
+
+/**
+ * @def     SBC_SWK_CTRL_CANTO_MASK_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CTRL_CANTO_MASK_Msk             (0b00010000U)
+
+/**
+ * @def     SBC_SWK_CTRL_CFG_VAL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CTRL_CFG_VAL_Pos                (0U)
+
+/**
+ * @def     SBC_SWK_CTRL_CFG_VAL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CTRL_CFG_VAL_Msk                (0b00000001U)
+
+
+/* --------------------------------  SWK_BTL0_CTRL  ------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_BTL0_CTRL_TBIT_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_BTL0_CTRL_TBIT_Pos              (0U)
+
+/**
+ * @def     SBC_SWK_BTL0_CTRL_TBIT_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_BTL0_CTRL_TBIT_Msk              (0b11111111U)
+
+
+/* --------------------------------  SWK_BTL1_CTRL  ------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_BTL1_CTRL_SP_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_BTL1_CTRL_SP_Pos                (0U)
+
+/**
+ * @def     SBC_SWK_BTL1_CTRL_SP_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_BTL1_CTRL_SP_Msk                (0b00111111U)
+
+
+/* --------------------------------  SWK_ID3_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_ID3_CTRL_ID28_21_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_ID3_CTRL_ID28_21_Pos            (0U)
+
+/**
+ * @def     SBC_SWK_ID3_CTRL_ID28_21_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_ID3_CTRL_ID28_21_Msk            (0b11111111U)
+
+
+/* --------------------------------  SWK_ID2_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_ID2_CTRL_ID20_13_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_ID2_CTRL_ID20_13_Pos            (0U)
+
+/**
+ * @def     SBC_SWK_ID2_CTRL_ID20_13_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_ID2_CTRL_ID20_13_Msk            (0b11111111U)
+
+
+/* --------------------------------  SWK_ID1_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_ID1_CTRL_ID12_5_Pos
+ * 
+ * @brief   Selective wake register bit position. 
+ */
+#define SBC_SWK_ID1_CTRL_ID12_5_Pos             (0U)
+
+/**
+ * @def     SBC_SWK_ID1_CTRL_ID12_5_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_ID1_CTRL_ID12_5_Msk             (0b11111111U)
+
+
+/* --------------------------------  SWK_ID0_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_ID0_CTRL_ID4_0_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_ID0_CTRL_ID4_0_Pos              (2U)
+
+/**
+ * @def     SBC_SWK_ID0_CTRL_ID4_0_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_ID0_CTRL_ID4_0_Msk              (0b01111100U)
+
+/**
+ * @def     SBC_SWK_ID0_CTRL_RTR_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_ID0_CTRL_RTR_Pos                (1U)
+
+/**
+ * @def     SBC_SWK_ID0_CTRL_RTR_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_ID0_CTRL_RTR_Msk                (0b00000010U)
+
+/**
+ * @def     SBC_SWK_ID0_CTRL_IDE_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_ID0_CTRL_IDE_Pos                (0U)
+
+/**
+ * @def     SBC_SWK_ID0_CTRL_IDE_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_ID0_CTRL_IDE_Msk                (0b00000001U)
+
+
+/* --------------------------------  SWK_MASK_ID3_CTRL  --------------------------- */
+
+
+/**
+ * @def     SBC_SWK_MASK_ID3_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_MASK_ID3_CTRL_Pos               (0U)
+
+/**
+ * @def     SBC_SWK_MASK_ID3_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_MASK_ID3_CTRL_Msk               (0b11111111U)
+
+
+/* --------------------------------  SWK_MASK_ID2_CTRL  --------------------------- */
+
+
+/**
+ * @def     SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Pos  (0U)
+
+/**
+ * @def     SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Msk  (0b11111111U)
+
+
+/* --------------------------------  SWK_MASK_ID1_CTRL  --------------------------- */
+
+
+/**
+ * @def     SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Pos   (0U)
+
+/**
+ * @def     SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Msk   (0b11111111U)
+
+
+/* --------------------------------  SWK_MASK_ID0_CTRL  --------------------------- */
+
+
+/**
+ * @def     SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Pos
+ * 
+ * @brief   Selective wake register bit position. 
+ */
+#define SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Pos    (2U)
+
+/**
+ * @def     SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk    (0b01111100U)
+
+
+/* --------------------------------  SWK_DLC_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_DLC_CTRL_DLC_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DLC_CTRL_DLC_Pos                (0U)
+
+/**
+ * @def     SBC_SWK_DLC_CTRL_DLC_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DLC_CTRL_DLC_Msk                (0b00001111U)
+
+
+/* --------------------------------  SWK_DATA7_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA7_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA7_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA7_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA7_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA6_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA6_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA6_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA6_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA6_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA5_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA5_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA5_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA5_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA5_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA4_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA4_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA4_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA4_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA4_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA3_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA3_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA3_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA3_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA3_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA2_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA2_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA2_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA2_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA2_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA1_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA1_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA1_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA1_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA1_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_DATA0_CTRL  ------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_DATA0_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_DATA0_CTRL_Pos                  (0U)
+
+/**
+ * @def     SBC_SWK_DATA0_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_DATA0_CTRL_Msk                  (0b11111111U)
+
+
+/* --------------------------------  SWK_CAN_FD_CTRL  ----------------------------- */
+
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos     (5U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Msk     (0b00100000U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Pos     (4U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Msk     (0b00010000U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_FD_FILTER_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CAN_FD_CTRL_FD_FILTER_Pos       (1U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_FD_FILTER_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CAN_FD_CTRL_FD_FILTER_Msk       (0b00001110U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Pos       (0U)
+
+/**
+ * @def     SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk       (0b00000001U)
+
+
+/* --------------------------------  SWK_OSC_TRIM_CTRL  --------------------------- */
+
+
+/**
+ * @def     SBC_SWK_OSC_TRIM_CTRL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_OSC_TRIM_CTRL_Pos               (0U)
+
+/**
+ * @def     SBC_SWK_OSC_TRIM_CTRL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_OSC_TRIM_CTRL_Msk               (0b01111111U)
+
+
+/* --------------------------------  SWK_OPT_CTRL  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_OPT_CTRL_RX_WK_SEL_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_OPT_CTRL_RX_WK_SEL_Pos          (7U)
+
+/**
+ * @def     SBC_SWK_OPT_CTRL_RX_WK_SEL_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_OPT_CTRL_RX_WK_SEL_Msk          (0b10000000U)
+
+
+/* --------------------------------  SWK_OSC_CAL_H_STAT  -------------------------- */
+
+
+/**
+ * @def     SBC_SWK_OSC_CAL_H_STAT_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_OSC_CAL_H_STAT_Pos              (0U)
+
+/**
+ * @def     SBC_SWK_OSC_CAL_H_STAT_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_OSC_CAL_H_STAT_Msk              (0b11111111U)
+
+
+/* --------------------------------  SWK_OPT_CAL_L_STAT  -------------------------- */
+
+
+/**
+ * @def     SBC_SWK_OPT_CAL_L_STAT_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_OPT_CAL_L_STAT_Pos              (0U)
+
+/**
+ * @def     SBC_SWK_OPT_CAL_L_STAT_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_OPT_CAL_L_STAT_Msk              (0b11111111U)
+
+
+/* --------------------------------  SWK_CDR_CTRL1  ------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_CDR_CTRL1_SEL_FILT_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CDR_CTRL1_SEL_FILT_Pos          (2U)
+
+/**
+ * @def     SBC_SWK_CDR_CTRL1_SEL_FILT_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CDR_CTRL1_SEL_FILT_Msk          (0b00001100U)
+
+/**
+ * @def     SBC_SWK_CDR_CTRL1_CDR_EN_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CDR_CTRL1_CDR_EN_Pos            (0U)
+
+/**
+ * @def     SBC_SWK_CDR_CTRL1_CDR_EN_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CDR_CTRL1_CDR_EN_Msk            (0b00000001U)
+
+
+/* --------------------------------  SWK_CDR_CTRL2  ------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Pos       (0U)
+
+/**
+ * @def     SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Msk       (0b00000011U)
+
+
+/* --------------------------------  SWK_CDR_LIMIT_HIGH_CTRL  --------------------- */
+
+
+/**
+ * @def     SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Pos   (0U)
+
+/**
+ * @def     SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Msk   (0b11111111U)
+
+
+/* --------------------------------  SWK_CDR_LIMIT_LOW_CTRL  ---------------------- */
+
+
+/**
+ * @def     SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Pos
+ * 
+ * @brief   Selective wake register bit position.
+ */
+#define SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Pos    (0U)
+
+/**
+ * @def     SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Msk
+ * 
+ * @brief   Selective wake register bit mask.
+ */
+#define SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Msk    (0b11111111U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* =============   General Status Registers Position & Mask        ================ */
+/* ================================================================================ */
+
+
+
+/* --------------------------------  SUP_STAT_1  ---------------------------------- */
+
+
+/**
+ * @def     SBC_SUP_STAT_1_VS_UV_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_1_VS_UV_Pos                (6U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VS_UV_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_1_VS_UV_Msk                (0b01000000U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VS_OV_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_1_VS_OV_Pos                (5U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VS_OV_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_1_VS_OV_Msk                (0b00100000U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VCC1_OV_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_1_VCC1_OV_Pos              (1U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VCC1_OV_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_1_VCC1_OV_Msk              (0b00000010U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VCC1_WARN_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_1_VCC1_WARN_Pos            (0U)
+
+/**
+ * @def     SBC_SUP_STAT_1_VCC1_WARN_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_1_VCC1_WARN_Msk            (0b00000001U)
+
+
+/* --------------------------------  SUP_STAT_0  ---------------------------------- */
+
+
+/**
+ * @def     SBC_SUP_STAT_0_POR_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_0_POR_Pos                  (7U)
+
+/**
+ * @def     SBC_SUP_STAT_0_POR_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_0_POR_Msk                  (0b10000000U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC2_OT_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_0_VCC2_OT_Pos              (4U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC2_OT_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_0_VCC2_OT_Msk              (0b00010000U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC2_UV_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_0_VCC2_UV_Pos              (3U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC2_UV_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_0_VCC2_UV_Msk              (0b00001000U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC1_SC_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_0_VCC1_SC_Pos              (2U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC1_SC_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_0_VCC1_SC_Msk              (0b00000100U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC1_UV_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_SUP_STAT_0_VCC1_UV_Pos              (0U)
+
+/**
+ * @def     SBC_SUP_STAT_0_VCC1_UV_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_SUP_STAT_0_VCC1_UV_Msk              (0b00000001U)
+
+
+/* --------------------------------  THERM_STAT  ---------------------------------- */
+
+
+/**
+ * @def     SBC_THERM_STAT_TSD2_SAFE_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_THERM_STAT_TSD2_SAFE_Pos            (3U)
+
+/**
+ * @def     SBC_THERM_STAT_TSD2_SAFE_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_THERM_STAT_TSD2_SAFE_Msk            (0b00001000U)
+
+/**
+ * @def     SBC_THERM_STAT_TSD2_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_THERM_STAT_TSD2_Pos                 (2U)
+
+/**
+ * @def     SBC_THERM_STAT_TSD2_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_THERM_STAT_TSD2_Msk                 (0b00000100U)
+
+/**
+ * @def     SBC_THERM_STAT_TSD1_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_THERM_STAT_TSD1_Pos                 (1U)
+
+/**
+ * @def     SBC_THERM_STAT_TSD1_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_THERM_STAT_TSD1_Msk                 (0b00000010U)
+
+/**
+ * @def     SBC_THERM_STAT_TPW_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_THERM_STAT_TPW_Pos                  (0U)
+
+/**
+ * @def     SBC_THERM_STAT_TPW_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_THERM_STAT_TPW_Msk                  (0b00000001U)
+
+
+/* --------------------------------  DEV_STAT  ------------------------------------ */
+
+
+/**
+ * @def     SBC_DEV_STAT_DEV_STAT_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_DEV_STAT_DEV_STAT_Pos               (6U)
+
+/**
+ * @def     SBC_DEV_STAT_DEV_STAT_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_DEV_STAT_DEV_STAT_Msk               (0b11000000U)
+
+/**
+ * @def     SBC_DEV_STAT_WD_FAIL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_DEV_STAT_WD_FAIL_Pos                (2U)
+
+/**
+ * @def     SBC_DEV_STAT_WD_FAIL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_DEV_STAT_WD_FAIL_Msk                (0b00001100U)
+
+/**
+ * @def     SBC_DEV_STAT_SPI_FAIL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_DEV_STAT_SPI_FAIL_Pos               (1U)
+
+/**
+ * @def     SBC_DEV_STAT_SPI_FAIL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_DEV_STAT_SPI_FAIL_Msk               (0b00000010U)
+
+/**
+ * @def     SBC_DEV_STAT_FAILURE_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_DEV_STAT_FAILURE_Pos                (0U)
+
+/**
+ * @def     SBC_DEV_STAT_FAILURE_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_DEV_STAT_FAILURE_Msk                (0b00000001U)
+
+
+/* --------------------------------  BUS_STAT  ------------------------------------ */
+
+
+/**
+ * @def     SBC_BUS_STAT_CANTO_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_BUS_STAT_CANTO_Pos                  (4U)
+
+/**
+ * @def     SBC_BUS_STAT_CANTO_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_BUS_STAT_CANTO_Msk                  (0b00010000U)
+
+/**
+ * @def     SBC_BUS_STAT_SYSERR_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_BUS_STAT_SYSERR_Pos                 (3U)
+
+/**
+ * @def     SBC_BUS_STAT_SYSERR_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_BUS_STAT_SYSERR_Msk                 (0b00001000U)
+
+/**
+ * @def     SBC_BUS_STAT_CAN_FAIL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_BUS_STAT_CAN_FAIL_Pos               (1U)
+
+/**
+ * @def     SBC_BUS_STAT_CAN_FAIL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_BUS_STAT_CAN_FAIL_Msk               (0b00000110U)
+
+/**
+ * @def     SBC_BUS_STAT_VCAN_UV_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_BUS_STAT_VCAN_UV_Pos                (0U)
+
+/**
+ * @def     SBC_BUS_STAT_VCAN_UV_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_BUS_STAT_VCAN_UV_Msk                (0b00000001U)
+
+
+/* --------------------------------  WK_STAT_0  ----------------------------------- */
+
+
+/**
+ * @def     SBC_WK_STAT_0_CAN_WU_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_STAT_0_CAN_WU_Pos                (5U)
+
+/**
+ * @def     SBC_WK_STAT_0_CAN_WU_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_STAT_0_CAN_WU_Msk                (0b00100000U)
+
+/**
+ * @def     SBC_WK_STAT_0_TIMER_WU_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_STAT_0_TIMER_WU_Pos              (4U)
+
+/**
+ * @def     SBC_WK_STAT_0_TIMER_WU_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_STAT_0_TIMER_WU_Msk              (0b00010000U)
+
+/**
+ * @def     SBC_WK_STAT_0_WK_WU_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_STAT_0_WK_WU_Pos                 (0U)
+
+/**
+ * @def     SBC_WK_STAT_0_WK_WU_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_STAT_0_WK_WU_Msk                 (0b00000001U)
+
+
+/* --------------------------------  WK_STAT_1  ----------------------------------- */
+
+
+/**
+ * @def     SBC_WK_STAT_1_GPIO_WK_WU_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_STAT_1_GPIO_WK_WU_Pos            (4U)
+
+/**
+ * @def     SBC_WK_STAT_1_GPIO_WK_WU_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_STAT_1_GPIO_WK_WU_Msk            (0b00010000U)
+
+
+/* --------------------------------  WK_LVL_STAT  --------------------------------- */
+
+
+/**
+ * @def     SBC_WK_LVL_STAT_SBC_DEV_LVL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_LVL_STAT_SBC_DEV_LVL_Pos         (7U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_SBC_DEV_LVL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_LVL_STAT_SBC_DEV_LVL_Msk         (0b10000000U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_CFG0_STATE_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_LVL_STAT_CFG0_STATE_Pos          (6U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_CFG0_STATE_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_LVL_STAT_CFG0_STATE_Msk          (0b01000000U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_GPIO_LVL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_LVL_STAT_GPIO_LVL_Pos            (4U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_GPIO_LVL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_LVL_STAT_GPIO_LVL_Msk            (0b00010000U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_WK_LVL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_WK_LVL_STAT_WK_LVL_Pos              (0U)
+
+/**
+ * @def     SBC_WK_LVL_STAT_WK_LVL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_WK_LVL_STAT_WK_LVL_Msk              (0b00000001U)
+
+
+/* --------------------------------  GPIO_OC_STAT  -------------------------------- */
+
+
+/**
+ * @def     SBC_GPIO_OC_STAT_GPIO_OC_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_GPIO_OC_STAT_GPIO_OC_Pos            (6U)
+
+/**
+ * @def     SBC_GPIO_OC_STAT_GPIO_OC_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_GPIO_OC_STAT_GPIO_OC_Msk            (0b01000000U)
+
+
+/* --------------------------------  GPIO_OL_STAT  -------------------------------- */
+
+
+/**
+ * @def     SBC_GPIO_OL_STAT_GPIO_OL_Pos
+ * 
+ * @brief   General status register bit position.
+ */
+#define SBC_GPIO_OL_STAT_GPIO_OL_Pos            (6U)
+
+/**
+ * @def     SBC_GPIO_OL_STAT_GPIO_OL_Msk
+ * 
+ * @brief   General status register bit mask.
+ */
+#define SBC_GPIO_OL_STAT_GPIO_OL_Msk            (0b01000000U)
+
+
+
+
+
+
+
+/* ================================================================================ */
+/* =========   Selective Wake Status Registers Position & Mask        ============= */
+/* ================================================================================ */
+
+
+
+
+/* --------------------------------  SWK_STAT  ------------------------------------ */
+
+
+/**
+ * @def     SBC_SWK_STAT_SYNC_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_STAT_SYNC_Pos                   (6U)
+
+/**
+ * @def     SBC_SWK_STAT_SYNC_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_STAT_SYNC_Msk                   (0b01000000U)
+
+/**
+ * @def     SBC_SWK_STAT_CANSIL_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_STAT_CANSIL_Pos                 (3U)
+
+/**
+ * @def     SBC_SWK_STAT_CANSIL_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_STAT_CANSIL_Msk                 (0b00001000U)
+
+/**
+ * @def     SBC_SWK_STAT_SWK_SET_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_STAT_SWK_SET_Pos                (2U)
+
+/**
+ * @def     SBC_SWK_STAT_SWK_SET_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_STAT_SWK_SET_Msk                (0b00000100U)
+
+/**
+ * @def     SBC_SWK_STAT_WUP_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_STAT_WUP_Pos                    (1U)
+
+/**
+ * @def     SBC_SWK_STAT_WUP_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_STAT_WUP_Msk                    (0b00000010U)
+
+/**
+ * @def     SBC_SWK_STAT_WUF_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_STAT_WUF_Pos                    (0U)
+
+/**
+ * @def     SBC_SWK_STAT_WUF_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_STAT_WUF_Msk                    (0b00000001U)
+
+
+
+
+
+/* --------------------------------  SWK_ECNT_STAT  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_ECNT_STAT_ECNT_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_ECNT_STAT_ECNT_Pos              (0U)
+
+/**
+ * @def     SBC_SWK_ECNT_STAT_ECNT_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_ECNT_STAT_ECNT_Msk              (0b00111111U)
+
+
+/* --------------------------------  SWK_CDR_STAT1  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_CDR_STAT1_NAVG_SAT_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_CDR_STAT1_NAVG_SAT_Pos          (0U)
+
+/**
+ * @def     SBC_SWK_CDR_STAT1_NAVG_SAT_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_CDR_STAT1_NAVG_SAT_Msk          (0b11111111U)
+
+
+/* --------------------------------  SWK_CDR_STAT2  -------------------------------- */
+
+
+/**
+ * @def     SBC_SWK_CDR_STAT2_NAVG_SAT_Pos
+ * 
+ * @brief   Selective wake status register bit position.
+ */
+#define SBC_SWK_CDR_STAT2_NAVG_SAT_Pos          (4U)
+
+/**
+ * @def     SBC_SWK_CDR_STAT2_NAVG_SAT_Msk
+ * 
+ * @brief   Selective wake status register bit mask.
+ */
+#define SBC_SWK_CDR_STAT2_NAVG_SAT_Msk          (0b11110000U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ======   Family and Product Information Register Position & Mask        ======== */
+/* ================================================================================ */
+
+
+
+/* --------------------------------  FAM_PROD_STAT  -------------------------------- */
+
+
+/**
+ * @def     SBC_FAM_PROD_STAT_FAM_Pos
+ * 
+ * @brief   Family and product register bit position.
+ */
+#define SBC_FAM_PROD_STAT_FAM_Pos               (4U)
+
+/**
+ * @def     SBC_FAM_PROD_STAT_FAM_Msk
+ * 
+ * @brief   Family and product register bit mask.
+ */
+#define SBC_FAM_PROD_STAT_FAM_Msk               (0b11110000U)
+
+/**
+ * @def     SBC_FAM_PROD_STAT_PROD_Pos
+ * 
+ * @brief   Family and product register bit position.
+ */
+#define SBC_FAM_PROD_STAT_PROD_Pos              (0U)
+
+/**
+ * @def     SBC_FAM_PROD_STAT_PROD_Msk
+ * 
+ * @brief   Family and product register bit mask.
+ */
+#define SBC_FAM_PROD_STAT_PROD_Msk              (0b00001111U)
+
+
+
+
+
+
+/* ================================================================================ */
+/* ===============   General Control Registers Enumerations        ================ */
+/* ================================================================================ */ 
+
+
+
+/* --------------------------------  M_S_CTRL  ------------------------------------ */
+
+typedef enum
+{
+    SBC_MODE_NORMAL                         = 0x00U,
+    SBC_MODE_SLEEP,
+    SBC_MODE_STOP,
+    SBC_MODE_RESET
+};
+
+typedef enum
+{
+    SBC_VCC2_OFF                            = 0x00U,
+    SBC_VCC2_ON_NORMAL,
+    SBC_VCC2_ON_NORMAL_STOP,
+    SBC_VCC2_ON_ALWAYS
+};
+
+typedef enum
+{
+    SBC_VCC1_OV_RST_NOACTION                = 0x00U,
+    SBC_VCC1_OV_RST_RESTART_FAILSAFE
+};
+
+typedef enum
+{
+    SBC_VCC1_RT_VRT1                        = 0x00U,
+    SBC_VCC1_RT_VRT2,
+    SBC_VCC1_RT_VRT3,
+    SBC_VCC1_RT_VRT4
+};
+
+
+/* --------------------------------  HW_CTRL_0  ----------------------------------- */
+
+typedef enum
+{
+    SBC_SOFT_RESET_RST_TRIGGER_SOFTRST      = 0x00U,
+    SBC_SOFT_RESET_RST_NOTRIGGER_SOFTRST
+};
+
+typedef enum
+{
+    SBC_FO_ON_NOT_ACTIVE                    = 0x00U,
+    SBC_FO_ON_ACTIVE
+};
+
+typedef enum
+{
+    SBC_CP_EN_OFF                           = 0x00U,
+    SBC_CP_EN_ON
+};
+
+typedef enum
+{
+    SBC_CFG1_RESTART_FAILSAFE_2WDFAIL       = 0x00U,
+    SBC_CFG1_RESTART_FAILSAFE_1WDFAIL
+};
+
+
+/* --------------------------------  WD_CTRL  ------------------------------------- */
+
+typedef enum
+{
+    SBC_CHECKSUM_0                       = 0x00U,
+    SBC_CHECKSUM_1
+};
+
+typedef enum
+{
+    SBC_WD_STM_EN_0_ACTIVE_STOPMODE         = 0x00U,
+    SBC_WD_STM_EN_0_NOTACTIVE_STOPMODE
+};
+
+typedef enum
+{
+    SBC_WD_WIN_TIMEOUT_WD                   = 0x00U,
+    SBC_WD_WIN_WINDOW_WD
+};
+
+typedef enum
+{
+    SBC_WD_EN_WK_BUS_NOSTART_AFTER_CANWAKE  = 0x00U,
+    SBC_WD_EN_WK_BUS_START_LONGOPENWINDOW_CANWAKE
+};
+
+typedef enum
+{
+    SBC_WD_TIMER_10MS                       = 0x00U,
+    SBC_WD_TIMER_20MS,
+    SBC_WD_TIMER_50MS,
+    SBC_WD_TIMER_100MS,
+    SBC_WD_TIMER_200MS,
+    SBC_WD_TIMER_500MS,
+    SBC_WD_TIMER_1000MS,
+    SBC_WD_TIMER_10000MS
+};
+
+
+/* --------------------------------  BUS_CTRL_0  ---------------------------------- */
+
+typedef enum
+{
+    SBC_BUS_CTRL_0_CAN_WAKECAPABLE_NOSWK    = 0x01U,
+    SBC_BUS_CTRL_0_CAN_RECEIVEONLY_NOSWK,
+    SBC_BUS_CTRL_0_CAN_NORMAL_NOSWK,
+    SBC_BUS_CTRL_0_CAN_OFF,
+    SBC_BUS_CTRL_0_CAN_WAKECAPABLE_SWK,
+    SBC_BUS_CTRL_0_CAN_RECEIVEONLY_SWK,
+    SBC_BUS_CTRL_0_CAN_NORMAL_SWK
+};
+
+
+/* --------------------------------  WK_CTRL_0  ----------------------------------- */
+
+typedef enum
+{
+    WK_CTRL_0_TIMER_WK_EN_WAKEUP_DISABLED   = 0x00U,
+    WK_CTRL_0_TIMER_WK_EN_WAKESOURCE
+};
+
+typedef enum
+{
+    SBC_WD_STM_EN_1_WATCHDOG_STOPMPDE       = 0x00U,
+    SBC_WD_STM_EN_1_NOWATCHDOG_STOPMODE
+};
+
+
+/* --------------------------------  WK_CTRL_1  ----------------------------------- */
+
+typedef enum
+{
+    SBC_INT_GLOBAL_WAKESOURCES_ONLY         = 0x00U,
+    SBC_INT_GLOBAL_ALLINFORMATIONBITS
+};
+
+typedef enum
+{
+    SBC_WK_MEAS_WK_AS_WAKEUP                = 0x00U,
+    SBC_WK_MEAS_WK_AS_VOLTAGESENSING
+};
+
+typedef enum
+{
+    SBC_WK_EN_WAKEUP_DISABLED               = 0x00U,
+    SBC_WK_EN_WAKEUP_ENABLED
+};
+
+
+/* --------------------------------  WK_PUPD_CTRL  -------------------------------- */
+
+typedef enum
+{
+    SBC_GPIO_WK_PUPD_NOPULLING              = 0x00U,
+    SBC_GPIO_WK_PUPD_PULLDOWN,
+    SBC_GPIO_WK_PUPD_PULLUP,
+    SBC_GPIO_WK_PUPD_AUTOMATIC_PULLING
+};
+
+typedef enum
+{
+    SBC_WK_PUPD_NOPULLING                   = 0x00U,
+    SBC_WK_PUPD_PULLDOWN,
+    SBC_WK_PUPD_PULLUP,
+    SBC_WK_PUPD_AUTOMATIC_PULLING
+};
+
+
+/* --------------------------------  BUS_CTRL_3  ---------------------------------- */
+
+typedef enum
+{
+    SBC_CAN_FLASH_DISABLED                  = 0x00U,
+    SBC_CAN_FLASH_ENABLED
+};
+
+
+/* --------------------------------  TIMER_CTRL  ---------------------------------- */
+
+typedef enum
+{
+    SBC_TIMER_ON_TIMEROFF_HSX_LOW           = 0x00U,
+    SBC_TIMER_ON_100US,
+    SBC_TIMER_ON_300US,
+    SBC_TIMER_ON_1MS,
+    SBC_TIMER_ON_10MS,
+    SBC_TIMER_ON_20MS,
+    SBC_TIMER_ON_TIMEROFF_HSX_HIGH
+};
+
+typedef enum
+{
+    SBC_TIMER_PER_10MS                      = 0x00U,
+    SBC_TIMER_PER_20MS,
+    SBC_TIMER_PER_50MS,
+    SBC_TIMER_PER_100MS,
+    SBC_TIMER_PER_200MS,
+    SBC_TIMER_PER_500MS,
+    SBC_TIMER_PER_1S,
+    SBC_TIMER_PER_2S,
+    SBC_TIMER_PER_5S,
+    SBC_TIMER_PER_10S,
+    SBC_TIMER_PER_20S,
+    SBC_TIMER_PER_50S,
+    SBC_TIMER_PER_100S,
+    SBC_TIMER_PER_200S,
+    SBC_TIMER_PER_500S,
+    SBC_TIMER_PER_1000S
+};
+
+
+/* --------------------------------  HW_CTRL_1  ----------------------------------- */
+
+typedef enum
+{
+    SBC_RSTN_HYS_DEFAULT                    = 0x00U,
+    SBC_RSTN_HYS_HIGHEST_VRT
+};
+
+typedef enum
+{
+    SBC_TSD2_DEL_NO_WAIT_RELEASE_EXTENSION  = 0x00U,
+    SBC_TSD2_DEL_64S_AFTER_16_TSD2_EVENTS
+};
+
+typedef enum
+{
+    SBC_RSTN_DEL_TRD1                       = 0x00U,
+    SBC_RSTN_DEL_TRD2
+};
+
+typedef enum
+{
+    SBC_CFG_LOCK_0_NOTLOCKED                = 0x00U,
+    SBC_CFG_LOCK_0_LOCKED
+};
+
+
+/* --------------------------------  HW_CTRL_2  ----------------------------------- */
+
+typedef enum
+{
+    SBC_2MHZ_FREQ_1_8_MHZ                   = 0x00U,
+    SBC_2MHZ_FREQ_2_0_MHZ,
+    SBC_2MHZ_FREQ_2_2_MHZ,
+    SBC_2MHZ_FREQ_2_4_MHZ
+};
+
+typedef enum
+{
+    SBC_I_PEAK_TH_LOW                       = 0x00U,
+    SBC_I_PEAK_TH_HIGH
+};
+
+typedef enum
+{
+    SBC_SS_MOD_FR_DISABLED                  = 0x00U,
+    SBC_SS_MOD_FR_15_6KHZ,
+    SBC_SS_MOD_FR_31_2KHZ,
+    SBC_SS_MOD_FR_62_5KHZ
+};
+
+typedef enum
+{
+    SBC_CFG_LOCK_1_NOTLOCKED                = 0x00U,
+    SBC_CFG_LOCK_1_LOCKED
+};
+
+
+/* --------------------------------  GPIO_CTRL  ----------------------------------- */
+
+typedef enum
+{
+    SBC_GPIO_FO                             = 0x00U,
+    SBC_GPIO_HSS_TIMER                      = 0x03U,
+    SBC_GPIO_OFF,
+    SBC_GPIO_WAKE_INPUT,
+    SBC_GPIO_LSS_PWM,
+    SBC_GPIO_HSS_PWM
+};
+
+
+/* --------------------------------  PWM_CTRL  ------------------------------------ */
+
+typedef enum
+{
+    SBC_PWM_DC_0                            = 0x00U,
+    SBC_PWM_DC_10                           = 0x19U,
+    SBC_PWM_DC_20                           = 0x51U,
+    SBC_PWM_DC_30                           = 0x4DU,
+    SBC_PWM_DC_40                           = 0x66U,
+    SBC_PWM_DC_50                           = 0x80U,
+    SBC_PWM_DC_60                           = 0x99U,
+    SBC_PWM_DC_70                           = 0xB3U,
+    SBC_PWM_DC_80                           = 0xCCU,
+    SBC_PWM_DC_90                           = 0xE6U,
+    SBC_PWM_DC_100                          = 0xFFU
+};
+
+
+/* --------------------------------  PWM_FREQ_CTRL  ------------------------------- */
+
+typedef enum
+{
+    SBC_PWM_FREQ_100HZ                      = 0x00U,
+    SBC_PWM_FREQ_200HZ,
+    SBC_PWM_FREQ_325HZ,
+    SBC_PWM_FREQ_400HZ
+};
+
+
+/* --------------------------------  HW_CTRL_3 ----------------------------------- */
+
+typedef enum
+{
+    SBC_TSD_THR_DEFAULT                     = 0x00U,
+    SBC_TSD_THR_HIGHER
+};
+
+typedef enum
+{
+    SBC_ICC1_LIM_ADJ_750MA                  = 0x00U,
+    SBC_ICC1_LIM_ADJ_1000MA,
+    SBC_ICC1_LIM_ADJ_1200MA,
+    SBC_ICC1_LIM_ADJ_1500MA
+};
+
+
+
+
+
+
+/* ================================================================================ */
+/* ==========   Selective Wake Control Registers Enumerations        ============== */
+/* ================================================================================ */ 
+
+
+
+/* --------------------------------  SWK_CTRL  ------------------------------------ */
+
+typedef enum
+{ 
+    SBC_OSC_CAL_DISABLED                    = 0x00U,
+    SBC_OSC_CAL_ENABLED
+};
+
+typedef enum
+{
+    SBC_TRIM_EN_LOCKED                      = 0x00U,
+    SBC_TRIM_EN_UNLOCKED                    = 0x03U
+};
+
+typedef enum
+{
+    SBC_CANTO_MASK_NOINT                    = 0x00U,
+    SBC_CANTO_MASK_INT_ON_TO
+};
+
+typedef enum
+{
+    SBC_CFG_VAL_NOTVALID                    = 0x00U,
+    SBC_CFG_VAL_VALID
+};
+
+
+/* --------------------------------  SWK_ID0_CTRL --------------------------------- */
+
+typedef enum
+{
+    SBC_RTR_NORMAL_DATA_FRAME               = 0x00U,
+    SBC_RTR_REMOTE_TRANSMIT_REQUEST
+};
+
+typedef enum
+{
+    SBC_IDE_STANDARD                         = 0x00U,
+    SBC_IDE_EXTENDED
+};
+
+
+/* --------------------------------  SWK_DLC_CTRL --------------------------------- */
+
+typedef enum
+{
+    SBC_DLC_0BYTES                          = 0x00U,
+    SBC_DLC_1BYTES,
+    SBC_DLC_2BYTES,
+    SBC_DLC_3BYTES,
+    SBC_DLC_4BYTES,
+    SBC_DLC_5BYTES,
+    SBC_DLC_6BYTES,
+    SBC_DLC_7BYTES,
+    SBC_DLC_8BYTES
+};
+
+
+/* --------------------------------  SWK_CAN_FD_CTRL ------------------------------ */
+
+typedef enum
+{
+    SBC_DIS_ERR_CNT_ENABLED                 = 0x00U,
+    SBC_DIS_ERR_CNT_DISABLED
+};
+
+typedef enum
+{
+    SBC_RX_FILT_BYP_NOTBYPASSED             = 0x00U,
+    SBC_RX_FILT_BYP_BYPASSED
+};
+
+typedef enum
+{
+    SBC_FD_FILTER_50NS                      = 0x00U,
+    SBC_FD_FILTER_100NS,
+    SBC_FD_FILTER_150NS,
+    SBC_FD_FILTER_200NS,
+    SBC_FD_FILTER_250NS,
+    SBC_FD_FILTER_300NS,
+    SBC_FD_FILTER_350NS,
+    SBC_FD_FILTER_700NS
+};
+
+typedef enum
+{
+    SBC_CAN_FD_EN_DISABLED                  = 0x00U,
+    SBC_CAN_FD_EN_ENABLED
+};
+
+
+/* --------------------------------  SWK_OPT_CTRL --------------------------------- */
+
+typedef enum
+{ 
+    SBC_RX_WK_SEL_LOWPOWER                  = 0x00U,
+    SBC_RX_WK_SEL_STANDARD
+};
+
+
+/* --------------------------------  SWK_CDR_CTRL1 -------------------------------- */
+
+typedef enum
+{ 
+    SBC_SEL_FILT_TC8                        = 0x00U,
+    SBC_SEL_FILT_TC16,
+    SBC_SEL_FILT_TC32,
+    SBC_SEL_FILT_ADAPT
+};
+
+typedef enum
+{
+    SBC_CDR_EN_DISABLED                     = 0x00U,
+    SBC_CDR_EN_ENABLED
+};
+
+
+/* --------------------------------  SWK_CDR_CTRL2 -------------------------------- */
+
+typedef enum
+{
+    SBC_SEL_OSC_CLK_80MHZ                   = 0x00U,
+    SBC_SEL_OSC_CLK_40MHZ,
+    SBC_SEL_OSC_CLK_20MHZ,
+    SBC_SEL_OSC_CLK_10MHZ
+};
+
+
+
+
+
+
+/* ================================================================================ */
+/* ==========   General Status Information Registers Enumerations        ========== */
+/* ================================================================================ */ 
+
+
+
+/* --------------------------------  SUP_STAT_1  ---------------------------------- */
+
+typedef enum
+{
+    SBC_VS_UV_NOEVENT                       = 0x00U,
+    SBC_VS_UV_EVENT
+};
+
+typedef enum
+{
+    SBC_VS_OV_NOEVENT                       = 0x00U,
+    SBC_VS_OV_EVENT
+};
+
+typedef enum
+{ 
+    SBC_VCC1_OV_NOEVENT                     = 0x00U,
+    SBC_VCC1_OV_EVENT
+};
+
+typedef enum
+{
+    SBC_VCC1_UV_PREWARN_NOEVENT             = 0x00U,
+    SBC_VCC1_UV_PREWARN_EVENT
+};
+
+
+/* --------------------------------  SUP_STAT_0 ----------------------------------- */
+
+typedef enum
+{
+    SBC_POR_NOEVENT                         = 0x00U,
+    SBC_POR_EVENT
+};
+
+typedef enum
+{
+    SBC_VCC2_OT_NOEVENT                     = 0x00U,
+    SBC_VCC2_OT_EVENT
+};
+
+typedef enum
+{
+    SBC_VCC2_UV_NOEVENT                     = 0x00U,
+    SBC_VCC2_UV_EVENT
+};
+
+typedef enum
+{
+    SBC_VCC1_SC_NOEVENT                     = 0x00U,
+    SBC_VCC1_SC_TO_GND_EVENT
+};
+
+typedef enum
+{
+    SBC_VCC1_UV_NOEVENT                     = 0x00U,
+    SBC_VCC1_UV_EVENT
+};
+
+
+/* --------------------------------  THERM_STAT ----------------------------------- */
+
+typedef enum
+{
+    SBC_TSD2_SAFE_NOSAFESTATE               = 0x00U,
+    SBC_TSD2_SAFE_SAFESTATE_DETECTED
+};
+
+typedef enum
+{
+    SBC_TSD2_NOEVENT                        = 0x00U,
+    SBC_TSD2_EVENT
+};
+
+typedef enum
+{
+    SBC_TSD1_NOEVENT                        = 0x00U,
+    SBC_TSD1_EVENT
+};
+
+typedef enum
+{
+    SBC_TPW_NOEVENT                         = 0x00U,
+    SBC_TPW_EVENT
+};
+
+
+/* --------------------------------  DEV_STAT ------------------------------------- */
+
+typedef enum
+{
+    SBC_DEV_STAT_CLEARED                    = 0x00U,
+    SBC_DEV_STAT_RESTART_AFTER_FAIL,
+    SBC_DEV_STAT_SLEEP_MODE
+};
+
+typedef enum
+{
+    SBC_WD_FAIL_NOFAIL                      = 0x00U,
+    SBC_WD_FAIL_1FAIL,
+    SBC_WD_FAIL_2FAIL
+};
+
+typedef enum
+{
+    SBC_SPI_FAIL_NOEVENT                    = 0x00U,
+    SBC_SPI_FAIL_EVENT
+};
+
+typedef enum
+{
+    SBC_FAILURE_NOEVENT                     = 0x00U,
+    SBC_FAILURE_EVENT
+};
+
+
+/* --------------------------------  BUS_STAT ------------------------------------- */
+
+typedef enum
+{
+    SBC_CANTO_NORMAL                        = 0x00U,
+    SBC_CANTO_TIMEOUT
+};
+
+typedef enum
+{
+    SBC_SYSERR_NOEVENT                      = 0x00U,
+    SBC_SYSERR_DETECTED
+};
+
+typedef enum
+{
+    SBC_CAN_FAIL_NO_FAIL                    = 0x00U,
+    SBC_CAN_FAIL_TSD,
+    SBC_CAN_FAIL_TXD_DOM_TO,
+    SBC_CAN_FAIL_BUS_DOM_TO
+};
+
+typedef enum
+{
+    SBC_VCAN_UV_NOEVENT                     = 0x00U,
+    SBC_VCAN_UV_EVENT
+};
+
+
+/* --------------------------------  WK_STAT_0 ------------------------------------ */
+
+typedef enum
+{
+    SBC_CAN_WU_NOEVENT                      = 0x00U,
+    SBC_CAN_WU_EVENT
+};
+
+typedef enum
+{
+    SBC_TIMER_WU_NOEVENT                    = 0x00U,
+    SBC_TIMER_WU_EVENT
+};
+
+typedef enum
+{
+    SBC_WK_WU_NOEVENT                       = 0x00U,
+    SBC_WK_WU_EVENT
+};
+
+
+/* --------------------------------  WK_STAT_1 ------------------------------------ */
+
+typedef enum
+{
+    SBC_GPIO_WK_WU_NOEVENT                  = 0x00U,
+    SBC_GPIO_WK_WU_EVENT
+};
+
+
+/* --------------------------------  WK_LVL_STAT ---------------------------------- */
+
+typedef enum
+{
+    SBC_DEV_LVL_NORMAL                      = 0x00U,
+    SBC_DEV_LVL_DEVELOPMENT_MODE
+};
+
+typedef enum
+{
+    SBC_CFG0_STATE_CONFIG_2_4               = 0x00U,
+    SBC_CFG0_STATE_CONFIG_1_3
+};
+
+typedef enum
+{
+    SBC_GPIO_LVL_LOW                        = 0x00U,
+    SBC_GPIO_LVL_HIGH
+};
+
+typedef enum
+{
+    SBC_WK_LVL_LOW                          = 0x00U,
+    SBC_WK_LVL_HIGH
+};
+
+
+/* --------------------------------  GPIO_OC_STAT --------------------------------- */
+
+typedef enum
+{
+    SBC_GPIO_OC_NOEVENT                     = 0x00U,
+    SBC_GPIO_OC_EVENT
+};
+
+
+/* --------------------------------  GPIO_OL_STAT --------------------------------- */
+
+typedef enum
+{
+    SBC_GPIO_OL_NOEVENT                     = 0x00U,
+    SBC_GPIO_OL_EVENT
+};
+
+
+
+
+
+
+/* ================================================================================ */
+/* =============   Selective Wake Status Registers Enumerations        ============ */
+/* ================================================================================ */ 
+
+
+
+/* --------------------------------  SWK_STAT  ------------------------------------ */
+
+typedef enum
+{
+    SBC_SYNC_NOT_SYNCHRONOUS                = 0x00U,
+    SBC_SYNC_VALID_FRAME_RECEIVED
+};
+
+typedef enum
+{
+    SBC_CANSIL_NOT_EXCEEDED                 = 0x00U,
+    SBC_CANSIL_EXCEEDED
+};
+
+typedef enum
+{
+    SBC_SWK_SET_SWK_NOT_ACTIVE              = 0x00U,
+    SBC_SWK_SET_SWK_ACTIVE
+};
+
+typedef enum
+{
+    SBC_WUP_NO_WUP                          = 0x00U,
+    SBC_WUP_DETECTED
+};
+
+typedef enum
+{
+    SBC_WUF_NO_WUF                          = 0x00U,
+    SBC_WUF_DETECTED
+};
+
+
+/* --------------------------------  SWK_ECNT_STAT  ------------------------------ */
+
+typedef enum
+{
+    SBC_ECNT_NOEVENT                        = 0x00U,
+    SBC_ECNT_31_FRAME_ERRORS                = 0x1FU,
+    SBC_ECNT_ERROR_OVERFLOW                 = 0x20U
+};
+
+
+/* ================================================================================ */
+/* ========   Family and Product Information Registers Enumerations        ======== */
+/* ================================================================================ */ 
+
+
+
+/* --------------------------------  FAM_PROD_STAT  ------------------------------- */
+
+typedef enum
+{
+    SBC_FAM_DRIVER                          = 0x01U,
+    SBC_FAM_DCDC,
+    SBC_FAM_MIDRANGE,
+    SBC_FAM_MULTICAN,
+    SBC_FAM_LITE,
+    SBC_FAM_MIDRANGEPLUS                    = 0x07U
+};
+
+typedef enum
+{
+    SBC_PROD_TLE9461                        = 0x06U,
+    SBC_PROD_TLE9461V33,
+    SBC_PROD_TLE9471                        = 0x0EU,
+    SBC_PROD_TLE9471V33
+};
+
+
+#endif  /* TLE94x1_DEFINES_H */
diff --git a/cva_bootloader_m0128/src/TLE9461/TLE94x1_ISR.h b/cva_bootloader_m0128/src/TLE9461/TLE94x1_ISR.h
new file mode 100644
index 0000000..b40bbbe
--- /dev/null
+++ b/cva_bootloader_m0128/src/TLE9461/TLE94x1_ISR.h
@@ -0,0 +1,127 @@
+/*********************************************************************************************************************
+ * Copyright (c) 2019, Infineon Technologies AG
+ *
+ * 
+ * Distributed under the Boost Software License, Version 1.0.
+ * 
+ * 
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ * 
+ * Permission is hereby granted, free of charge, to any person or organization
+ * obtaining a copy of the software and accompanying documentation covered by
+ * this license (the "Software") to use, reproduce, display, distribute,
+ * execute, and transmit the Software, and to prepare derivative works of the
+ * Software, and to permit third-parties to whom the Software is furnished to
+ * do so, all subject to the following:
+ * 
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer,
+ * must be included in all copies of the Software, in whole or in part, and
+ * all derivative works of the Software, unless such copies or derivative
+ * works are solely in the form of machine-executable object code generated by
+ * a source language processor.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ *********************************************************************************************************************/
+
+
+/****************************************************************************************************//**
+ * @file        TLE94x1_ISR.h
+ *
+ * @brief       Declaration file for ISR-Vectors and ISR related functions
+ * 
+ * @version     V1.0.0
+ * @date        15. April 2019
+ * @author      Markus Noll / markus.noll@infineon.com
+ * @author      Yannek Micha Rixen / Yannek.Rixen@infineon.com
+ *******************************************************************************************************/
+
+
+
+
+#ifndef TLE94x1_ISR_H
+#define TLE94x1_ISR_H
+
+
+
+
+
+
+
+/* ================================================================================ */
+/* ============================   HEADER FILES   ================================== */
+/* ================================================================================ */ 
+
+#include "TLE94x1_DEFINES.h"
+
+
+
+
+
+
+
+
+/* ================================================================================ */
+/* ================================   MACROS   ==================================== */
+/* ================================================================================ */ 
+
+
+/**
+ * @def     SBC_ISR_VECTOR
+ *
+ * @brief   Vector defining the handling of interrupts.
+ * 
+ *          Vectors of this type have to be registered by the SBC_Register_Callback method.
+ */
+#define SBC_ISR_VECTOR(REG,MASK,POS,COMPARE)    ((((uint32_t)REG) << 24) | (((uint32_t)MASK) << 16) | (((uint32_t)POS) << 8) | ((uint32_t)COMPARE))
+
+
+
+
+
+
+/* ================================================================================ */
+/* =======================   General Interrupt Defines   ========================== */
+/* ================================================================================ */ 
+
+
+
+/* Interrupts based on WK_STAT_0 and WK_STAT_1 register are always available */
+#define SBC_ISR_CAN_WU                          SBC_ISR_VECTOR(SBC_WK_STAT_0,       SBC_WK_STAT_0_CAN_WU_Msk,       SBC_WK_STAT_0_CAN_WU_Pos,       SBC_CAN_WU_EVENT)
+#define SBC_ISR_TIMER_WU                        SBC_ISR_VECTOR(SBC_WK_STAT_0,       SBC_WK_STAT_0_TIMER_WU_Msk,     SBC_WK_STAT_0_TIMER_WU_Pos,     SBC_TIMER_WU_EVENT)
+#define SBC_ISR_WK_WU                           SBC_ISR_VECTOR(SBC_WK_STAT_0,       SBC_WK_STAT_0_WK_WU_Msk,        SBC_WK_STAT_0_WK_WU_Pos,        SBC_WK_WU_EVENT)
+#define SBC_ISR_GPIO_WK_WU                      SBC_ISR_VECTOR(SBC_WK_STAT_1,       SBC_WK_STAT_1_GPIO_WK_WU_Msk,   SBC_WK_STAT_1_GPIO_WK_WU_Pos,   SBC_GPIO_WK_WU_EVENT)
+
+
+/* Following interrupts only usable if INT_GLOBAL bit is set to '1' */
+#define SBC_ISR_VS_UV                           SBC_ISR_VECTOR(SBC_SUP_STAT_1,      SBC_SUP_STAT_1_VS_UV_Msk,       SBC_SUP_STAT_1_VS_UV_Pos,       SBC_VS_UV_EVENT)
+#define SBC_ISR_VS_OV                           SBC_ISR_VECTOR(SBC_SUP_STAT_1,      SBC_SUP_STAT_1_VS_OV_Msk,       SBC_SUP_STAT_1_VS_OV_Pos,       SBC_VS_OV_EVENT)
+#define SBC_ISR_VCC1_OV                         SBC_ISR_VECTOR(SBC_SUP_STAT_1,      SBC_SUP_STAT_1_VCC1_OV_Msk,     SBC_SUP_STAT_1_VCC1_OV_Pos,     SBC_VCC1_OV_EVENT)
+#define SBC_ISR_VCC1_UV_PREWARN                 SBC_ISR_VECTOR(SBC_SUP_STAT_1,      SBC_SUP_STAT_1_VCC1_WARN_Msk,   SBC_SUP_STAT_1_VCC1_WARN_Pos,   SBC_VCC1_UV_PREWARN_EVENT)
+#define SBC_ISR_VCC2_OT                         SBC_ISR_VECTOR(SBC_SUP_STAT_0,      SBC_SUP_STAT_0_VCC2_OT_Msk,     SBC_SUP_STAT_0_VCC2_OT_Pos,     SBC_VCC2_OT_EVENT)
+#define SBC_ISR_VCC2_UV                         SBC_ISR_VECTOR(SBC_SUP_STAT_0,      SBC_SUP_STAT_0_VCC2_UV_Msk,     SBC_SUP_STAT_0_VCC2_UV_Pos,     SBC_VCC2_UV_EVENT)
+#define SBC_ISR_VCC1_UV                         SBC_ISR_VECTOR(SBC_SUP_STAT_0,      SBC_SUP_STAT_0_VCC1_UV_Msk,     SBC_SUP_STAT_0_VCC1_UV_Pos,     SBC_VCC1_UV_EVENT)
+#define SBC_ISR_TSD2_SAFESTATE                  SBC_ISR_VECTOR(SBC_THERM_STAT,      SBC_THERM_STAT_TSD2_SAFE_Msk,   SBC_THERM_STAT_TSD2_SAFE_Pos,   SBC_TSD2_SAFE_SAFESTATE_DETECTED)
+#define SBC_ISR_TSD1                            SBC_ISR_VECTOR(SBC_THERM_STAT,      SBC_THERM_STAT_TSD1_Msk,        SBC_THERM_STAT_TSD1_Pos,        SBC_TSD1_EVENT)
+#define SBC_ISR_TPW                             SBC_ISR_VECTOR(SBC_THERM_STAT,      SBC_THERM_STAT_TPW_Msk,         SBC_THERM_STAT_TPW_Pos,         SBC_TPW_EVENT)
+#define SBC_ISR_RESTART_AFTER_FAIL              SBC_ISR_VECTOR(SBC_DEV_STAT,        SBC_DEV_STAT_DEV_STAT_Msk,      SBC_DEV_STAT_DEV_STAT_Pos,      SBC_DEV_STAT_RESTART_AFTER_FAIL)
+#define SBC_ISR_FROM_SLEEPMODE                  SBC_ISR_VECTOR(SBC_DEV_STAT,        SBC_DEV_STAT_DEV_STAT_Msk,      SBC_DEV_STAT_DEV_STAT_Pos,      SBC_DEV_STAT_SLEEP_MODE)
+#define SBC_ISR_WD_FAIL_1                       SBC_ISR_VECTOR(SBC_DEV_STAT,        SBC_DEV_STAT_WD_FAIL_Msk,       SBC_DEV_STAT_WD_FAIL_Pos,       SBC_WD_FAIL_1FAIL)
+#define SBC_ISR_WD_FAIL_2                       SBC_ISR_VECTOR(SBC_DEV_STAT,        SBC_DEV_STAT_WD_FAIL_Msk,       SBC_DEV_STAT_WD_FAIL_Pos,       SBC_WD_FAIL_2FAIL)
+#define SBC_ISR_FAILURE                         SBC_ISR_VECTOR(SBC_DEV_STAT,        SBC_DEV_STAT_FAILURE_Msk,       SBC_DEV_STAT_FAILURE_Pos,       SBC_FAILURE_EVENT)
+#define SBC_ISR_CAN_TSD                         SBC_ISR_VECTOR(SBC_BUS_STAT,        SBC_BUS_STAT_CAN_FAIL_Msk,      SBC_BUS_STAT_CAN_FAIL_Pos,      SBC_CAN_FAIL_TSD)
+#define SBC_ISR_CAN_TXD_DOM_TO                  SBC_ISR_VECTOR(SBC_BUS_STAT,        SBC_BUS_STAT_CAN_FAIL_Msk,      SBC_BUS_STAT_CAN_FAIL_Pos,      SBC_CAN_FAIL_TXD_DOM_TO)
+#define SBC_ISR_CAN_BUS_DOM_TO                  SBC_ISR_VECTOR(SBC_BUS_STAT,        SBC_BUS_STAT_CAN_FAIL_Msk,      SBC_BUS_STAT_CAN_FAIL_Pos,      SBC_CAN_FAIL_BUS_DOM_TO)
+#define SBC_ISR_VCAN_UV                         SBC_ISR_VECTOR(SBC_BUS_STAT,        SBC_BUS_STAT_VCAN_UV_Msk,       SBC_BUS_STAT_VCAN_UV_Pos,       SBC_VCAN_UV_EVENT)
+#define SBC_ISR_GPIO_OC                         SBC_ISR_VECTOR(SBC_GPIO_OC_STAT,    SBC_GPIO_OC_STAT_GPIO_OC_Msk,   SBC_GPIO_OC_STAT_GPIO_OC_Pos,   SBC_GPIO_OC_EVENT)
+#define SBC_ISR_GPIO_OL                         SBC_ISR_VECTOR(SBC_GPIO_OL_STAT,    SBC_GPIO_OL_STAT_GPIO_OL_Msk,   SBC_GPIO_OL_STAT_GPIO_OL_Pos,   SBC_GPIO_OL_EVENT)
+
+
+#endif  /*TLE94x1_ISR_H*/
diff --git a/cva_bootloader_m0128/src/TLE9461/TLE94x1_SPI.c b/cva_bootloader_m0128/src/TLE9461/TLE94x1_SPI.c
new file mode 100644
index 0000000..c9a1a9f
--- /dev/null
+++ b/cva_bootloader_m0128/src/TLE9461/TLE94x1_SPI.c
@@ -0,0 +1,156 @@
+/*********************************************************************************************************************
+ * Copyright (c) 2019, Infineon Technologies AG
+ *
+ * 
+ * Distributed under the Boost Software License, Version 1.0.
+ * 
+ * 
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ * 
+ * Permission is hereby granted, free of charge, to any person or organization
+ * obtaining a copy of the software and accompanying documentation covered by
+ * this license (the "Software") to use, reproduce, display, distribute,
+ * execute, and transmit the Software, and to prepare derivative works of the
+ * Software, and to permit third-parties to whom the Software is furnished to
+ * do so, all subject to the following:
+ * 
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer,
+ * must be included in all copies of the Software, in whole or in part, and
+ * all derivative works of the Software, unless such copies or derivative
+ * works are solely in the form of machine-executable object code generated by
+ * a source language processor.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ *********************************************************************************************************************/
+
+
+/****************************************************************************************************//**
+ * @file        TLE94x1_SPI.c
+ *
+ * @brief       Implementation of all SPI related functions
+ *
+ * @version     V1.0.0
+ * @date        15. April 2019
+ * @author      Markus Noll / markus.noll@infineon.com
+ * @author      Yannek Micha Rixen / Yannek.Rixen@infineon.com
+ *******************************************************************************************************/
+
+
+
+
+/* ================================================================================ */
+/* ============================   HEADER FILES     ================================ */
+/* ================================================================================ */ 
+
+#include "TLE94x1_SPI.h"
+#include "mcu.h"
+
+void SPI_PortInit(void);
+
+
+
+
+/* ================================================================================ */
+/* =======================   SPI communication functions     ====================== */
+/* ================================================================================ */ 
+
+
+uint8_t spitxbuf[10],spirxbuf[10];
+extern McuType mcu;
+uint8_t SBC_SPI_INIT(void) {
+    SpiDrv_InitCfgType masterCfg;
+
+    SPI_PortInit();
+
+    SpiDrv_GetDefaultConfig(&masterCfg);
+    masterCfg.basicParameters.isMasterNode = true;
+    masterCfg.basicParameters.baudRate     = 1000000ul;
+    masterCfg.basicParameters.pcsSelection     = SPIDRV_PCS_SEL_PCS0;
+    //masterCfg.basicParameters.clockPolarity = SPIDRV_CLK_POLARITY_IDLE_IN_HIGH;
+    masterCfg.basicParameters.clockPhase    = SPIDRV_CLK_PHASE_DATA_SAMPLE_ON_TRAILING_EDGE;
+
+    while(ClockDrv_GetFreq(&mcu.clockDrv, CLOCKDRV_SPI0, &masterCfg.basicParameters.busClockFreq) == false)
+    {
+        ;
+    }
+    SpiDrv_SetConfig(&mcu.spiDrv0, &masterCfg);
+
+    SpiDrv_SetRxFifoWaterMask(&mcu.spiDrv0, 0);
+    //SpiDrv_SetIsrConfig(&mcu.spiDrv0, SPIDRV_ISR_SRC_RX_DATA, true);
+
+    /* Enable the SPI interrupts */
+    return 0;
+}
+
+
+
+uint16_t SBC_SPI_TRANSFER16(uint8_t Upper, uint8_t Lower) {
+    uint16_t ret;
+    //LPSPI_DRV_SetPcs(LPSPICOM1,LPSPI_PCS0,LPSPI_ACTIVE_LOW);
+    spitxbuf[0] = Upper;
+    spitxbuf[1] = Lower;
+
+    SpiDrv_MasterSyncTransfer(&mcu.spiDrv0,SPIDRV_FRAME_SIZE_BIT_TYPE_BYTE,2,spitxbuf,spirxbuf);
+    //LPSPI_DRV_MasterTransferBlocking(LPSPICOM1,spitxbuf,spirxbuf,2,10);
+    ret = spirxbuf[0];
+    ret <<= 8;
+    ret |= spirxbuf[1];
+    //LPSPI_DRV_SetPcs(LPSPICOM1,LPSPI_PCS0,LPSPI_ACTIVE_HIGH);
+    return ret;
+}
+
+
+/********************CVA SPI DRV**********************/
+
+void SPI0_Handler(void)
+{
+    if(SpiDrv_GetStatus(&mcu.spiDrv0, SPIDRV_STATUS_RX_DATA) == true && SpiDrv_GetIsrConfig(&mcu.spiDrv0, SPIDRV_ISR_SRC_RX_DATA) == true)
+    {
+        //spi0IrqCnt++;
+        //uint8_t len = SpiDrv_AsyncReceive(&mcu.spiDrv0, (void *)masterRxBuff, true);
+    }
+}
+
+void SPI_PortInit(void)
+{
+    /* SPI CS */
+    PinsDrv_SetMuxModeSel(&mcu.pta, 12, PINSDRV_MUX_ALT7);
+    /* Strength driver */
+    PortReg_SetPcrDrvStr(mcu.pta.port, 12, 1);
+    /* fast slew rate */
+    PortReg_SetPcrSr(mcu.pta.port, 12, 1);
+
+    /* SPI CLK */
+    PinsDrv_SetMuxModeSel(&mcu.pta, 11, PINSDRV_MUX_ALT7);
+    /* Strength driver */
+    PortReg_SetPcrDrvStr(mcu.pta.port, 11, 1);
+    /* fast slew rate */
+    PortReg_SetPcrSr(mcu.pta.port, 11, 1);
+
+    /* SPI SIN */
+    PinsDrv_SetMuxModeSel(&mcu.pta, 10, PINSDRV_MUX_ALT7);
+    /* Strength driver */
+    PortReg_SetPcrDrvStr(mcu.pta.port, 10, 1);
+    /* fast slew rate */
+    PortReg_SetPcrSr(mcu.pta.port, 10, 1);
+
+    /* SPI SOUT */
+    PinsDrv_SetMuxModeSel(&mcu.pta, 9, PINSDRV_MUX_ALT7);
+    /* Strength driver */
+    PortReg_SetPcrDrvStr(mcu.pta.port, 9, 1);
+    /* fast slew rate */
+    PortReg_SetPcrSr(mcu.pta.port, 9, 1);
+}
+
+void SPI_TEST_TASK(void)
+{
+    
+}
\ No newline at end of file
diff --git a/cva_bootloader_m0128/src/TLE9461/TLE94x1_SPI.h b/cva_bootloader_m0128/src/TLE9461/TLE94x1_SPI.h
new file mode 100644
index 0000000..abf88cc
--- /dev/null
+++ b/cva_bootloader_m0128/src/TLE9461/TLE94x1_SPI.h
@@ -0,0 +1,95 @@
+/*********************************************************************************************************************
+ * Copyright (c) 2019, Infineon Technologies AG
+ *
+ * 
+ * Distributed under the Boost Software License, Version 1.0.
+ * 
+ * 
+ * Boost Software License - Version 1.0 - August 17th, 2003
+ * 
+ * Permission is hereby granted, free of charge, to any person or organization
+ * obtaining a copy of the software and accompanying documentation covered by
+ * this license (the "Software") to use, reproduce, display, distribute,
+ * execute, and transmit the Software, and to prepare derivative works of the
+ * Software, and to permit third-parties to whom the Software is furnished to
+ * do so, all subject to the following:
+ * 
+ * The copyright notices in the Software and this entire statement, including
+ * the above license grant, this restriction and the following disclaimer,
+ * must be included in all copies of the Software, in whole or in part, and
+ * all derivative works of the Software, unless such copies or derivative
+ * works are solely in the form of machine-executable object code generated by
+ * a source language processor.
+ * 
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+ * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+ * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ * 
+ *********************************************************************************************************************/
+
+
+/****************************************************************************************************//**
+ * @file        TLE94x1_SPI.h
+ *
+ * @brief       Declaration file for TLE94x1 SBC family device SPI functions
+ *
+ * @version     V1.0.0
+ * @date        15. April 2019
+ * @author      Markus Noll / markus.noll@infineon.com
+ * @author      Yannek Micha Rixen / Yannek.Rixen@infineon.com
+ *******************************************************************************************************/
+
+
+
+ 
+#ifndef TLE94x1_SPI_H
+#define TLE94x1_SPI_H
+ 
+
+
+
+
+ 
+/* ================================================================================ */
+/* ============================   HEADER FILES     ================================ */
+/* ================================================================================ */ 
+
+#include <stdint.h>
+
+
+
+/* ================================================================================ */
+/* =============================   SPI Functions     ============================== */
+/* ================================================================================ */
+
+/**
+ * @brief   IMPORTANT! THIS METHOD HAS TO BE DEFINED BY THE USER
+ * 
+ *          The function has to initialze the SPI of the uC and will be called once during SBC_Init().
+ *          In case, the SPI hardware is already initialized by some other code before, it can be left blank.
+ * 
+ * @retval  Method has to return 0 if initialization was successful.
+ */
+uint8_t SBC_SPI_INIT(void);
+
+/**
+ * @brief   IMPORTANT! THIS METHOD HAS TO BE DEFINED BY THE USER
+ * 
+ *          The function will be called by the library everytime when a SPI communication is needed.
+ *          The function proceeds a bidirectional 16-bit transfer to/from the SBC  .
+ *          As some UCs only supports 8-Bit transfers, the input arguments are split in two 8-bit arguments.
+ *          For further implementation details have a look at datasheet chapter 13.1 or at the Arduino-examples.
+ * 
+ * @param   Upper   The first 8 bit to transmit to the SBC.
+ * @param   Lower   The second 8 bit to transmit to the SBC.
+ * @retval  The function will return all 16 bits received from the SBC. 
+ *          Bit[15:8] are the first 8 bits received (Status-Information-Field).
+ *          Bit[7:0] is the data-field transmitted of the SBC.
+ */	
+uint16_t SBC_SPI_TRANSFER16(uint8_t Upper, uint8_t Lower);
+
+#endif /* TLE94x1_SPI_H */
diff --git a/cva_bootloader_m0128/src/main.c b/cva_bootloader_m0128/src/main.c
index 91eef05..94e6120 100644
--- a/cva_bootloader_m0128/src/main.c
+++ b/cva_bootloader_m0128/src/main.c
@@ -29,7 +29,7 @@
 #include "fls.h"
 #include "private_driver/uds/user/uds_user.h"
 #include "SEGGER_RTT.h"
-
+#include "TLE94x1.h"
 /*******************************************************************************
  * the defines
  ******************************************************************************/
@@ -94,7 +94,7 @@ static uint32_t             sBootloader_Req ;
 
 #pragma location = ".bootloaderInfo"
 const Bootloade_CfgInfoType sBootloader_Version __attribute__((used, section(".bootloaderInfo"))) = {
-    .HWVersion = "HW01",
+    .HWVersion = "DV02",
     .BLVersion = "BL0101",
     .bootBuildDate = __DATE__,
     .bootBuildTime = __TIME__,
@@ -807,7 +807,7 @@ uint8_t flashCfgSecInfo[40]  =
   0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
   0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
 };
-
+uint8_t testdata[8] = {0,0,0,0, 0,0,0,0,};
 int main(void)
 {
     uint32_t temp;
@@ -845,6 +845,18 @@ int main(void)
     ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTB, &clockConfig);
     ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTC, &clockConfig);
 
+
+    /* Setup the SPI clock */
+    clockConfig.gating = true;
+    clockConfig.source = CLOCKDRV_PLL_DIV;
+    ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_SPI0, &clockConfig);
+
+    uint32_t tTcr =  SpiReg_GetTcr((const SpiRegType *)&mcu.spiDrv0.reg);
+    SpiDrv_SetPrescaler(&tTcr,0x02);
+
+    SBC_SPI_INIT();
+    SBC_Init();
+
     /* get CAN controller default configuration */
     FlexCanDrv_GetDefaultCfg(&flexCanCfg);
     flexCanCfg.msgNum = sizeof(msgCfgObj) / sizeof(FlexCanDrv_MsgCfgType);
@@ -888,7 +900,20 @@ int main(void)
             gSystick1msEvent = 0;
             gSystick1msCnt++;
 
-            if(gSystick1msCnt >= 500)
+            if (gSystick1msCnt % 10 == 0)
+            {
+                SBC_WD_Trigger();
+            }
+            if (gSystick1msCnt % 1000 == 0)
+            {
+                uint16_t ret = SBC_Read_Command(SBC_WD_CTRL);
+                //SEGGER_RTT_printf(0,"%04d : SBC_WD_CTRL = %x\n",rollingcounter++,ret);
+                testdata[4] = 0x01;
+                testdata[5] = ret>>8;
+                testdata[6] = ret&0xff;
+                FlexCanBoot_TxMessage(UDS_TEXT_TX_MSG_ID,testdata,8);
+            }
+            if(gSystick1msCnt >= 5000)
             {
                 gSystick1msCnt = 0;
                 /* Test Io */