/*
 * Copyright (c) 2022, Shenzhen CVA Innovation CO.,LTD
 * All rights reserved.
 *
 * Shenzhen CVA Innovation CO.,LTD (CVA chip) is supplying this file for use
 * exclusively with CVA's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * CVA SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 */

#ifndef _PCC1_REG_H_
#define _PCC1_REG_H_

/*! \brief Contains public interface to various functions related
 *         to the PCC1 Registers
 */

/*******************************************************************************
 * the includes
 ******************************************************************************/

#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
 * the defines
 ******************************************************************************/

/* DMA Bit Fields */
#define PCC1_DMA_CKEN_MASK         (0x10u)
#define PCC1_DMA_CKEN_SHIFT        (4u)
#define PCC1_DMA_CKEN_WIDTH        (1u)
#define PCC1_DMA_SWR_MASK          (0x01u)
#define PCC1_DMA_SWR_SHIFT         (0u)
#define PCC1_DMA_SWR_WIDTH         (1u)

/* MSCM Bit Fields */
#define PCC1_MSCM_CKEN_MASK        (0x10u)
#define PCC1_MSCM_CKEN_SHIFT       (4u)
#define PCC1_MSCM_CKEN_WIDTH       (1u)
#define PCC1_MSCM_SWR_MASK         (0x01u)
#define PCC1_MSCM_SWR_SHIFT        (0u)
#define PCC1_MSCM_SWR_WIDTH        (1u)

/* CRC Bit Fields */
#define PCC1_CRC_CKEN_MASK         (0x10u)
#define PCC1_CRC_CKEN_SHIFT        (4u)
#define PCC1_CRC_CKEN_WIDTH        (1u)
#define PCC1_CRC_SWR_MASK          (0x01u)
#define PCC1_CRC_SWR_SHIFT         (0u)
#define PCC1_CRC_SWR_WIDTH         (1u)

/* EIM Bit Fields */
#define PCC1_EIM_CKEN_MASK         (0x10u)
#define PCC1_EIM_CKEN_SHIFT        (4u)
#define PCC1_EIM_CKEN_WIDTH        (1u)
#define PCC1_EIM_SWR_MASK          (0x01u)
#define PCC1_EIM_SWR_SHIFT         (0u)
#define PCC1_EIM_SWR_WIDTH         (1u)

/* ERM Bit Fields */
#define PCC1_ERM_CKEN_MASK         (0x10u)
#define PCC1_ERM_CKEN_SHIFT        (4u)
#define PCC1_ERM_CKEN_WIDTH        (1u)
#define PCC1_ERM_SWR_MASK          (0x01u)
#define PCC1_ERM_SWR_SHIFT         (0u)
#define PCC1_ERM_SWR_WIDTH         (1u)

/* FHU Bit Fields */
#define PCC1_FHU_CKEN_MASK         (0x10u)
#define PCC1_FHU_CKEN_SHIFT        (4u)
#define PCC1_FHU_CKEN_WIDTH        (1u)
#define PCC1_FHU_SWR_MASK          (0x01u)
#define PCC1_FHU_SWR_SHIFT         (0u)
#define PCC1_FHU_SWR_WIDTH         (1u)

/* SPI0 Bit Fields */
#define PCC1_SPI0_SRC_MASK         (0x30000u)
#define PCC1_SPI0_SRC_SHIFT        (16u)
#define PCC1_SPI0_SRC_WIDTH        (2u)
#define PCC1_SPI0_CKEN_MASK        (0x10u)
#define PCC1_SPI0_CKEN_SHIFT       (4u)
#define PCC1_SPI0_CKEN_WIDTH       (1u)
#define PCC1_SPI0_SWR_MASK         (0x01u)
#define PCC1_SPI0_SWR_SHIFT        (0u)
#define PCC1_SPI0_SWR_WIDTH        (1u)

/* SPI1 Bit Fields */
#define PCC1_SPI1_SRC_MASK         (0x30000u)
#define PCC1_SPI1_SRC_SHIFT        (16u)
#define PCC1_SPI1_SRC_WIDTH        (2u)
#define PCC1_SPI1_CKEN_MASK        (0x10u)
#define PCC1_SPI1_CKEN_SHIFT       (4u)
#define PCC1_SPI1_CKEN_WIDTH       (1u)
#define PCC1_SPI1_SWR_MASK         (0x01u)
#define PCC1_SPI1_SWR_SHIFT        (0u)
#define PCC1_SPI1_SWR_WIDTH        (1u)

/* UART0 Bit Fields */
#define PCC1_UART0_SRC_MASK        (0x30000u)
#define PCC1_UART0_SRC_SHIFT       (16u)
#define PCC1_UART0_SRC_WIDTH       (2u)
#define PCC1_UART0_CKEN_MASK       (0x10u)
#define PCC1_UART0_CKEN_SHIFT      (4u)
#define PCC1_UART0_CKEN_WIDTH      (1u)
#define PCC1_UART0_SWR_MASK        (0x01u)
#define PCC1_UART0_SWR_SHIFT       (0u)
#define PCC1_UART0_SWR_WIDTH       (1u)

/* UART1 Bit Fields */
#define PCC1_UART1_SRC_MASK        (0x30000u)
#define PCC1_UART1_SRC_SHIFT       (16u)
#define PCC1_UART1_SRC_WIDTH       (2u)
#define PCC1_UART1_CKEN_MASK       (0x10u)
#define PCC1_UART1_CKEN_SHIFT      (4u)
#define PCC1_UART1_CKEN_WIDTH      (1u)
#define PCC1_UART1_SWR_MASK        (0x01u)
#define PCC1_UART1_SWR_SHIFT       (0u)
#define PCC1_UART1_SWR_WIDTH       (1u)

/* CAN Bit Fields */
#define PCC1_CAN_CFG_CKEN_MASK     (0x20u)
#define PCC1_CAN_CFG_CKEN_SHIFT    (5u)
#define PCC1_CAN_CFG_CKEN_WIDTH    (1u)
#define PCC1_CAN_CKEN_MASK         (0x10u)
#define PCC1_CAN_CKEN_SHIFT        (4u)
#define PCC1_CAN_CKEN_WIDTH        (1u)
#define PCC1_CAN_SWR_MASK          (0x01u)
#define PCC1_CAN_SWR_SHIFT         (0u)
#define PCC1_CAN_SWR_WIDTH         (1u)

/* I2C Bit Fields */
#define PCC1_I2C_SRC_MASK          (0x30000u)
#define PCC1_I2C_SRC_SHIFT         (16u)
#define PCC1_I2C_SRC_WIDTH         (2u)
#define PCC1_I2C_CKEN_MASK         (0x10u)
#define PCC1_I2C_CKEN_SHIFT        (4u)
#define PCC1_I2C_CKEN_WIDTH        (1u)
#define PCC1_I2C_SWR_MASK          (0x01u)
#define PCC1_I2C_SWR_SHIFT         (0u)
#define PCC1_I2C_SWR_WIDTH         (1u)

/* PWM0 Bit Fields */
#define PCC1_PWM0_CKEN_MASK        (0x10u)
#define PCC1_PWM0_CKEN_SHIFT       (4u)
#define PCC1_PWM0_CKEN_WIDTH       (1u)
#define PCC1_PWM0_SWR_MASK         (0x01u)
#define PCC1_PWM0_SWR_SHIFT        (0u)
#define PCC1_PWM0_SWR_WIDTH        (1u)

/* PWM1 Bit Fields */
#define PCC1_PWM1_CKEN_MASK        (0x10u)
#define PCC1_PWM1_CKEN_SHIFT       (4u)
#define PCC1_PWM1_CKEN_WIDTH       (1u)
#define PCC1_PWM1_SWR_MASK         (0x01u)
#define PCC1_PWM1_SWR_SHIFT        (0u)
#define PCC1_PWM1_SWR_WIDTH        (1u)

/* MFT0 Bit Fields */
#define PCC1_MFT0_CKEN_MASK        (0x10u)
#define PCC1_MFT0_CKEN_SHIFT       (4u)
#define PCC1_MFT0_CKEN_WIDTH       (1u)
#define PCC1_MFT0_SWR_MASK         (0x01u)
#define PCC1_MFT0_SWR_SHIFT        (0u)
#define PCC1_MFT0_SWR_WIDTH        (1u)

/* MFT1 Bit Fields */
#define PCC1_MFT1_CKEN_MASK        (0x10u)
#define PCC1_MFT1_CKEN_SHIFT       (4u)
#define PCC1_MFT1_CKEN_WIDTH       (1u)
#define PCC1_MFT1_SWR_MASK         (0x01u)
#define PCC1_MFT1_SWR_SHIFT        (0u)
#define PCC1_MFT1_SWR_WIDTH        (1u)

/* GPIO Bit Fields */
#define PCC1_GPIO_SWR_MASK         (0x01u)
#define PCC1_GPIO_SWR_SHIFT        (0u)
#define PCC1_GPIO_SWR_WIDTH        (1u)

/* CMUS Bit Fields */
#define PCC1_CMUS_CKEN_MASK        (0x10u)
#define PCC1_CMUS_CKEN_SHIFT       (4u)
#define PCC1_CMUS_CKEN_WIDTH       (1u)
#define PCC1_CMUS_SWR_MASK         (0x01u)
#define PCC1_CMUS_SWR_SHIFT        (0u)
#define PCC1_CMUS_SWR_WIDTH        (1u)

/* CMUP Bit Fields */
#define PCC1_CMUP_CKEN_MASK        (0x10u)
#define PCC1_CMUP_CKEN_SHIFT       (4u)
#define PCC1_CMUP_CKEN_WIDTH       (1u)
#define PCC1_CMUP_SWR_MASK         (0x01u)
#define PCC1_CMUP_SWR_SHIFT        (0u)
#define PCC1_CMUP_SWR_WIDTH        (1u)

/* EXT_MFT0 Bit Fields */
#define PCC1_EXT_MFT0_SRC_MASK     (0x70000u)
#define PCC1_EXT_MFT0_SRC_SHIFT    (16u)
#define PCC1_EXT_MFT0_SRC_WIDTH    (3u)

/* EXT_MFT1 Bit Fields */
#define PCC1_EXT_MFT1_SRC_MASK     (0x70000u)
#define PCC1_EXT_MFT1_SRC_SHIFT    (16u)
#define PCC1_EXT_MFT1_SRC_WIDTH    (3u)

/* FIX_MFT0 Bit Fields */
#define PCC1_FIX_MFT0_SRC_MASK     (0x10000u)
#define PCC1_FIX_MFT0_SRC_SHIFT    (16u)
#define PCC1_FIX_MFT0_SRC_WIDTH    (1u)

/* FIX_MFT1 Bit Fields */
#define PCC1_FIX_MFT1_SRC_MASK     (0x10000u)
#define PCC1_FIX_MFT1_SRC_SHIFT    (16u)
#define PCC1_FIX_MFT1_SRC_WIDTH    (1u)

/* FLS_CTL Bit Fields */
#define PCC1_FLS_CTL_CNT_DIV_MASK  (0xF00u)
#define PCC1_FLS_CTL_CNT_DIV_SHIFT (8u)
#define PCC1_FLS_CTL_CNT_DIV_WIDTH (4u)
#define PCC1_FLS_CTL_CKEN_MASK     (0x10u)
#define PCC1_FLS_CTL_CKEN_SHIFT    (4u)
#define PCC1_FLS_CTL_CKEN_WIDTH    (1u)
#define PCC1_FLS_CTL_SWR_MASK      (0x01u)
#define PCC1_FLS_CTL_SWR_SHIFT     (0u)
#define PCC1_FLS_CTL_SWR_WIDTH     (1u)

/* MPU Bit Fields */
#define PCC1_MPU_CKEN_MASK         (0x10u)
#define PCC1_MPU_CKEN_SHIFT        (4u)
#define PCC1_MPU_CKEN_WIDTH        (1u)
#define PCC1_MPU_SWR_MASK          (0x01u)
#define PCC1_MPU_SWR_SHIFT         (0u)
#define PCC1_MPU_SWR_WIDTH         (1u)

/*******************************************************************************
 * the typedefs
 ******************************************************************************/

/*! \brief The definition of PCC1 registers
 */
typedef struct _Pcc1RegType_
{
    volatile uint32_t DMA;          /*!< DMA clock and software reset control register, offset: 0x0 */
    volatile uint32_t MSCM;         /*!< MSCM clock and software reset control register, offset: 0x4 */
    uint32_t          RESERVED0[2]; /*!< Reserved register, offset: 0x8 */
    volatile uint32_t CRC;          /*!< CRC clock and software reset control register, offset: 0x10 */
    volatile uint32_t EIM;          /*!< EIM clock and software reset control register, offset: 0x14 */
    volatile uint32_t ERM;          /*!< ERM clock and software reset control register, offset: 0x18 */
    volatile uint32_t FHU;          /*!< FHU clock and software reset control register, offset: 0x1C */
    uint32_t          RESERVED1[4]; /*!< Reserved register, offset: 0x20 */
    volatile uint32_t SPI0;         /*!< SPI0 clock and software reset control register, offset: 0x30 */
    volatile uint32_t SPI1;         /*!< SPI1 clock and software reset control register, offset: 0x34 */
    uint32_t          RESERVED2[2]; /*!< Reserved register, offset: 0x38 */
    volatile uint32_t UART0;        /*!< UART0 clock and software reset control register, offset: 0x40 */
    volatile uint32_t UART1;        /*!< UART1 clock and software reset control register, offset: 0x44 */
    uint32_t          RESERVED3[2]; /*!< Reserved register, offset: 0x48 */
    volatile uint32_t CAN;          /*!< CAN clock and software reset control register, offset: 0x50 */
    uint32_t          RESERVED4[3]; /*!< Reserved register, offset: 0x54 */
    volatile uint32_t I2C;          /*!< I2C clock and software reset control register, offset: 0x60 */
    uint32_t          RESERVED5[2]; /*!< Reserved register, offset: 0x64 */
    volatile uint32_t PWM0;         /*!< PWM0 clock and software reset control register, offset: 0x6C */
    volatile uint32_t PWM1;         /*!< PWM1 clock and software reset control register, offset: 0x70 */
    uint32_t          RESERVED6[3]; /*!< Reserved register, offset: 0x74 */
    volatile uint32_t MFT0;         /*!< MFT0 clock and software reset control register, offset: 0x80 */
    volatile uint32_t MFT1;         /*!< MFT1 clock and software reset control register, offset: 0x84 */
    uint32_t          RESERVED7[2]; /*!< Reserved register, offset: 0x88 */
    volatile uint32_t GPIO;         /*!< GPIO clock and software reset control register, offset: 0x90 */
    volatile uint32_t CMUS;         /*!< CMUS clock and software reset control register, offset: 0x94 */
    uint32_t          RESERVED8[1]; /*!< Reserved register, offset: 0x98 */
    volatile uint32_t CMUP;         /*!< CMUP clock and software reset control register, offset: 0x9C */
    volatile uint32_t EXT_MFT0;     /*!< MFT0 external clock and software reset control register, offset: 0xA0 */
    volatile uint32_t EXT_MFT1;     /*!< MFT1 external clock and software reset control register, offset: 0xA4 */
    uint32_t          RESERVED9[6]; /*!< Reserved register, offset: 0xA8 */
    volatile uint32_t FIX_MFT0;     /*!< MFT0 fix clock and software reset control register, offset: 0xC0 */
    volatile uint32_t FIX_MFT1;     /*!< MFT1 fix clock and software reset control register, offset: 0xC4 */
    volatile uint32_t FLS_CTL;      /*!< CMUP clock and software reset control register, offset: 0xC8 */
    volatile uint32_t MPU;          /*!< MPU clock and software reset control register, offset: 0xCC */
} Pcc1RegType;

/*******************************************************************************
 * the globals
 ******************************************************************************/

/*******************************************************************************
 * the function prototypes
 ******************************************************************************/

/*! \brief Gets the DMA clock enable
 *
 * This function gets the current DMA clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return DMA clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetDmaCkEn(const Pcc1RegType *obj)
{
    return ((obj->DMA & PCC1_DMA_CKEN_MASK) >> PCC1_DMA_CKEN_SHIFT);
}

/*! \brief Sets the DMA clock enable
 *
 * This function sets the DMA clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of DMA clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetDmaCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->DMA;

    tmp &= ~PCC1_DMA_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_DMA_CKEN_SHIFT)) & PCC1_DMA_CKEN_MASK);
    obj->DMA = tmp;
}

/*! \brief Gets the DMA software reset
 *
 * This function gets the current DMA software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return DMA software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetDmaSwR(const Pcc1RegType *obj)
{
    return ((obj->DMA & PCC1_DMA_SWR_MASK) >> PCC1_DMA_SWR_SHIFT);
}

/*! \brief Sets the DMA software reset
 *
 * This function sets the DMA software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of DMA software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetDmaSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->DMA;

    tmp &= ~PCC1_DMA_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_DMA_SWR_SHIFT)) & PCC1_DMA_SWR_MASK);
    obj->DMA = tmp;
}

/*! \brief Gets the MSCM clock enable
 *
 * This function gets the current MSCM clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return MSCM clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetMscmCkEn(const Pcc1RegType *obj)
{
    return ((obj->MSCM & PCC1_MSCM_CKEN_MASK) >> PCC1_MSCM_CKEN_SHIFT);
}

/*! \brief Sets the MSCM clock enable
 *
 * This function sets the MSCM clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of MSCM clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetMscmCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MSCM;

    tmp &= ~PCC1_MSCM_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_MSCM_CKEN_SHIFT)) & PCC1_MSCM_CKEN_MASK);
    obj->MSCM = tmp;
}

/*! \brief Gets the MSCM software reset
 *
 * This function gets the current MSCM software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return MSCM software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetMscmSwR(const Pcc1RegType *obj)
{
    return ((obj->MSCM & PCC1_MSCM_SWR_MASK) >> PCC1_MSCM_SWR_SHIFT);
}

/*! \brief Sets the MSCM software reset
 *
 * This function sets the MSCM software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of MSCM software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetMscmSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MSCM;

    tmp &= ~PCC1_MSCM_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_MSCM_SWR_SHIFT)) & PCC1_MSCM_SWR_MASK);
    obj->MSCM = tmp;
}

/*! \brief Gets the CRC clock enable
 *
 * This function gets the current CRC clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return CRC clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetCrcCkEn(const Pcc1RegType *obj)
{
    return ((obj->CRC & PCC1_CRC_CKEN_MASK) >> PCC1_CRC_CKEN_SHIFT);
}

/*! \brief Sets the CRC clock enable
 *
 * This function sets the CRC clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of CRC clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetCrcCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CRC;

    tmp &= ~PCC1_CRC_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_CRC_CKEN_SHIFT)) & PCC1_CRC_CKEN_MASK);
    obj->CRC = tmp;
}

/*! \brief Gets the CRC software reset
 *
 * This function gets the current CRC software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return CRC software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetCrcSwR(const Pcc1RegType *obj)
{
    return ((obj->CRC & PCC1_CRC_SWR_MASK) >> PCC1_CRC_SWR_SHIFT);
}

/*! \brief Sets the CRC software reset
 *
 * This function sets the CRC software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of CRC software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetCrcSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CRC;

    tmp &= ~PCC1_CRC_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_CRC_SWR_SHIFT)) & PCC1_CRC_SWR_MASK);
    obj->CRC = tmp;
}

/*! \brief Gets the EIM clock enable
 *
 * This function gets the current EIM clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return EIM clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetEimCkEn(const Pcc1RegType *obj)
{
    return ((obj->EIM & PCC1_EIM_CKEN_MASK) >> PCC1_EIM_CKEN_SHIFT);
}

/*! \brief Sets the EIM clock enable
 *
 * This function sets the EIM clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of EIM clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetEimCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->EIM;

    tmp &= ~PCC1_EIM_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_EIM_CKEN_SHIFT)) & PCC1_EIM_CKEN_MASK);
    obj->EIM = tmp;
}

/*! \brief Gets the EIM software reset
 *
 * This function gets the current EIM software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return EIM software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetEimSwR(const Pcc1RegType *obj)
{
    return ((obj->EIM & PCC1_EIM_SWR_MASK) >> PCC1_EIM_SWR_SHIFT);
}

/*! \brief Sets the EIM software reset
 *
 * This function sets the EIM software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of EIM software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetEimSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->EIM;

    tmp &= ~PCC1_EIM_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_EIM_SWR_SHIFT)) & PCC1_EIM_SWR_MASK);
    obj->EIM = tmp;
}

/*! \brief Gets the ERM clock enable
 *
 * This function gets the current ERM clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return ERM clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetErmCkEn(const Pcc1RegType *obj)
{
    return ((obj->ERM & PCC1_ERM_CKEN_MASK) >> PCC1_ERM_CKEN_SHIFT);
}

/*! \brief Sets the ERM clock enable
 *
 * This function sets the ERM clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of ERM clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetErmCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ERM;

    tmp &= ~PCC1_ERM_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_ERM_CKEN_SHIFT)) & PCC1_ERM_CKEN_MASK);
    obj->ERM = tmp;
}

/*! \brief Gets the ERM software reset
 *
 * This function gets the current ERM software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return ERM software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetErmSwR(const Pcc1RegType *obj)
{
    return ((obj->ERM & PCC1_ERM_SWR_MASK) >> PCC1_ERM_SWR_SHIFT);
}

/*! \brief Sets the ERM software reset
 *
 * This function sets the ERM software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of ERM software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetErmSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ERM;

    tmp &= ~PCC1_ERM_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_ERM_SWR_SHIFT)) & PCC1_ERM_SWR_MASK);
    obj->ERM = tmp;
}

/*! \brief Gets the FHU clock enable
 *
 * This function gets the current FHU clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return FHU clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetFhuCkEn(const Pcc1RegType *obj)
{
    return ((obj->FHU & PCC1_FHU_CKEN_MASK) >> PCC1_FHU_CKEN_SHIFT);
}

/*! \brief Sets the FHU clock enable
 *
 * This function sets the FHU clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of FHU clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetFhuCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->FHU;

    tmp &= ~PCC1_FHU_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_FHU_CKEN_SHIFT)) & PCC1_FHU_CKEN_MASK);
    obj->FHU = tmp;
}

/*! \brief Gets the FHU software reset
 *
 * This function gets the current FHU software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return FHU software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetFhuSwR(const Pcc1RegType *obj)
{
    return ((obj->FHU & PCC1_FHU_SWR_MASK) >> PCC1_FHU_SWR_SHIFT);
}

/*! \brief Sets the FHU software reset
 *
 * This function sets the FHU software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of FHU software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetFhuSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->FHU;

    tmp &= ~PCC1_FHU_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_FHU_SWR_SHIFT)) & PCC1_FHU_SWR_MASK);
    obj->FHU = tmp;
}

/*! \brief Gets the SPI0 module function clock source
 *
 * This function gets the current SPI0 module function clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return SPI0 module function clock source
 *         - 0h : clk_sirc_div
 *         - 1h : clk_sosc_div
 *         - 2h : clk_pll_div
 *         - 3h : clk_sirc_div
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetSpi0Src(const Pcc1RegType *obj)
{
    return ((obj->SPI0 & PCC1_SPI0_SRC_MASK) >> PCC1_SPI0_SRC_SHIFT);
}

/*! \brief Sets the SPI0 module function clock source
 *
 * This function sets the SPI0 module function clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of SPI0 module function clock source
 *                    - 0h : clk_sirc_div
 *                    - 1h : clk_sosc_div
 *                    - 2h : clk_pll_div
 *                    - 3h : clk_sirc_div
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetSpi0Src(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SPI0;

    tmp &= ~PCC1_SPI0_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_SPI0_SRC_SHIFT)) & PCC1_SPI0_SRC_MASK);
    obj->SPI0 = tmp;
}

/*! \brief Gets the SPI0 clock enable
 *
 * This function gets the current SPI0 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return SPI0 clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetSpi0CkEn(const Pcc1RegType *obj)
{
    return ((obj->SPI0 & PCC1_SPI0_CKEN_MASK) >> PCC1_SPI0_CKEN_SHIFT);
}

/*! \brief Sets the SPI0 clock enable
 *
 * This function sets the SPI0 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of SPI0 clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetSpi0CkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SPI0;

    tmp &= ~PCC1_SPI0_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_SPI0_CKEN_SHIFT)) & PCC1_SPI0_CKEN_MASK);
    obj->SPI0 = tmp;
}

/*! \brief Gets the SPI0 software reset
 *
 * This function gets the current SPI0 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return SPI0 software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetSpi0SwR(const Pcc1RegType *obj)
{
    return ((obj->SPI0 & PCC1_SPI0_SWR_MASK) >> PCC1_SPI0_SWR_SHIFT);
}

/*! \brief Sets the SPI0 software reset
 *
 * This function sets the SPI0 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of SPI0 software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetSpi0SwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SPI0;

    tmp &= ~PCC1_SPI0_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_SPI0_SWR_SHIFT)) & PCC1_SPI0_SWR_MASK);
    obj->SPI0 = tmp;
}

/*! \brief Gets the SPI1 module function clock source
 *
 * This function gets the current SPI1 module function clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return SPI1 module function clock source
 *         - 0h : clk_sirc_div
 *         - 1h : clk_sosc_div
 *         - 2h : clk_pll_div
 *         - 3h : clk_sirc_div
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetSpi1Src(const Pcc1RegType *obj)
{
    return ((obj->SPI1 & PCC1_SPI1_SRC_MASK) >> PCC1_SPI1_SRC_SHIFT);
}

/*! \brief Sets the SPI1 module function clock source
 *
 * This function sets the SPI1 module function clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of SPI1 module function clock source
 *                    - 0h : clk_sirc_div
 *                    - 1h : clk_sosc_div
 *                    - 2h : clk_pll_div
 *                    - 3h : clk_sirc_div
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetSpi1Src(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SPI1;

    tmp &= ~PCC1_SPI1_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_SPI1_SRC_SHIFT)) & PCC1_SPI1_SRC_MASK);
    obj->SPI1 = tmp;
}

/*! \brief Gets the SPI1 clock enable
 *
 * This function gets the current SPI1 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return SPI1 clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetSpi1CkEn(const Pcc1RegType *obj)
{
    return ((obj->SPI1 & PCC1_SPI1_CKEN_MASK) >> PCC1_SPI1_CKEN_SHIFT);
}

/*! \brief Sets the SPI1 clock enable
 *
 * This function sets the SPI1 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of SPI1 clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetSpi1CkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SPI1;

    tmp &= ~PCC1_SPI1_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_SPI1_CKEN_SHIFT)) & PCC1_SPI1_CKEN_MASK);
    obj->SPI1 = tmp;
}

/*! \brief Gets the SPI1 software reset
 *
 * This function gets the current SPI1 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return SPI1 software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetSpi1SwR(const Pcc1RegType *obj)
{
    return ((obj->SPI1 & PCC1_SPI1_SWR_MASK) >> PCC1_SPI1_SWR_SHIFT);
}

/*! \brief Sets the SPI1 software reset
 *
 * This function sets the SPI1 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of SPI1 software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetSpi1SwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SPI1;

    tmp &= ~PCC1_SPI1_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_SPI1_SWR_SHIFT)) & PCC1_SPI1_SWR_MASK);
    obj->SPI1 = tmp;
}

/*! \brief Gets the UART0 module function clock source
 *
 * This function gets the current UART0 module function clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return UART0 module function clock source
 *         - 0h : clk_sirc_div
 *         - 1h : clk_sosc_div
 *         - 2h : clk_pll_div
 *         - 3h : clk_sirc_div
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetUart0Src(const Pcc1RegType *obj)
{
    return ((obj->UART0 & PCC1_UART0_SRC_MASK) >> PCC1_UART0_SRC_SHIFT);
}

/*! \brief Sets the UART0 module function clock source
 *
 * This function sets the UART0 module function clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of UART0 module function clock source
 *                    - 0h : clk_sirc_div
 *                    - 1h : clk_sosc_div
 *                    - 2h : clk_pll_div
 *                    - 3h : clk_sirc_div
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetUart0Src(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->UART0;

    tmp &= ~PCC1_UART0_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_UART0_SRC_SHIFT)) & PCC1_UART0_SRC_MASK);
    obj->UART0 = tmp;
}

/*! \brief Gets the UART0 clock enable
 *
 * This function gets the current UART0 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return UART0 clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetUart0CkEn(const Pcc1RegType *obj)
{
    return ((obj->UART0 & PCC1_UART0_CKEN_MASK) >> PCC1_UART0_CKEN_SHIFT);
}

/*! \brief Sets the UART0 clock enable
 *
 * This function sets the UART0 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of UART0 clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetUart0CkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->UART0;

    tmp &= ~PCC1_UART0_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_UART0_CKEN_SHIFT)) & PCC1_UART0_CKEN_MASK);
    obj->UART0 = tmp;
}

/*! \brief Gets the UART0 software reset
 *
 * This function gets the current UART0 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return UART0 software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetUart0SwR(const Pcc1RegType *obj)
{
    return ((obj->UART0 & PCC1_UART0_SWR_MASK) >> PCC1_UART0_SWR_SHIFT);
}

/*! \brief Sets the UART0 software reset
 *
 * This function sets the UART0 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of UART0 software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetUart0SwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->UART0;

    tmp &= ~PCC1_UART0_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_UART0_SWR_SHIFT)) & PCC1_UART0_SWR_MASK);
    obj->UART0 = tmp;
}

/*! \brief Gets the UART1 module function clock source
 *
 * This function gets the current UART1 module function clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return UART1 module function clock source
 *         - 0h : clk_sirc_div
 *         - 1h : clk_sosc_div
 *         - 2h : clk_pll_div
 *         - 3h : clk_sirc_div
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetUart1Src(const Pcc1RegType *obj)
{
    return ((obj->UART1 & PCC1_UART1_SRC_MASK) >> PCC1_UART1_SRC_SHIFT);
}

/*! \brief Sets the UART1 module function clock source
 *
 * This function sets the UART1 module function clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of UART1 module function clock source
 *                    - 0h : clk_sirc_div
 *                    - 1h : clk_sosc_div
 *                    - 2h : clk_pll_div
 *                    - 3h : clk_sirc_div
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetUart1Src(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->UART1;

    tmp &= ~PCC1_UART1_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_UART1_SRC_SHIFT)) & PCC1_UART1_SRC_MASK);
    obj->UART1 = tmp;
}

/*! \brief Gets the UART1 clock enable
 *
 * This function gets the current UART1 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return UART1 clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetUart1CkEn(const Pcc1RegType *obj)
{
    return ((obj->UART1 & PCC1_UART1_CKEN_MASK) >> PCC1_UART1_CKEN_SHIFT);
}

/*! \brief Sets the UART1 clock enable
 *
 * This function sets the UART1 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of UART1 clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetUart1CkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->UART1;

    tmp &= ~PCC1_UART1_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_UART1_CKEN_SHIFT)) & PCC1_UART1_CKEN_MASK);
    obj->UART1 = tmp;
}

/*! \brief Gets the UART1 software reset
 *
 * This function gets the current UART1 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return UART1 software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetUart1SwR(const Pcc1RegType *obj)
{
    return ((obj->UART1 & PCC1_UART1_SWR_MASK) >> PCC1_UART1_SWR_SHIFT);
}

/*! \brief Sets the UART1 software reset
 *
 * This function sets the UART1 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of UART1 software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetUart1SwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->UART1;

    tmp &= ~PCC1_UART1_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_UART1_SWR_SHIFT)) & PCC1_UART1_SWR_MASK);
    obj->UART1 = tmp;
}

/*! \brief Gets the CAN configure clock enable
 *
 * This function gets the current CAN configure clock enable.
 * It works for both function clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return CAN configure clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetCanCfgCkEn(const Pcc1RegType *obj)
{
    return ((obj->CAN & PCC1_CAN_CFG_CKEN_MASK) >> PCC1_CAN_CFG_CKEN_SHIFT);
}

/*! \brief Sets the CAN configure clock enable
 *
 * This function sets the CAN configure clock enable.
 * It works for both function clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of CAN configure clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetCanCfgCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CAN;

    tmp &= ~PCC1_CAN_CFG_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_CAN_CFG_CKEN_SHIFT)) & PCC1_CAN_CFG_CKEN_MASK);
    obj->CAN = tmp;
}

/*! \brief Gets the CAN work clock enable
 *
 * This function gets the current CAN work clock enable.
 * It works for both function clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return CAN work clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetCanCkEn(const Pcc1RegType *obj)
{
    return ((obj->CAN & PCC1_CAN_CKEN_MASK) >> PCC1_CAN_CKEN_SHIFT);
}

/*! \brief Sets the CAN work clock enable
 *
 * This function sets the CAN work clock enable.
 * It works for both function clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of CAN work clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetCanCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CAN;

    tmp &= ~PCC1_CAN_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_CAN_CKEN_SHIFT)) & PCC1_CAN_CKEN_MASK);
    obj->CAN = tmp;
}

/*! \brief Gets the CAN software reset
 *
 * This function gets the current CAN software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return CAN software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetCanSwR(const Pcc1RegType *obj)
{
    return ((obj->CAN & PCC1_CAN_SWR_MASK) >> PCC1_CAN_SWR_SHIFT);
}

/*! \brief Sets the CAN software reset
 *
 * This function sets the CAN software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of CAN software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetCanSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CAN;

    tmp &= ~PCC1_CAN_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_CAN_SWR_SHIFT)) & PCC1_CAN_SWR_MASK);
    obj->CAN = tmp;
}

/*! \brief Gets the I2C module function clock source
 *
 * This function gets the current I2C module function clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return I2C module function clock source
 *         - 0h : clk_sirc_div
 *         - 1h : clk_sosc_div
 *         - 2h : clk_pll_div
 *         - 3h : clk_sirc_div
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetI2CSrc(const Pcc1RegType *obj)
{
    return ((obj->I2C & PCC1_I2C_SRC_MASK) >> PCC1_I2C_SRC_SHIFT);
}

/*! \brief Sets the I2C module function clock source
 *
 * This function sets the I2C module function clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of I2C module function clock source
 *                    - 0h : clk_sirc_div
 *                    - 1h : clk_sosc_div
 *                    - 2h : clk_pll_div
 *                    - 3h : clk_sirc_div
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetI2CSrc(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->I2C;

    tmp &= ~PCC1_I2C_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_I2C_SRC_SHIFT)) & PCC1_I2C_SRC_MASK);
    obj->I2C = tmp;
}

/*! \brief Gets the I2C clock enable
 *
 * This function gets the current I2C clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return I2C clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetI2CCkEn(const Pcc1RegType *obj)
{
    return ((obj->I2C & PCC1_I2C_CKEN_MASK) >> PCC1_I2C_CKEN_SHIFT);
}

/*! \brief Sets the I2C clock enable
 *
 * This function sets the I2C clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of I2C clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetI2CCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->I2C;

    tmp &= ~PCC1_I2C_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_I2C_CKEN_SHIFT)) & PCC1_I2C_CKEN_MASK);
    obj->I2C = tmp;
}

/*! \brief Gets the I2C software reset
 *
 * This function gets the current I2C software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return I2C software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetI2CSwR(const Pcc1RegType *obj)
{
    return ((obj->I2C & PCC1_I2C_SWR_MASK) >> PCC1_I2C_SWR_SHIFT);
}

/*! \brief Sets the I2C software reset
 *
 * This function sets the I2C software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of I2C software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetI2CSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->I2C;

    tmp &= ~PCC1_I2C_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_I2C_SWR_SHIFT)) & PCC1_I2C_SWR_MASK);
    obj->I2C = tmp;
}

/*! \brief Gets the PWM0 clock enable
 *
 * This function gets the current PWM0 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return PWM0 clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetPwm0CkEn(const Pcc1RegType *obj)
{
    return ((obj->PWM0 & PCC1_PWM0_CKEN_MASK) >> PCC1_PWM0_CKEN_SHIFT);
}

/*! \brief Sets the PWM0 clock enable
 *
 * This function sets the PWM0 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of PWM0 clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetPwm0CkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PWM0;

    tmp &= ~PCC1_PWM0_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_PWM0_CKEN_SHIFT)) & PCC1_PWM0_CKEN_MASK);
    obj->PWM0 = tmp;
}

/*! \brief Gets the PWM0 software reset
 *
 * This function gets the current PWM0 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return PWM0 software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetPwm0SwR(const Pcc1RegType *obj)
{
    return ((obj->PWM0 & PCC1_PWM0_SWR_MASK) >> PCC1_PWM0_SWR_SHIFT);
}

/*! \brief Sets the PWM0 software reset
 *
 * This function sets the PWM0 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of PWM0 software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetPwm0SwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PWM0;

    tmp &= ~PCC1_PWM0_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_PWM0_SWR_SHIFT)) & PCC1_PWM0_SWR_MASK);
    obj->PWM0 = tmp;
}

/*! \brief Gets the PWM1 clock enable
 *
 * This function gets the current PWM1 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return PWM1 clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetPwm1CkEn(const Pcc1RegType *obj)
{
    return ((obj->PWM1 & PCC1_PWM1_CKEN_MASK) >> PCC1_PWM1_CKEN_SHIFT);
}

/*! \brief Sets the PWM1 clock enable
 *
 * This function sets the PWM1 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of PWM1 clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetPwm1CkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PWM1;

    tmp &= ~PCC1_PWM1_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_PWM1_CKEN_SHIFT)) & PCC1_PWM1_CKEN_MASK);
    obj->PWM1 = tmp;
}

/*! \brief Gets the PWM1 software reset
 *
 * This function gets the current PWM1 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return PWM1 software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetPwm1SwR(const Pcc1RegType *obj)
{
    return ((obj->PWM1 & PCC1_PWM1_SWR_MASK) >> PCC1_PWM1_SWR_SHIFT);
}

/*! \brief Sets the PWM1 software reset
 *
 * This function sets the PWM1 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of PWM1 software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetPwm1SwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->PWM1;

    tmp &= ~PCC1_PWM1_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_PWM1_SWR_SHIFT)) & PCC1_PWM1_SWR_MASK);
    obj->PWM1 = tmp;
}

/*! \brief Gets the MFT0 clock enable
 *
 * This function gets the current MFT0 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return MFT0 clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetMft0CkEn(const Pcc1RegType *obj)
{
    return ((obj->MFT0 & PCC1_MFT0_CKEN_MASK) >> PCC1_MFT0_CKEN_SHIFT);
}

/*! \brief Sets the MFT0 clock enable
 *
 * This function sets the MFT0 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of MFT0 clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetMft0CkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MFT0;

    tmp &= ~PCC1_MFT0_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_MFT0_CKEN_SHIFT)) & PCC1_MFT0_CKEN_MASK);
    obj->MFT0 = tmp;
}

/*! \brief Gets the MFT0 software reset
 *
 * This function gets the current MFT0 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return MFT0 software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetMft0SwR(const Pcc1RegType *obj)
{
    return ((obj->MFT0 & PCC1_MFT0_SWR_MASK) >> PCC1_MFT0_SWR_SHIFT);
}

/*! \brief Sets the MFT0 software reset
 *
 * This function sets the MFT0 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of MFT0 software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetMft0SwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MFT0;

    tmp &= ~PCC1_MFT0_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_MFT0_SWR_SHIFT)) & PCC1_MFT0_SWR_MASK);
    obj->MFT0 = tmp;
}

/*! \brief Gets the MFT1 clock enable
 *
 * This function gets the current MFT1 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return MFT1 clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetMft1CkEn(const Pcc1RegType *obj)
{
    return ((obj->MFT1 & PCC1_MFT1_CKEN_MASK) >> PCC1_MFT1_CKEN_SHIFT);
}

/*! \brief Sets the MFT1 clock enable
 *
 * This function sets the MFT1 clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of MFT1 clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetMft1CkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MFT1;

    tmp &= ~PCC1_MFT1_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_MFT1_CKEN_SHIFT)) & PCC1_MFT1_CKEN_MASK);
    obj->MFT1 = tmp;
}

/*! \brief Gets the MFT1 software reset
 *
 * This function gets the current MFT1 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return MFT1 software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetMft1SwR(const Pcc1RegType *obj)
{
    return ((obj->MFT1 & PCC1_MFT1_SWR_MASK) >> PCC1_MFT1_SWR_SHIFT);
}

/*! \brief Sets the MFT1 software reset
 *
 * This function sets the MFT1 software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of MFT1 software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetMft1SwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MFT1;

    tmp &= ~PCC1_MFT1_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_MFT1_SWR_SHIFT)) & PCC1_MFT1_SWR_MASK);
    obj->MFT1 = tmp;
}

/*! \brief Gets the GPIO software reset
 *
 * This function gets the current GPIO software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return GPIO software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetGpioSwR(const Pcc1RegType *obj)
{
    return ((obj->GPIO & PCC1_GPIO_SWR_MASK) >> PCC1_GPIO_SWR_SHIFT);
}

/*! \brief Sets the GPIO software reset
 *
 * This function sets the GPIO software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of GPIO software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetGpioSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->GPIO;

    tmp &= ~PCC1_GPIO_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_GPIO_SWR_SHIFT)) & PCC1_GPIO_SWR_MASK);
    obj->GPIO = tmp;
}

/*! \brief Gets the CMUS clock enable
 *
 * This function gets the current CMUS clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return CMUS clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetCmusCkEn(const Pcc1RegType *obj)
{
    return ((obj->CMUS & PCC1_CMUS_CKEN_MASK) >> PCC1_CMUS_CKEN_SHIFT);
}

/*! \brief Sets the CMUS clock enable
 *
 * This function sets the CMUS clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of CMUS clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetCmusCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CMUS;

    tmp &= ~PCC1_CMUS_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_CMUS_CKEN_SHIFT)) & PCC1_CMUS_CKEN_MASK);
    obj->CMUS = tmp;
}

/*! \brief Gets the CMUS software reset
 *
 * This function gets the current CMUS software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return CMUS software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetCmusSwR(const Pcc1RegType *obj)
{
    return ((obj->CMUS & PCC1_CMUS_SWR_MASK) >> PCC1_CMUS_SWR_SHIFT);
}

/*! \brief Sets the CMUS software reset
 *
 * This function sets the CMUS software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of CMUS software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetCmusSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CMUS;

    tmp &= ~PCC1_CMUS_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_CMUS_SWR_SHIFT)) & PCC1_CMUS_SWR_MASK);
    obj->CMUS = tmp;
}

/*! \brief Gets the CMUP clock enable
 *
 * This function gets the current CMUP clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return CMUP clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetCmupCkEn(const Pcc1RegType *obj)
{
    return ((obj->CMUP & PCC1_CMUP_CKEN_MASK) >> PCC1_CMUP_CKEN_SHIFT);
}

/*! \brief Sets the CMUP clock enable
 *
 * This function sets the CMUP clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of CMUP clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetCmupCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CMUP;

    tmp &= ~PCC1_CMUP_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_CMUP_CKEN_SHIFT)) & PCC1_CMUP_CKEN_MASK);
    obj->CMUP = tmp;
}

/*! \brief Gets the CMUP software reset
 *
 * This function gets the current CMUP software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return CMUP software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetCmupSwR(const Pcc1RegType *obj)
{
    return ((obj->CMUP & PCC1_CMUP_SWR_MASK) >> PCC1_CMUP_SWR_SHIFT);
}

/*! \brief Sets the CMUP software reset
 *
 * This function sets the CMUP software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of CMUP software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetCmupSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->CMUP;

    tmp &= ~PCC1_CMUP_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_CMUP_SWR_SHIFT)) & PCC1_CMUP_SWR_MASK);
    obj->CMUP = tmp;
}

/*! \brief Gets the MFT0 external clock source
 *
 * This function gets the current MFT0 external clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return MFT0 external clock source
 *         - 0h : TCLK0
 *         - 1h : TCLK1
 *         - 2h : TCLK2
 *         - 3h : clk_sirc_div_mft
 *         - 4h : clk_sosc_div_mft
 *         - 5h : clk_pll_div_mft
 *         - 6h : clk_sirc_div_mft
 *         - 7h : clk_sirc_div_mft
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetExtMft0Src(const Pcc1RegType *obj)
{
    return ((obj->EXT_MFT0 & PCC1_EXT_MFT0_SRC_MASK) >> PCC1_EXT_MFT0_SRC_SHIFT);
}

/*! \brief Sets the MFT0 external clock source
 *
 * This function sets the MFT0 external clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of MFT0 external clock source
 *                    - 0h : TCLK0
 *                    - 1h : TCLK1
 *                    - 2h : TCLK2
 *                    - 3h : clk_sirc_div_mft
 *                    - 4h : clk_sosc_div_mft
 *                    - 5h : clk_pll_div_mft
 *                    - 6h : clk_sirc_div_mft
 *                    - 7h : clk_sirc_div_mft
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetExtMft0Src(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->EXT_MFT0;

    tmp &= ~PCC1_EXT_MFT0_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_EXT_MFT0_SRC_SHIFT)) & PCC1_EXT_MFT0_SRC_MASK);
    obj->EXT_MFT0 = tmp;
}

/*! \brief Gets the MFT1 external clock source
 *
 * This function gets the current MFT1 external clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return MFT1 external clock source
 *         - 0h : TCLK0
 *         - 1h : TCLK1
 *         - 2h : TCLK2
 *         - 3h : clk_sirc_div_mft
 *         - 4h : clk_sosc_div_mft
 *         - 5h : clk_pll_div_mft
 *         - 6h : clk_sirc_div_mft
 *         - 7h : clk_sirc_div_mft
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetExtMft1Src(const Pcc1RegType *obj)
{
    return ((obj->EXT_MFT1 & PCC1_EXT_MFT1_SRC_MASK) >> PCC1_EXT_MFT1_SRC_SHIFT);
}

/*! \brief Sets the MFT1 external clock source
 *
 * This function sets the MFT1 external clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of MFT1 external clock source
 *                    - 0h : TCLK0
 *                    - 1h : TCLK1
 *                    - 2h : TCLK2
 *                    - 3h : clk_sirc_div_mft
 *                    - 4h : clk_sosc_div_mft
 *                    - 5h : clk_pll_div_mft
 *                    - 6h : clk_sirc_div_mft
 *                    - 7h : clk_sirc_div_mft
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetExtMft1Src(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->EXT_MFT1;

    tmp &= ~PCC1_EXT_MFT1_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_EXT_MFT1_SRC_SHIFT)) & PCC1_EXT_MFT1_SRC_MASK);
    obj->EXT_MFT1 = tmp;
}

/*! \brief Gets the MFT0 fix clock source
 *
 * This function gets the current MFT0 fix clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return MFT0 fix clock source
 *         - 0b : clk_lpo32
 *         - 1b : RTC_CLKIN
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetFixMft0Src(const Pcc1RegType *obj)
{
    return ((obj->FIX_MFT0 & PCC1_FIX_MFT0_SRC_MASK) >> PCC1_FIX_MFT0_SRC_SHIFT);
}

/*! \brief Sets the MFT0 fix clock source
 *
 * This function sets the MFT0 fix clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of MFT0 fix clock source
 *                    - 0b : clk_lpo32
 *                    - 1b : RTC_CLKIN
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetFixMft0Src(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->FIX_MFT0;

    tmp &= ~PCC1_FIX_MFT0_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_FIX_MFT0_SRC_SHIFT)) & PCC1_FIX_MFT0_SRC_MASK);
    obj->FIX_MFT0 = tmp;
}

/*! \brief Gets the MFT1 fix clock source
 *
 * This function gets the current MFT1 fix clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return MFT1 fix clock source
 *         - 0b : clk_lpo32
 *         - 1b : RTC_CLKIN
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetFixMft1Src(const Pcc1RegType *obj)
{
    return ((obj->FIX_MFT1 & PCC1_FIX_MFT1_SRC_MASK) >> PCC1_FIX_MFT1_SRC_SHIFT);
}

/*! \brief Sets the MFT1 fix clock source
 *
 * This function sets the MFT1 fix clock source.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of MFT1 fix clock source
 *                    - 0b : clk_lpo32
 *                    - 1b : RTC_CLKIN
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetFixMft1Src(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->FIX_MFT1;

    tmp &= ~PCC1_FIX_MFT1_SRC_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_FIX_MFT1_SRC_SHIFT)) & PCC1_FIX_MFT1_SRC_MASK);
    obj->FIX_MFT1 = tmp;
}

/*! \brief Gets the FLS_CTRL modulecounter clock divide ratio
 *
 * This function gets the current FLS_CTRL modulecounter clock divide ratio.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return FLS_CTRL modulecounter clock divide ratio
 *         - 0h : 1
 *         - 1h : 2
 *         - 2h : 3
 *            .
 *            .
 *            .
 *         - Fh : 16
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetFlsCtlCntDiv(const Pcc1RegType *obj)
{
    return ((obj->FLS_CTL & PCC1_FLS_CTL_CNT_DIV_MASK) >> PCC1_FLS_CTL_CNT_DIV_SHIFT);
}

/*! \brief Sets the FLS_CTRL modulecounter clock divide ratio
 *
 * This function sets the FLS_CTRL modulecounter clock divide ratio.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of FLS_CTRL modulecounter clock divide ratio
 *                    - 0h : 1
 *                    - 1h : 2
 *                    - 2h : 3
 *                       .
 *                       .
 *                       .
 *                    - Fh : 16
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetFlsCtlCntDiv(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->FLS_CTL;

    tmp &= ~PCC1_FLS_CTL_CNT_DIV_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_FLS_CTL_CNT_DIV_SHIFT)) & PCC1_FLS_CTL_CNT_DIV_MASK);
    obj->FLS_CTL = tmp;
}

/*! \brief Gets the FLS_CTL clock enable
 *
 * This function gets the current FLS_CTL clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return FLS_CTL clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetFlsCtlCkEn(const Pcc1RegType *obj)
{
    return ((obj->FLS_CTL & PCC1_FLS_CTL_CKEN_MASK) >> PCC1_FLS_CTL_CKEN_SHIFT);
}

/*! \brief Sets the FLS_CTL clock enable
 *
 * This function sets the FLS_CTL clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of FLS_CTL clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetFlsCtlCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->FLS_CTL;

    tmp &= ~PCC1_FLS_CTL_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_FLS_CTL_CKEN_SHIFT)) & PCC1_FLS_CTL_CKEN_MASK);
    obj->FLS_CTL = tmp;
}

/*! \brief Gets the FLS_CTL software reset
 *
 * This function gets the current FLS_CTL software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return FLS_CTL software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetFlsCtlSwR(const Pcc1RegType *obj)
{
    return ((obj->FLS_CTL & PCC1_FLS_CTL_SWR_MASK) >> PCC1_FLS_CTL_SWR_SHIFT);
}

/*! \brief Sets the FLS_CTL software reset
 *
 * This function sets the FLS_CTL software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of FLS_CTL software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetFlsCtlSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->FLS_CTL;

    tmp &= ~PCC1_FLS_CTL_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_FLS_CTL_SWR_SHIFT)) & PCC1_FLS_CTL_SWR_MASK);
    obj->FLS_CTL = tmp;
}

/*! \brief Gets the MPU clock enable
 *
 * This function gets the current MPU clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return MPU clock enable
 *         - 0b : disable
 *         - 1b : enable
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetMpuCkEn(const Pcc1RegType *obj)
{
    return ((obj->MPU & PCC1_MPU_CKEN_MASK) >> PCC1_MPU_CKEN_SHIFT);
}

/*! \brief Sets the MPU clock enable
 *
 * This function sets the MPU clock enable.
 * It works for both function clock and configure clock.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of MPU clock enable
 *                    - 0b : disable
 *                    - 1b : enable
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetMpuCkEn(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MPU;

    tmp &= ~PCC1_MPU_CKEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_MPU_CKEN_SHIFT)) & PCC1_MPU_CKEN_MASK);
    obj->MPU = tmp;
}

/*! \brief Gets the MPU software reset
 *
 * This function gets the current MPU software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \return MPU software reset
 *         - 0b : normal
 *         - 1b : reset
 */
__attribute__((always_inline)) static inline uint8_t Pcc1Reg_GetMpuSwR(const Pcc1RegType *obj)
{
    return ((obj->MPU & PCC1_MPU_SWR_MASK) >> PCC1_MPU_SWR_SHIFT);
}

/*! \brief Sets the MPU software reset
 *
 * This function sets the MPU software reset.
 * It works for both function clock domain and configure clock domain.
 *
 * \param[in] obj : pointer to PCC1 register instance
 * \param[in] value : the value of MPU software reset
 *                    - 0b : normal
 *                    - 1b : reset
 */
__attribute__((always_inline)) static inline void Pcc1Reg_SetMpuSwR(Pcc1RegType *obj, uint8_t value)
{
    uint32_t tmp = obj->MPU;

    tmp &= ~PCC1_MPU_SWR_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PCC1_MPU_SWR_SHIFT)) & PCC1_MPU_SWR_MASK);
    obj->MPU = tmp;
}

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* _PCC1_REG_H_ */
