/*
 * Copyright (c) 2022, Shenzhen CVA Innovation CO.,LTD
 * All rights reserved.
 *
 * Shenzhen CVA Innovation CO.,LTD (CVA chip) is supplying this file for use
 * exclusively with CVA's microcontroller products. This file can be freely
 * distributed within development tools that are supporting such microcontroller
 * products.
 *
 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
 * CVA SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
 * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
 */

#ifndef _PMC_REG_H_
#define _PMC_REG_H_

/*! \brief Contains public interface to various functions related
 *         to the PMC Registers
 */

/*******************************************************************************
 * the includes
 ******************************************************************************/

#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
 * the defines
 ******************************************************************************/

/* WKSRC Bit Fields */
#define PMC_WKSRC_STOP_ST_FLG_MASK             (0x800u)
#define PMC_WKSRC_STOP_ST_FLG_SHIFT            (11u)
#define PMC_WKSRC_STOP_ST_FLG_WIDTH            (1u)
#define PMC_WKSRC_STBY_ST_FLG_MASK             (0x400u)
#define PMC_WKSRC_STBY_ST_FLG_SHIFT            (10u)
#define PMC_WKSRC_STBY_ST_FLG_WIDTH            (1u)
#define PMC_WKSRC_TOUCH_WAKEUP_MASK            (0x200u)
#define PMC_WKSRC_TOUCH_WAKEUP_SHIFT           (9u)
#define PMC_WKSRC_TOUCH_WAKEUP_WIDTH           (1u)
#define PMC_WKSRC_LPTMR_WAKEUP_MASK            (0x100u)
#define PMC_WKSRC_LPTMR_WAKEUP_SHIFT           (8u)
#define PMC_WKSRC_LPTMR_WAKEUP_WIDTH           (1u)
#define PMC_WKSRC_LPIT_WAKEUP_MASK             (0x80u)
#define PMC_WKSRC_LPIT_WAKEUP_SHIFT            (7u)
#define PMC_WKSRC_LPIT_WAKEUP_WIDTH            (1u)
#define PMC_WKSRC_RTC_WAKEUP_MASK              (0x40u)
#define PMC_WKSRC_RTC_WAKEUP_SHIFT             (6u)
#define PMC_WKSRC_RTC_WAKEUP_WIDTH             (1u)
#define PMC_WKSRC_RESET_WAKEUP_MASK            (0x20u)
#define PMC_WKSRC_RESET_WAKEUP_SHIFT           (5u)
#define PMC_WKSRC_RESET_WAKEUP_WIDTH           (1u)
#define PMC_WKSRC_PORTC_WAKEUP_MASK            (0x4u)
#define PMC_WKSRC_PORTC_WAKEUP_SHIFT           (2u)
#define PMC_WKSRC_PORTC_WAKEUP_WIDTH           (1u)
#define PMC_WKSRC_PORTB_WAKEUP_MASK            (0x2u)
#define PMC_WKSRC_PORTB_WAKEUP_SHIFT           (1u)
#define PMC_WKSRC_PORTB_WAKEUP_WIDTH           (1u)
#define PMC_WKSRC_PORTA_WAKEUP_MASK            (0x1u)
#define PMC_WKSRC_PORTA_WAKEUP_SHIFT           (0u)
#define PMC_WKSRC_PORTA_WAKEUP_WIDTH           (1u)

/* PKP Bit Fields */
#define PMC_PKP_PAD_KEEP_MASK                  (0x1u)
#define PMC_PKP_PAD_KEEP_SHIFT                 (0u)
#define PMC_PKP_PAD_KEEP_WIDTH                 (1u)

/* ANACTRL Bit Fields */
#define PMC_ANACTRL_DA_SIRC_EN_MASK            (0x10000u)
#define PMC_ANACTRL_DA_SIRC_EN_SHIFT           (16u)
#define PMC_ANACTRL_DA_SIRC_EN_WIDTH           (1u)
#define PMC_ANACTRL_DA_HPBG_OTP_EN_MASK        (0x80u)
#define PMC_ANACTRL_DA_HPBG_OTP_EN_SHIFT       (7u)
#define PMC_ANACTRL_DA_HPBG_OTP_EN_WIDTH       (1u)
#define PMC_ANACTRL_DA_PMC_SEL_LVW_MASK        (0x60u)
#define PMC_ANACTRL_DA_PMC_SEL_LVW_SHIFT       (5u)
#define PMC_ANACTRL_DA_PMC_SEL_LVW_WIDTH       (2u)
#define PMC_ANACTRL_DA_PMC_EN_LVD_MASK         (0x2u)
#define PMC_ANACTRL_DA_PMC_EN_LVD_SHIFT        (1u)
#define PMC_ANACTRL_DA_PMC_EN_LVD_WIDTH        (1u)
#define PMC_ANACTRL_DA_PMC_EN_LVW_MASK         (0x1u)
#define PMC_ANACTRL_DA_PMC_EN_LVW_SHIFT        (0u)
#define PMC_ANACTRL_DA_PMC_EN_LVW_WIDTH        (1u)

/* GLBCTL Bit Fields */
#define PMC_GLBCTL_CPU_RETETION_EN_MASK        (0x1u)
#define PMC_GLBCTL_CPU_RETETION_EN_SHIFT       (0u)
#define PMC_GLBCTL_CPU_RETETION_EN_WIDTH       (1u)

/* SRAM_LP Bit Fields */
#define PMC_SRAM_LP_SRAM_NORM_ALON_LPSEL_MASK  (0x70000000u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_LPSEL_SHIFT (28u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_LPSEL_WIDTH (3u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_ME_MASK     (0x8000000u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_ME_SHIFT    (27u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_ME_WIDTH    (1u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_SD_MASK     (0x4000000u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_SD_SHIFT    (26u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_SD_WIDTH    (1u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_DS_MASK     (0x2000000u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_DS_SHIFT    (25u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_DS_WIDTH    (1u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_LS_MASK     (0x1000000u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_LS_SHIFT    (24u)
#define PMC_SRAM_LP_SRAM_NORM_ALON_LS_WIDTH    (1u)
#define PMC_SRAM_LP_SRAM_NORM_SHUT_SD_MASK     (0x300000u)
#define PMC_SRAM_LP_SRAM_NORM_SHUT_SD_SHIFT    (20u)
#define PMC_SRAM_LP_SRAM_NORM_SHUT_SD_WIDTH    (2u)
#define PMC_SRAM_LP_SRAM_NORM_SHUT_DS_MASK     (0xC0000u)
#define PMC_SRAM_LP_SRAM_NORM_SHUT_DS_SHIFT    (18u)
#define PMC_SRAM_LP_SRAM_NORM_SHUT_DS_WIDTH    (2u)
#define PMC_SRAM_LP_SRAM_NORM_SHUT_LS_MASK     (0x30000u)
#define PMC_SRAM_LP_SRAM_NORM_SHUT_LS_SHIFT    (16u)
#define PMC_SRAM_LP_SRAM_NORM_SHUT_LS_WIDTH    (2u)
#define PMC_SRAM_LP_SRAM_RET_CPU_SD_SEL_MASK   (0x1000u)
#define PMC_SRAM_LP_SRAM_RET_CPU_SD_SEL_SHIFT  (12u)
#define PMC_SRAM_LP_SRAM_RET_CPU_SD_SEL_WIDTH  (1u)
#define PMC_SRAM_LP_SRAM_RET_CPU_DS_SEL_MASK   (0x800u)
#define PMC_SRAM_LP_SRAM_RET_CPU_DS_SEL_SHIFT  (11u)
#define PMC_SRAM_LP_SRAM_RET_CPU_DS_SEL_WIDTH  (1u)
#define PMC_SRAM_LP_SRAM_RET_CPU_SD_MASK       (0x400u)
#define PMC_SRAM_LP_SRAM_RET_CPU_SD_SHIFT      (10u)
#define PMC_SRAM_LP_SRAM_RET_CPU_SD_WIDTH      (1u)
#define PMC_SRAM_LP_SRAM_RET_CPU_DS_MASK       (0x200u)
#define PMC_SRAM_LP_SRAM_RET_CPU_DS_SHIFT      (9u)
#define PMC_SRAM_LP_SRAM_RET_CPU_DS_WIDTH      (1u)
#define PMC_SRAM_LP_SRAM_RET_CPU_LS_MASK       (0x100u)
#define PMC_SRAM_LP_SRAM_RET_CPU_LS_SHIFT      (8u)
#define PMC_SRAM_LP_SRAM_RET_CPU_LS_WIDTH      (1u)
#define PMC_SRAM_LP_SRAM_RET_SYS_SD_SEL_MASK   (0x10u)
#define PMC_SRAM_LP_SRAM_RET_SYS_SD_SEL_SHIFT  (4u)
#define PMC_SRAM_LP_SRAM_RET_SYS_SD_SEL_WIDTH  (1u)
#define PMC_SRAM_LP_SRAM_RET_SYS_DS_SEL_MASK   (0x8u)
#define PMC_SRAM_LP_SRAM_RET_SYS_DS_SEL_SHIFT  (3u)
#define PMC_SRAM_LP_SRAM_RET_SYS_DS_SEL_WIDTH  (1u)
#define PMC_SRAM_LP_SRAM_RET_SYS_SD_MASK       (0x4u)
#define PMC_SRAM_LP_SRAM_RET_SYS_SD_SHIFT      (2u)
#define PMC_SRAM_LP_SRAM_RET_SYS_SD_WIDTH      (1u)
#define PMC_SRAM_LP_SRAM_RET_SYS_DS_MASK       (0x2u)
#define PMC_SRAM_LP_SRAM_RET_SYS_DS_SHIFT      (1u)
#define PMC_SRAM_LP_SRAM_RET_SYS_DS_WIDTH      (1u)
#define PMC_SRAM_LP_SRAM_RET_SYS_LS_MASK       (0x1u)
#define PMC_SRAM_LP_SRAM_RET_SYS_LS_SHIFT      (0u)
#define PMC_SRAM_LP_SRAM_RET_SYS_LS_WIDTH      (1u)

/* TKCTL Bit Fields */
#define PMC_TKCTL_TKANADLYSEL_MASK             (0x80000000u)
#define PMC_TKCTL_TKANADLYSEL_SHIFT            (31u)
#define PMC_TKCTL_TKANADLYSEL_WIDTH            (1u)
#define PMC_TKCTL_TKSUSPDLYSEL_MASK            (0x40000000u)
#define PMC_TKCTL_TKSUSPDLYSEL_SHIFT           (30u)
#define PMC_TKCTL_TKSUSPDLYSEL_WIDTH           (1u)
#define PMC_TKCTL_TKLPFLDOMODE_MASK            (0x20000000u)
#define PMC_TKCTL_TKLPFLDOMODE_SHIFT           (29u)
#define PMC_TKCTL_TKLPFLDOMODE_WIDTH           (1u)
#define PMC_TKCTL_PMC2TKDLYEN_MASK             (0x10000000u)
#define PMC_TKCTL_PMC2TKDLYEN_SHIFT            (28u)
#define PMC_TKCTL_PMC2TKDLYEN_WIDTH            (1u)
#define PMC_TKCTL_TKPMC2CPUHSHKVLD_MASK        (0x80000u)
#define PMC_TKCTL_TKPMC2CPUHSHKVLD_SHIFT       (19u)
#define PMC_TKCTL_TKPMC2CPUHSHKVLD_WIDTH       (1u)
#define PMC_TKCTL_TKPMC2CPUHSHKVAL_MASK        (0x7FFFFu)
#define PMC_TKCTL_TKPMC2CPUHSHKVAL_SHIFT       (0u)
#define PMC_TKCTL_TKPMC2CPUHSHKVAL_WIDTH       (19u)

/* TKLP Bit Fields */
#define PMC_TKLP_TKLPENST_MASK                 (0x04u)
#define PMC_TKLP_TKLPENST_SHIFT                (2u)
#define PMC_TKLP_TKLPENST_WIDTH                (1u)
#define PMC_TKLP_TKEXTRSTEN_MASK               (0x02u)
#define PMC_TKLP_TKEXTRSTEN_SHIFT              (1u)
#define PMC_TKLP_TKEXTRSTEN_WIDTH              (1u)
#define PMC_TKLP_TKLPEN_MASK                   (0x01u)
#define PMC_TKLP_TKLPEN_SHIFT                  (0u)
#define PMC_TKLP_TKLPEN_WIDTH                  (1u)

/* TK_HSHK_ST Bit Fields */
#define PMC_TKHSHKST_TKSUSPENDCNT_MASK         (0x7FFFFu)
#define PMC_TKHSHKST_TKSUSPENDCNT_SHIFT        (0u)
#define PMC_TKHSHKST_TKSUSPENDCNT_WIDTH        (19u)

/* KEY Bit Fields */
#define PMC_KEY_KEY_VAL_MASK                   (0xFFFFFFFFu)
#define PMC_KEY_KEY_VAL_SHIFT                  (0u)
#define PMC_KEY_KEY_VAL_WIDTH                  (32u)

/* UNLOCK Bit Fields */
#define PMC_UNLOCK_UNLOCK_MASK                 (0x1u)
#define PMC_UNLOCK_UNLOCK_SHIFT                (0u)
#define PMC_UNLOCK_UNLOCK_WIDTH                (1u)

/*******************************************************************************
 * the typedefs
 ******************************************************************************/

/*! \brief The definition of PMC registers
 */
typedef struct _PmcRegType_
{
    volatile uint32_t WKSRC;        /*!< * wakeup source register, offset: 0x0 */
    volatile uint32_t PKP;          /*!< * PAD keep register, offset: 0x4 */
    volatile uint32_t ANACTRL;      /*!< * Analog Interface Signal Control register, offset: 0x8 */
    uint32_t          Reserved0[1]; /*!< * Reserved register, offset: 0xC */
    volatile uint32_t GLBCTL;       /*!< * global control register, offset: 0x10 */
    uint32_t          Reserved1[1]; /*!< * Reserved register, offset: 0x14 */
    volatile uint32_t SRAM_LP;      /*!< * SRAM Low Power control register, offset: 0x18 */
    uint32_t          Reserved2[1]; /*!< * Reserved register, offset: 0x1C */
    volatile uint32_t TKCTL;        /*!< * touch control register, offset: 0x20 */
    volatile uint32_t TKLP;         /*!< * touch low power control register, offset: 0x24 */
    uint32_t          Reserved3[1]; /*!< * Reserved register, offset: 0x28 */
    volatile uint32_t TK_HSHK_ST;   /*!< * low power handshake counter register, offset: 0x2C */
    volatile uint32_t KEY;          /*!< * Key register, offset: 0x30 */
    uint32_t          UNLOCK;       /*!< * Key Unlock Indicator register, offset: 0x34 */
} PmcRegType;

/*******************************************************************************
 * the globals
 ******************************************************************************/

/*******************************************************************************
 * the function prototypes
 ******************************************************************************/
/*! \brief Gets the STOP state flag
 *
 * This function gets the current STOP state flag.
 * This bit indicates that PMC went through STOP mode before. Write 1 to this bit clears it.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return STOP state flag
 *         - 0b : PMC did not go through STOP mode
 *         - 1b : PMC went through STOP mode
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetWkSrcStopStFlg(const PmcRegType *obj)
{
    return ((obj->WKSRC & PMC_WKSRC_STOP_ST_FLG_MASK) >> PMC_WKSRC_STOP_ST_FLG_SHIFT);
}
/*! \brief Clears the STOP state flag
 *
 * This function clears the STOP state flag.
 * This bit indicates that PMC went through STOP mode before. Write 1 to this bit clears it.
 *
 * \param[in] obj : pointer to PMC register instance
 */
__attribute__((always_inline)) static inline void PmcReg_CleartWkSrcStopStFlg(PmcRegType *obj)
{
    obj->WKSRC = ((uint32_t)(1)) << PMC_WKSRC_STOP_ST_FLG_SHIFT;
}
/*! \brief Gets the STANDBY state flag
 *
 * This function gets the current STANDBY state flag.
 * This bit indicates that PMC went through STANDBY mode before.  If power state transfer to STANDBY mode is aborted, this bit will not be asserted. Write 1 to this bit clears it.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return STANDBY state flag
 *         - 0b : PMC did not go through STANDBY mode
 *         - 1b : PMC went through STANDBY mode
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetWkSrcStbyStFlg(const PmcRegType *obj)
{
    return ((obj->WKSRC & PMC_WKSRC_STBY_ST_FLG_MASK) >> PMC_WKSRC_STBY_ST_FLG_SHIFT);
}
/*! \brief Clears the STANDBY state flag
 *
 * This function clears the STANDBY state flag.
 * This bit indicates that PMC went through STANDBY mode before.  If power state transfer to STANDBY mode is aborted, this bit will not be asserted. Write 1 to this bit clears it.
 *
 * \param[in] obj : pointer to PMC register instance
 */
__attribute__((always_inline)) static inline void PmcReg_ClearWkSrcStbyStFlg(PmcRegType *obj)
{
    obj->WKSRC = ((uint32_t)(1)) << PMC_WKSRC_STBY_ST_FLG_SHIFT;
}
/*! \brief Gets the TOUCH wake up source flag
 *
 * This function gets the current TOUCH wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return TOUCH wake up source flag
 *         - 0b : Wake up source not asserted
 *         - 1b : Wake up source asserted
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetWkSrcTouchWakeup(const PmcRegType *obj)
{
    return ((obj->WKSRC & PMC_WKSRC_TOUCH_WAKEUP_MASK) >> PMC_WKSRC_TOUCH_WAKEUP_SHIFT);
}
/*! \brief Clears the TOUCH wake up source flag
 *
 * This function clears the TOUCH wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 */
__attribute__((always_inline)) static inline void PmcReg_ClearWkSrcTouchWakeup(PmcRegType *obj)
{
    obj->WKSRC = ((uint32_t)(1)) << PMC_WKSRC_TOUCH_WAKEUP_SHIFT;
}
/*! \brief Gets the LPTMR wake up source flag
 *
 * This function gets the current LPTMR wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return LPTMR wake up source flag
 *         - 0b : Wake up source not asserted
 *         - 1b : Wake up source asserted
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetWkSrcLptmrWakeup(const PmcRegType *obj)
{
    return ((obj->WKSRC & PMC_WKSRC_LPTMR_WAKEUP_MASK) >> PMC_WKSRC_LPTMR_WAKEUP_SHIFT);
}
/*! \brief Clears the LPTMR wake up source flag
 *
 * This function clears the LPTMR wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 */
__attribute__((always_inline)) static inline void PmcReg_ClearWkSrcLptmrWakeup(PmcRegType *obj)
{
    obj->WKSRC = ((uint32_t)(1)) << PMC_WKSRC_LPTMR_WAKEUP_SHIFT;
}
/*! \brief Gets the LPIT wake up source flag
 *
 * This function gets the current LPIT wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return LPIT wake up source flag
 *         - 0b : Wake up source not asserted
 *         - 1b : Wake up source asserted
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetWkSrcLpitWakeup(const PmcRegType *obj)
{
    return ((obj->WKSRC & PMC_WKSRC_LPIT_WAKEUP_MASK) >> PMC_WKSRC_LPIT_WAKEUP_SHIFT);
}
/*! \brief Clears the LPIT wake up source flag
 *
 * This function clears the LPIT wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 */
__attribute__((always_inline)) static inline void PmcReg_ClearWkSrcLpitWakeup(PmcRegType *obj)
{
    obj->WKSRC = ((uint32_t)(1)) << PMC_WKSRC_LPIT_WAKEUP_SHIFT;
}
/*! \brief Gets the RTC wake up source flag
 *
 * This function gets the current RTC wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return RTC wake up source flag
 *         - 0b : Wake up source not asserted
 *         - 1b : Wake up source asserted
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetWkSrcRtcWakeup(const PmcRegType *obj)
{
    return ((obj->WKSRC & PMC_WKSRC_RTC_WAKEUP_MASK) >> PMC_WKSRC_RTC_WAKEUP_SHIFT);
}
/*! \brief Clears the RTC wake up source flag
 *
 * This function clears the RTC wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 */
__attribute__((always_inline)) static inline void PmcReg_ClearWkSrcRtcWakeup(PmcRegType *obj)
{
    obj->WKSRC = ((uint32_t)(1)) << PMC_WKSRC_RTC_WAKEUP_SHIFT;
}
/*! \brief Gets the RESET wake up source flag
 *
 * This function gets the current RESET wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return RESET wake up source flag
 *         - 0b : Wake up source not asserted
 *         - 1b : Wake up source asserted
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetWkSrcResetWakeup(const PmcRegType *obj)
{
    return ((obj->WKSRC & PMC_WKSRC_RESET_WAKEUP_MASK) >> PMC_WKSRC_RESET_WAKEUP_SHIFT);
}
/*! \brief Clears the RESET wake up source flag
 *
 * This function clears the RESET wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 */
__attribute__((always_inline)) static inline void PmcReg_ClearWkSrcResetWakeup(PmcRegType *obj)
{
    obj->WKSRC = ((uint32_t)(1)) << PMC_WKSRC_RESET_WAKEUP_SHIFT;
}
/*! \brief Gets the PORTC wake up source flag
 *
 * This function gets the current PORTC wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return PORTC wake up source flag
 *         - 0b : Wake up source not asserted
 *         - 1b : Wake up source asserted
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetWkSrcPortcWakeup(const PmcRegType *obj)
{
    return ((obj->WKSRC & PMC_WKSRC_PORTC_WAKEUP_MASK) >> PMC_WKSRC_PORTC_WAKEUP_SHIFT);
}
/*! \brief Clears the PORTC wake up source flag
 *
 * This function clears the PORTC wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 */
__attribute__((always_inline)) static inline void PmcReg_ClearWkSrcPortcWakeup(PmcRegType *obj)
{
    obj->WKSRC = ((uint32_t)(1)) << PMC_WKSRC_PORTC_WAKEUP_SHIFT;
}
/*! \brief Gets the PORTB wake up source flag
 *
 * This function gets the current PORTB wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return PORTB wake up source flag
 *         - 0b : Wake up source not asserted
 *         - 1b : Wake up source asserted
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetWkSrcPortbWakeup(const PmcRegType *obj)
{
    return ((obj->WKSRC & PMC_WKSRC_PORTB_WAKEUP_MASK) >> PMC_WKSRC_PORTB_WAKEUP_SHIFT);
}
/*! \brief Clears the PORTB wake up source flag
 *
 * This function clears the PORTB wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 */
__attribute__((always_inline)) static inline void PmcReg_ClearWkSrcPortbWakeup(PmcRegType *obj)
{
    obj->WKSRC = ((uint32_t)(1)) << PMC_WKSRC_PORTB_WAKEUP_SHIFT;
}
/*! \brief Gets the PORTA wake up source flag
 *
 * This function gets the current PORTA wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return PORTA wake up source flag
 *         - 0b : Wake up source not asserted
 *         - 1b : Wake up source asserted
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetWkSrcPortaWakeup(const PmcRegType *obj)
{
    return ((obj->WKSRC & PMC_WKSRC_PORTA_WAKEUP_MASK) >> PMC_WKSRC_PORTA_WAKEUP_SHIFT);
}
/*! \brief Clears the PORTA wake up source flag
 *
 * This function clears the PORTA wake up source flag.
 *
 * \param[in] obj : pointer to PMC register instance
 */
__attribute__((always_inline)) static inline void PmcReg_ClearWkSrcPortaWakeup(PmcRegType *obj)
{
    obj->WKSRC = ((uint32_t)(1)) << PMC_WKSRC_PORTA_WAKEUP_SHIFT;
}
/*! \brief Gets the PAD keep enable
 *
 * This function gets the current PAD keep enable.
 * This bit can be set by hardware only. When this bit is set, SHUT domain PAD remains at the state at when it goes into STANDBY mode. Writing 1 to this bit clears it, and PAD can toggle with SHUT domain modules.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return PAD keep enable
 *         - 0b : PAD keep is not enabled
 *         - 1b : PAD keep is enabled
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetPkpPadKeep(const PmcRegType *obj)
{
    return ((obj->PKP & PMC_PKP_PAD_KEEP_MASK) >> PMC_PKP_PAD_KEEP_SHIFT);
}
/*! \brief Clears the PAD keep enable
 *
 * This function clears the PAD keep enable.
 * This bit can be set by hardware only. When this bit is set, SHUT domain PAD remains at the state at when it goes into STANDBY mode. Writing 1 to this bit clears it, and PAD can toggle with SHUT domain modules.
 *
 * \param[in] obj : pointer to PMC register instance
 */
__attribute__((always_inline)) static inline void PmcReg_ClearPkpPadKeep(PmcRegType *obj)
{
    obj->PKP = ((uint32_t)(1)) << PMC_PKP_PAD_KEEP_SHIFT;
}
/*! \brief Gets the Slow internal reference clock enable control
 *
 * This function gets the current Slow internal reference clock enable control.
 * This bit is valid only when ANA_DEBUG_EN is set, and is ignored if ANA_DEBUG_EN is cleared.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return Slow internal reference clock enable control
 *         - 0b : disable SIRC
 *         - 1b : enable SIRC
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetAnaCtrlDaSircEn(const PmcRegType *obj)
{
    return ((obj->ANACTRL & PMC_ANACTRL_DA_SIRC_EN_MASK) >> PMC_ANACTRL_DA_SIRC_EN_SHIFT);
}
/*! \brief Sets the Slow internal reference clock enable control
 *
 * This function sets the Slow internal reference clock enable control.
 * This bit is valid only when ANA_DEBUG_EN is set, and is ignored if ANA_DEBUG_EN is cleared.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of Slow internal reference clock enable control
 *                    - 0b : disable SIRC
 *                    - 1b : enable SIRC
 */
__attribute__((always_inline)) static inline void PmcReg_SetAnaCtrlDaSircEn(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ANACTRL;
    tmp &= ~PMC_ANACTRL_DA_SIRC_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_ANACTRL_DA_SIRC_EN_SHIFT)) & PMC_ANACTRL_DA_SIRC_EN_MASK);
    obj->ANACTRL = tmp;
}
/*! \brief Gets the OTP function enable control
 *
 * This function gets the current OTP function enable control.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return OTP function enable control
 *         - 0b : Disable
 *         - 1b : Enable;
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetAnaCtrlDaHpbgOtpEn(const PmcRegType *obj)
{
    return ((obj->ANACTRL & PMC_ANACTRL_DA_HPBG_OTP_EN_MASK) >> PMC_ANACTRL_DA_HPBG_OTP_EN_SHIFT);
}
/*! \brief Sets the OTP function enable control
 *
 * This function sets the OTP function enable control.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of OTP function enable control
 *                    - 0b : Disable
 *                    - 1b : Enable;
 */
__attribute__((always_inline)) static inline void PmcReg_SetAnaCtrlDaHpbgOtpEn(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ANACTRL;
    tmp &= ~PMC_ANACTRL_DA_HPBG_OTP_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_ANACTRL_DA_HPBG_OTP_EN_SHIFT)) & PMC_ANACTRL_DA_HPBG_OTP_EN_MASK);
    obj->ANACTRL = tmp;
}
/*! \brief Gets the Low voltage warning(LVW) level select
 *
 * This function gets the current Low voltage warning(LVW) level select.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return Low voltage warning(LVW) level select
 *         - 00b : V_LVW1
 *         - 01b : V_LVW2
 *         - 01b : V_LVW3
 *         - 11b : Not defined
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetAnaCtrlDaPmcSelLvw(const PmcRegType *obj)
{
    return ((obj->ANACTRL & PMC_ANACTRL_DA_PMC_SEL_LVW_MASK) >> PMC_ANACTRL_DA_PMC_SEL_LVW_SHIFT);
}
/*! \brief Sets the Low voltage warning(LVW) level select
 *
 * This function sets the Low voltage warning(LVW) level select.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of Low voltage warning(LVW) level select
 *                    - 00b : V_LVW1
 *                    - 01b : V_LVW2
 *                    - 01b : V_LVW3
 *                    - 11b : Not defined
 */
__attribute__((always_inline)) static inline void PmcReg_SetAnaCtrlDaPmcSelLvw(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ANACTRL;
    tmp &= ~PMC_ANACTRL_DA_PMC_SEL_LVW_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_ANACTRL_DA_PMC_SEL_LVW_SHIFT)) & PMC_ANACTRL_DA_PMC_SEL_LVW_MASK);
    obj->ANACTRL = tmp;
}
/*! \brief Gets the Low voltage detect(LVD) control
 *
 * This function gets the current Low voltage detect(LVD) control.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return Low voltage detect(LVD) control
 *         - 0b : Disable low voltage detect function
 *         - 1b : Enable low voltage detect function
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetAnaCtrlDaPmcEnLvd(const PmcRegType *obj)
{
    return ((obj->ANACTRL & PMC_ANACTRL_DA_PMC_EN_LVD_MASK) >> PMC_ANACTRL_DA_PMC_EN_LVD_SHIFT);
}
/*! \brief Sets the Low voltage detect(LVD) control
 *
 * This function sets the Low voltage detect(LVD) control.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of Low voltage detect(LVD) control
 *                    - 0b : Disable low voltage detect function
 *                    - 1b : Enable low voltage detect function
 */
__attribute__((always_inline)) static inline void PmcReg_SetAnaCtrlDaPmcEnLvd(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ANACTRL;
    tmp &= ~PMC_ANACTRL_DA_PMC_EN_LVD_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_ANACTRL_DA_PMC_EN_LVD_SHIFT)) & PMC_ANACTRL_DA_PMC_EN_LVD_MASK);
    obj->ANACTRL = tmp;
}
/*! \brief Gets the Low voltage warning(LVW) control
 *
 * This function gets the current Low voltage warning(LVW) control.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return Low voltage warning(LVW) control
 *         - 0b : Disable low voltage warning function
 *         - 1b : Enable low voltage warning function
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetAnaCtrlDaPmcEnLvw(const PmcRegType *obj)
{
    return ((obj->ANACTRL & PMC_ANACTRL_DA_PMC_EN_LVW_MASK) >> PMC_ANACTRL_DA_PMC_EN_LVW_SHIFT);
}
/*! \brief Sets the Low voltage warning(LVW) control
 *
 * This function sets the Low voltage warning(LVW) control.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of Low voltage warning(LVW) control
 *                    - 0b : Disable low voltage warning function
 *                    - 1b : Enable low voltage warning function
 */
__attribute__((always_inline)) static inline void PmcReg_SetAnaCtrlDaPmcEnLvw(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->ANACTRL;
    tmp &= ~PMC_ANACTRL_DA_PMC_EN_LVW_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_ANACTRL_DA_PMC_EN_LVW_SHIFT)) & PMC_ANACTRL_DA_PMC_EN_LVW_MASK);
    obj->ANACTRL = tmp;
}

/*! \brief Gets the CPU retention enable
 *
 * This function gets the current CPU retention enable.
 * enable the PMC cpu retention function, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return CPU retention enable
 *         - 0 : CPU retention function is disabled.
 *         - 1 : CPU retention function is enabled. Attention: release to the user this register must description as the following content. #CPU after reset then start to excute instruction from the begining when exit standby mode or CPU start to excute instruction from the states before enter standby mode when exit standby mode.#
 *         - 0 : excute instruction from the begining.
 *         - 1 : excute instruction from the states before enter standby mode.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetGlbCtlCpuRetetionEn(const PmcRegType *obj)
{
    return ((obj->GLBCTL & PMC_GLBCTL_CPU_RETETION_EN_MASK) >> PMC_GLBCTL_CPU_RETETION_EN_SHIFT);
}
/*! \brief Sets the CPU retention enable
 *
 * This function sets the CPU retention enable.
 * enable the PMC cpu retention function, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of CPU retention enable
 *                    - 0 : CPU retention function is disabled.
 *                    - 1 : CPU retention function is enabled. Attention: release to the user this register must description as the following content. #CPU after reset then start to excute instruction from the begining when exit standby mode or CPU start to excute instruction from the states before enter standby mode when exit standby mode.#
 *                    - 0 : excute instruction from the begining.
 *                    - 1 : excute instruction from the states before enter standby mode.
 */
__attribute__((always_inline)) static inline void PmcReg_SetGlbCtlCpuRetetionEn(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->GLBCTL;
    tmp &= ~PMC_GLBCTL_CPU_RETETION_EN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_GLBCTL_CPU_RETETION_EN_SHIFT)) & PMC_GLBCTL_CPU_RETETION_EN_MASK);
    obj->GLBCTL = tmp;
}
/*! \brief Gets the SRAM retention ALON low power control source select
 *
 * This function gets the current SRAM retention ALON low power control source select.
 * SRAM retention ALON low power control source select, when lock function disable this register can write access. bit0 for LS mode, bit1 for DS mode, bit2 for ME(memory enable)
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention ALON low power control source select
 *         - 0 : SRAM retention ALON low power control is hardware
 *         - 1 : SRAM retention ALON low power control is register configuration
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramNormAlonLpsel(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_NORM_ALON_LPSEL_MASK) >> PMC_SRAM_LP_SRAM_NORM_ALON_LPSEL_SHIFT);
}
/*! \brief Sets the SRAM retention ALON low power control source select
 *
 * This function sets the SRAM retention ALON low power control source select.
 * SRAM retention ALON low power control source select, when lock function disable this register can write access. bit0 for LS mode, bit1 for DS mode, bit2 for ME(memory enable)
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention ALON low power control source select
 *                    - 0 : SRAM retention ALON low power control is hardware
 *                    - 1 : SRAM retention ALON low power control is register configuration
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramNormAlonLpsel(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_NORM_ALON_LPSEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_NORM_ALON_LPSEL_SHIFT)) & PMC_SRAM_LP_SRAM_NORM_ALON_LPSEL_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention ALON memory enable control
 *
 * This function gets the current SRAM retention ALON memory enable control.
 * enable ALON SRAMmemory function, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention ALON memory enable control
 *         - 0 : ALON SRAM memory function is disabled.
 *         - 1 : ALON SRAM memory function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramNormAlonMe(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_NORM_ALON_ME_MASK) >> PMC_SRAM_LP_SRAM_NORM_ALON_ME_SHIFT);
}
/*! \brief Sets the SRAM retention ALON memory enable control
 *
 * This function sets the SRAM retention ALON memory enable control.
 * enable ALON SRAMmemory function, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention ALON memory enable control
 *                    - 0 : ALON SRAM memory function is disabled.
 *                    - 1 : ALON SRAM memory function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramNormAlonMe(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_NORM_ALON_ME_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_NORM_ALON_ME_SHIFT)) & PMC_SRAM_LP_SRAM_NORM_ALON_ME_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention ALON shut down control
 *
 * This function gets the current SRAM retention ALON shut down control.
 * enable the PMC SRAM retention ALON function to shut down mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention ALON shut down control
 *         - 0 : sram retention SD mode for ALON function is disabled.
 *         - 1 : sram retention SD mode  for ALON function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramNormAlonSd(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_NORM_ALON_SD_MASK) >> PMC_SRAM_LP_SRAM_NORM_ALON_SD_SHIFT);
}
/*! \brief Sets the SRAM retention ALON shut down control
 *
 * This function sets the SRAM retention ALON shut down control.
 * enable the PMC SRAM retention ALON function to shut down mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention ALON shut down control
 *                    - 0 : sram retention SD mode for ALON function is disabled.
 *                    - 1 : sram retention SD mode  for ALON function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramNormAlonSd(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_NORM_ALON_SD_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_NORM_ALON_SD_SHIFT)) & PMC_SRAM_LP_SRAM_NORM_ALON_SD_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention ALON deep sleep control
 *
 * This function gets the current SRAM retention ALON deep sleep control.
 * enable the PMC SRAM retention ALON function to deep sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention ALON deep sleep control
 *         - 0 : sram retention DS mode for ALON function is disabled.
 *         - 1 : sram retention DS mode  for ALON function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramNormAlonDs(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_NORM_ALON_DS_MASK) >> PMC_SRAM_LP_SRAM_NORM_ALON_DS_SHIFT);
}
/*! \brief Sets the SRAM retention ALON deep sleep control
 *
 * This function sets the SRAM retention ALON deep sleep control.
 * enable the PMC SRAM retention ALON function to deep sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention ALON deep sleep control
 *                    - 0 : sram retention DS mode for ALON function is disabled.
 *                    - 1 : sram retention DS mode  for ALON function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramNormAlonDs(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_NORM_ALON_DS_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_NORM_ALON_DS_SHIFT)) & PMC_SRAM_LP_SRAM_NORM_ALON_DS_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention ALON light sleep control
 *
 * This function gets the current SRAM retention ALON light sleep control.
 * enable the PMC SRAM retention ALON function to light sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention ALON light sleep control
 *         - 0 : sram retention LS mode for ALON function is disabled.
 *         - 1 : sram retention LS mode  for ALON function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramNormAlonLs(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_NORM_ALON_LS_MASK) >> PMC_SRAM_LP_SRAM_NORM_ALON_LS_SHIFT);
}
/*! \brief Sets the SRAM retention ALON light sleep control
 *
 * This function sets the SRAM retention ALON light sleep control.
 * enable the PMC SRAM retention ALON function to light sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention ALON light sleep control
 *                    - 0 : sram retention LS mode for ALON function is disabled.
 *                    - 1 : sram retention LS mode  for ALON function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramNormAlonLs(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_NORM_ALON_LS_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_NORM_ALON_LS_SHIFT)) & PMC_SRAM_LP_SRAM_NORM_ALON_LS_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention SHUT shut down control
 *
 * This function gets the current SRAM retention SHUT shut down control.
 * enable the PMC SRAM retention SHUT function to shut down mode, when lock function disable this register can write access. bit0 for flash sram， bit1 for can sram control； per bi
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention SHUT shut down control
 *         - 0 : sram retention SD mode for SHUT function is disabled. per bit *         - 1 : sram retention SD mode  for SHUT function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramNormShutSd(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_NORM_SHUT_SD_MASK) >> PMC_SRAM_LP_SRAM_NORM_SHUT_SD_SHIFT);
}
/*! \brief Sets the SRAM retention SHUT shut down control
 *
 * This function sets the SRAM retention SHUT shut down control.
 * enable the PMC SRAM retention SHUT function to shut down mode, when lock function disable this register can write access. bit0 for flash sram， bit1 for can sram control； per bi
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention SHUT shut down control
 *                    - 0 : sram retention SD mode for SHUT function is disabled. per bit *                    - 1 : sram retention SD mode  for SHUT function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramNormShutSd(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_NORM_SHUT_SD_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_NORM_SHUT_SD_SHIFT)) & PMC_SRAM_LP_SRAM_NORM_SHUT_SD_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention SHUT deep sleep control
 *
 * This function gets the current SRAM retention SHUT deep sleep control.
 * enable the PMC SRAM retention SHUT function to deep sleep mode, when lock function disable this register can write access. bit0 for flash sram， bit1 for can sram control； per bi
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention SHUT deep sleep control
 *         - 0 : sram retention DS mode for SHUT function is disabled. per bit *         - 1 : sram retention DS mode  for SHUT function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramNormShutDs(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_NORM_SHUT_DS_MASK) >> PMC_SRAM_LP_SRAM_NORM_SHUT_DS_SHIFT);
}
/*! \brief Sets the SRAM retention SHUT deep sleep control
 *
 * This function sets the SRAM retention SHUT deep sleep control.
 * enable the PMC SRAM retention SHUT function to deep sleep mode, when lock function disable this register can write access. bit0 for flash sram， bit1 for can sram control； per bi
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention SHUT deep sleep control
 *                    - 0 : sram retention DS mode for SHUT function is disabled. per bit *                    - 1 : sram retention DS mode  for SHUT function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramNormShutDs(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_NORM_SHUT_DS_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_NORM_SHUT_DS_SHIFT)) & PMC_SRAM_LP_SRAM_NORM_SHUT_DS_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention SHUT light sleep control
 *
 * This function gets the current SRAM retention SHUT light sleep control.
 * enable the PMC SRAM retention SHUT function to light sleep mode, when lock function disable this register can write access. bit0 for flash sram， bit1 for can sram control； per bi
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention SHUT light sleep control
 *         - 0 : sram retention LS mode for SHUT function is disabled. per bit *         - 1 : sram retention LS mode  for SHUT function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramNormShutLs(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_NORM_SHUT_LS_MASK) >> PMC_SRAM_LP_SRAM_NORM_SHUT_LS_SHIFT);
}
/*! \brief Sets the SRAM retention SHUT light sleep control
 *
 * This function sets the SRAM retention SHUT light sleep control.
 * enable the PMC SRAM retention SHUT function to light sleep mode, when lock function disable this register can write access. bit0 for flash sram， bit1 for can sram control； per bi
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention SHUT light sleep control
 *                    - 0 : sram retention LS mode for SHUT function is disabled. per bit *                    - 1 : sram retention LS mode  for SHUT function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramNormShutLs(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_NORM_SHUT_LS_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_NORM_SHUT_LS_SHIFT)) & PMC_SRAM_LP_SRAM_NORM_SHUT_LS_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention CPU shut down source control
 *
 * This function gets the current SRAM retention CPU shut down source control.
 * select the source for  the CPU SRAM retention cpu  shut down mode, when lock disable the register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention CPU shut down source control
 *         - 0 : cpu sram retention SD mode source is hw control
 *         - 1 : cpu sram retention SD mode source is register control
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramRetCpuSdSel(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_RET_CPU_SD_SEL_MASK) >> PMC_SRAM_LP_SRAM_RET_CPU_SD_SEL_SHIFT);
}
/*! \brief Sets the SRAM retention CPU shut down source control
 *
 * This function sets the SRAM retention CPU shut down source control.
 * select the source for  the CPU SRAM retention cpu  shut down mode, when lock disable the register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention CPU shut down source control
 *                    - 0 : cpu sram retention SD mode source is hw control
 *                    - 1 : cpu sram retention SD mode source is register control
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramRetCpuSdSel(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_RET_CPU_SD_SEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_RET_CPU_SD_SEL_SHIFT)) & PMC_SRAM_LP_SRAM_RET_CPU_SD_SEL_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention CPU deep sleep source control
 *
 * This function gets the current SRAM retention CPU deep sleep source control.
 * select the source for  the CPU SRAM retention cpu  deep sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention CPU deep sleep source control
 *         - 0 : cpu sram retention DS mode source is hw control
 *         - 1 : cpu sram retention DS mode source is register control
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramRetCpuDsSel(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_RET_CPU_DS_SEL_MASK) >> PMC_SRAM_LP_SRAM_RET_CPU_DS_SEL_SHIFT);
}
/*! \brief Sets the SRAM retention CPU deep sleep source control
 *
 * This function sets the SRAM retention CPU deep sleep source control.
 * select the source for  the CPU SRAM retention cpu  deep sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention CPU deep sleep source control
 *                    - 0 : cpu sram retention DS mode source is hw control
 *                    - 1 : cpu sram retention DS mode source is register control
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramRetCpuDsSel(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_RET_CPU_DS_SEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_RET_CPU_DS_SEL_SHIFT)) & PMC_SRAM_LP_SRAM_RET_CPU_DS_SEL_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention CPU shut down control
 *
 * This function gets the current SRAM retention CPU shut down control.
 * enable the PMC SRAM retention cpu function to shut down mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention CPU shut down control
 *         - 0 : sram retention SD mode for cpu function is disabled.
 *         - 1 : sram retention SD mode  for cpu function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramRetCpuSd(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_RET_CPU_SD_MASK) >> PMC_SRAM_LP_SRAM_RET_CPU_SD_SHIFT);
}
/*! \brief Sets the SRAM retention CPU shut down control
 *
 * This function sets the SRAM retention CPU shut down control.
 * enable the PMC SRAM retention cpu function to shut down mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention CPU shut down control
 *                    - 0 : sram retention SD mode for cpu function is disabled.
 *                    - 1 : sram retention SD mode  for cpu function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramRetCpuSd(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_RET_CPU_SD_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_RET_CPU_SD_SHIFT)) & PMC_SRAM_LP_SRAM_RET_CPU_SD_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention CPU deep sleep control
 *
 * This function gets the current SRAM retention CPU deep sleep control.
 * enable the PMC SRAM retention cpu function to deep sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention CPU deep sleep control
 *         - 0 : sram retention DS mode for cpu function is disabled.
 *         - 1 : sram retention DS mode  for cpu function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramRetCpuDs(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_RET_CPU_DS_MASK) >> PMC_SRAM_LP_SRAM_RET_CPU_DS_SHIFT);
}
/*! \brief Sets the SRAM retention CPU deep sleep control
 *
 * This function sets the SRAM retention CPU deep sleep control.
 * enable the PMC SRAM retention cpu function to deep sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention CPU deep sleep control
 *                    - 0 : sram retention DS mode for cpu function is disabled.
 *                    - 1 : sram retention DS mode  for cpu function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramRetCpuDs(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_RET_CPU_DS_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_RET_CPU_DS_SHIFT)) & PMC_SRAM_LP_SRAM_RET_CPU_DS_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention CPU light sleep control
 *
 * This function gets the current SRAM retention CPU light sleep control.
 * enable the PMC SRAM retention cpu function to light sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention CPU light sleep control
 *         - 0 : sram retention LS mode for cpu function is disabled.
 *         - 1 : sram retention LS mode  for cpu function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramRetCpuLs(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_RET_CPU_LS_MASK) >> PMC_SRAM_LP_SRAM_RET_CPU_LS_SHIFT);
}
/*! \brief Sets the SRAM retention CPU light sleep control
 *
 * This function sets the SRAM retention CPU light sleep control.
 * enable the PMC SRAM retention cpu function to light sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention CPU light sleep control
 *                    - 0 : sram retention LS mode for cpu function is disabled.
 *                    - 1 : sram retention LS mode  for cpu function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramRetCpuLs(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_RET_CPU_LS_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_RET_CPU_LS_SHIFT)) & PMC_SRAM_LP_SRAM_RET_CPU_LS_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention SYS shut down source control
 *
 * This function gets the current SRAM retention SYS shut down source control.
 * select the source for  the SYS SRAM retention SYS  shut down mode, when lock disable the register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention SYS shut down source control
 *         - 0 : SYS sram retention SD mode source is hw control
 *         - 1 : SYS sram retention SD mode source is register control
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramRetSysSdSel(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_RET_SYS_SD_SEL_MASK) >> PMC_SRAM_LP_SRAM_RET_SYS_SD_SEL_SHIFT);
}
/*! \brief Sets the SRAM retention SYS shut down source control
 *
 * This function sets the SRAM retention SYS shut down source control.
 * select the source for  the SYS SRAM retention SYS  shut down mode, when lock disable the register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention SYS shut down source control
 *                    - 0 : SYS sram retention SD mode source is hw control
 *                    - 1 : SYS sram retention SD mode source is register control
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramRetSysSdSel(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_RET_SYS_SD_SEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_RET_SYS_SD_SEL_SHIFT)) & PMC_SRAM_LP_SRAM_RET_SYS_SD_SEL_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention SYS deep sleep source control
 *
 * This function gets the current SRAM retention SYS deep sleep source control.
 * select the source for  the SYS SRAM retention SYS  deep sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention SYS deep sleep source control
 *         - 0 : SYS sram retention DS mode source is hw control
 *         - 1 : SYS sram retention DS mode source is register control
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramRetSysDsSel(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_RET_SYS_DS_SEL_MASK) >> PMC_SRAM_LP_SRAM_RET_SYS_DS_SEL_SHIFT);
}
/*! \brief Sets the SRAM retention SYS deep sleep source control
 *
 * This function sets the SRAM retention SYS deep sleep source control.
 * select the source for  the SYS SRAM retention SYS  deep sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention SYS deep sleep source control
 *                    - 0 : SYS sram retention DS mode source is hw control
 *                    - 1 : SYS sram retention DS mode source is register control
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramRetSysDsSel(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_RET_SYS_DS_SEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_RET_SYS_DS_SEL_SHIFT)) & PMC_SRAM_LP_SRAM_RET_SYS_DS_SEL_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention SYS shut down control
 *
 * This function gets the current SRAM retention SYS shut down control.
 * enable the PMC SRAM retention SYS function to shut down mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention SYS shut down control
 *         - 0 : sram retention SD mode for SYS function is disabled.
 *         - 1 : sram retention SD mode  for SYS function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramRetSysSd(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_RET_SYS_SD_MASK) >> PMC_SRAM_LP_SRAM_RET_SYS_SD_SHIFT);
}
/*! \brief Sets the SRAM retention SYS shut down control
 *
 * This function sets the SRAM retention SYS shut down control.
 * enable the PMC SRAM retention SYS function to shut down mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention SYS shut down control
 *                    - 0 : sram retention SD mode for SYS function is disabled.
 *                    - 1 : sram retention SD mode  for SYS function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramRetSysSd(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_RET_SYS_SD_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_RET_SYS_SD_SHIFT)) & PMC_SRAM_LP_SRAM_RET_SYS_SD_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention SYS deep sleep control
 *
 * This function gets the current SRAM retention SYS deep sleep control.
 * enable the PMC SRAM retention SYS function to deep sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention SYS deep sleep control
 *         - 0 : sram retention DS mode for SYS function is disabled.
 *         - 1 : sram retention DS mode  for SYS function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramRetSysDs(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_RET_SYS_DS_MASK) >> PMC_SRAM_LP_SRAM_RET_SYS_DS_SHIFT);
}
/*! \brief Sets the SRAM retention SYS deep sleep control
 *
 * This function sets the SRAM retention SYS deep sleep control.
 * enable the PMC SRAM retention SYS function to deep sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention SYS deep sleep control
 *                    - 0 : sram retention DS mode for SYS function is disabled.
 *                    - 1 : sram retention DS mode  for SYS function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramRetSysDs(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_RET_SYS_DS_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_RET_SYS_DS_SHIFT)) & PMC_SRAM_LP_SRAM_RET_SYS_DS_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the SRAM retention SYS light sleep control
 *
 * This function gets the current SRAM retention SYS light sleep control.
 * enable the PMC SRAM retention SYS function to light sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return SRAM retention SYS light sleep control
 *         - 0 : sram retention LS mode for SYS function is disabled.
 *         - 1 : sram retention LS mode  for SYS function is enabled.
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetSramLpSramRetSysLs(const PmcRegType *obj)
{
    return ((obj->SRAM_LP & PMC_SRAM_LP_SRAM_RET_SYS_LS_MASK) >> PMC_SRAM_LP_SRAM_RET_SYS_LS_SHIFT);
}
/*! \brief Sets the SRAM retention SYS light sleep control
 *
 * This function sets the SRAM retention SYS light sleep control.
 * enable the PMC SRAM retention SYS function to light sleep mode, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of SRAM retention SYS light sleep control
 *                    - 0 : sram retention LS mode for SYS function is disabled.
 *                    - 1 : sram retention LS mode  for SYS function is enabled.
 */
__attribute__((always_inline)) static inline void PmcReg_SetSramLpSramRetSysLs(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->SRAM_LP;
    tmp &= ~PMC_SRAM_LP_SRAM_RET_SYS_LS_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_SRAM_LP_SRAM_RET_SYS_LS_SHIFT)) & PMC_SRAM_LP_SRAM_RET_SYS_LS_MASK);
    obj->SRAM_LP = tmp;
}
/*! \brief Gets the Touch low power enable
 *
 * This function gets the current Touch low power enable.
 * enable the PMC touch low power control function, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return Touch low power enable
 *         - 0 : touch can not work at standby mode;
 *         - 1 : touch can work at standby mode;
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetTklpTkLpen(const PmcRegType *obj)
{
    return ((obj->TKLP & PMC_TKLP_TKLPEN_MASK) >> PMC_TKLP_TKLPEN_SHIFT);
}
/*! \brief Sets the Touch low power enable
 *
 * This function sets the Touch low power enable.
 * enable the PMC touch low power control function, when lock function disable this register can write access.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of Touch low power enable
 *                    - 0 : touch can not work at standby mode;
 *                    - 1 : touch can work at standby mode;
 */
__attribute__((always_inline)) static inline void PmcReg_SetTklpTkLpen(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->TKLP;
    tmp &= ~PMC_TKLP_TKLPEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_TKLP_TKLPEN_SHIFT)) & PMC_TKLP_TKLPEN_MASK);
    obj->TKLP = tmp;
}
/*! \brief Gets the Touch low power enable with external reset enable
 *
 * This function gets the current Touch low power enable with external reset enable.
 * enable the PMC touch low power control function with extrst.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return Touch low power enable with external reset enable
 *         - 0 : touch low power enable only use RG_TK_LPEN;
 *         - 1 : touch low power enable use RG_TK_LPEN and extRST;
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetTklpTkExtrsten(const PmcRegType *obj)
{
    return ((obj->TKLP & PMC_TKLP_TKEXTRSTEN_MASK) >> PMC_TKLP_TKEXTRSTEN_SHIFT);
}
/*! \brief Sets the Touch low power enable with external reset enable
 *
 * This function sets the Touch low power enable with external reset enable.
 * enable the PMC touch low power control function with extrst.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of Touch low power enable
 *                    - 0 : touch low power enable only use RG_TK_LPEN;
 *                    - 1 : touch low power enable use RG_TK_LPEN and extRST;
 */
__attribute__((always_inline)) static inline void PmcReg_SetTklpTkExtrsten(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->TKLP;
    tmp &= ~PMC_TKLP_TKEXTRSTEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_TKLP_TKEXTRSTEN_SHIFT)) & PMC_TKLP_TKEXTRSTEN_MASK);
    obj->TKLP = tmp;
}
/*! \brief Gets the Touch low power enable status
 *
 * This function gets the current Touch low power enable status.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return Touch low power enable status
 *         - 0 : touch low power enable status is 0;
 *         - 1 : touch low power enable status is 1;
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetTklpTkLpenSt(const PmcRegType *obj)
{
    return ((obj->TKLP & PMC_TKLP_TKLPENST_MASK) >> PMC_TKLP_TKLPENST_SHIFT);
}
/*! \brief Gets the pmc and cpu handshake valid time interval when rg_tk_lpen enable @ standby mode
 *
 * This function gets the current pmc and cpu handshake valid time interval when rg_tk_lpen enable @ standby mode.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return pmc and cpu handshake valid time interval when rg_tk_lpen enable @ standby mode
 *         -  standby mode# This bit configs handshake valid time interval for pmc and cpu. It uses LPO 128K for timing and 1 cycle is about 8us. 0001h : time interval is 1T with clk_LPO. 0002h: time interval is 2T with clk_LPO. 0003h: time interval is 3T with clk_LPO. ...
 */
__attribute__((always_inline)) static inline uint16_t PmcReg_GetTkctlTkPmc2cpuHshkVal(const PmcRegType *obj)
{
    return ((obj->TKCTL & PMC_TKCTL_TKPMC2CPUHSHKVAL_MASK) >> PMC_TKCTL_TKPMC2CPUHSHKVAL_SHIFT);
}
/*! \brief Sets the pmc and cpu handshake valid time interval when rg_tk_lpen enable @ standby mode
 *
 * This function sets the pmc and cpu handshake valid time interval when rg_tk_lpen enable @ standby mode.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of pmc and cpu handshake valid time interval when rg_tk_lpen enable @ standby mode
 *                    -  standby mode# This bit configs handshake valid time interval for pmc and cpu. It uses LPO 128K for timing and 1 cycle is about 8us. 0001h : time interval is 1T with clk_LPO. 0002h: time interval is 2T with clk_LPO. 0003h: time interval is 3T with clk_LPO. ...
 */
__attribute__((always_inline)) static inline void PmcReg_SetTkctlTkPmc2cpuHshkVal(PmcRegType *obj, uint16_t value)
{
    uint32_t tmp = obj->TKCTL;
    tmp &= ~PMC_TKCTL_TKPMC2CPUHSHKVAL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_TKCTL_TKPMC2CPUHSHKVAL_SHIFT)) & PMC_TKCTL_TKPMC2CPUHSHKVAL_MASK);
    obj->TKCTL = tmp;
}
/*! \brief Gets the pmc and cpu handshake valid flag when rg_tk_lpen valid
 *
 * This function gets the current pmc and cpu handshake valid flag when rg_tk_lpen valid @ standby mode.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return pmc and cpu handshake valid time interval when rg_tk_lpen enable @ standby mode
 *         - 0b : pmc will not enter stadnby mode when rg_tk_lpen valid
 *         - 1b : pmc allowed to enter stadnby mode when rg_tk_lpen valid
 */
__attribute__((always_inline)) static inline uint16_t PmcReg_GetTkctlTkPmc2cpuHshkVld(const PmcRegType *obj)
{
    return ((obj->TKCTL & PMC_TKCTL_TKPMC2CPUHSHKVLD_MASK) >> PMC_TKCTL_TKPMC2CPUHSHKVLD_SHIFT);
}
/*! \brief Gets the PMC to Touch ACK delay select
 *
 * This function gets the current PMC to Touch ACK delay select.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return  PMC to Touch ACK delay select
 *         - 0b : PMC to Touch ACK has delay
 *         - 1b : PMC to Touch ACK no delay
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetTkctlPmc2TkDlyen(const PmcRegType *obj)
{
    return ((obj->TKCTL & PMC_TKCTL_PMC2TKDLYEN_MASK) >> PMC_TKCTL_PMC2TKDLYEN_SHIFT);
}
/*! \brief Sets the PMC to Touch ACK delay select
 *
 * This function sets the PMC to Touch ACK delay select.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of PMC to Touch ACK delay select
 *                    - 0b : PMC to Touch ACK has delay
 *                    - 1b : PMC to Touch ACK no delay
 */
__attribute__((always_inline)) static inline void PmcReg_SetTkctlPmc2TkDlyen(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->TKCTL;
    tmp &= ~PMC_TKCTL_PMC2TKDLYEN_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_TKCTL_PMC2TKDLYEN_SHIFT)) & PMC_TKCTL_PMC2TKDLYEN_MASK);
    obj->TKCTL = tmp;
}

/*! \brief Gets the FLDO power mode when support touch low power in standby mode
 *
 * This function gets the current FLDO power mode when support touch low power in standby mode.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return  FLDO power mode when support touch low power in standby mode
 *         - 0b : FLDO is toggle same as MLDO when touch active in standby mode
 *         - 1b : FLDO is at Low power mode when touch active in standby mode
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetTkctlTkLpFldoMode(const PmcRegType *obj)
{
    return ((obj->TKCTL & PMC_TKCTL_TKLPFLDOMODE_MASK) >> PMC_TKCTL_TKLPFLDOMODE_SHIFT);
}
/*! \brief Sets the FLDO power mode when support touch low power in standby mode
 *
 * This function sets the FLDO power mode when support touch low power in standby mode.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : FLDO power mode when support touch low power in standby mode
 *                    - 0b : FLDO is toggle same as MLDO when touch active in standby mode
 *                    - 1b : FLDO is at Low power mode when touch active in standby mode
 */
__attribute__((always_inline)) static inline void PmcReg_SetTkctlTkLpFldoMode(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->TKCTL;
    tmp &= ~PMC_TKCTL_TKLPFLDOMODE_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_TKCTL_TKLPFLDOMODE_SHIFT)) & PMC_TKCTL_TKLPFLDOMODE_MASK);
    obj->TKCTL = tmp;
}

/*! \brief Gets the touch wake up delay selection @ standby mode
 *
 * This function gets the current touch  wake up delay selection @ standby mode.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return touch  wake up delay selection @ standby mode
 *         -  standby mode# This bit configs analog side delay after touch  wake up. It uses LPO 128K for timing and 1 cycle is about 8us.
 *         - 0b : wait 1~2 LPO cycles
 *         - 1b : wait 2~3 LPO cycles
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetTkctlTkAnaDlySel(const PmcRegType *obj)
{
    return ((obj->TKCTL & PMC_TKCTL_TKANADLYSEL_MASK) >> PMC_TKCTL_TKANADLYSEL_SHIFT);
}
/*! \brief Sets the touch wake up delay selection @ standby mode
 *
 * This function sets the touch  wake up delay selection @ standby mode.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of touch  wake up delay selection @ standby mode
 *                    -  standby mode# This bit configs analog side delay after touch  wake up. It uses LPO 128K for timing and 1 cycle is about 8us.
 *                    - 0b : wait 1~2 LPO cycles
 *                    - 1b : wait 2~3 LPO cycles
 */
__attribute__((always_inline)) static inline void PmcReg_SetTkctlTkAnaDlySel(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->TKCTL;
    tmp &= ~PMC_TKCTL_TKANADLYSEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_TKCTL_TKANADLYSEL_SHIFT)) & PMC_TKCTL_TKANADLYSEL_MASK);
    obj->TKCTL = tmp;
}
/*! \brief Gets the touch suspend delay selection @ standby mode
 *
 * This function gets the current touch  suspend delay selection @ standby mode.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return touch  suspend delay selection @ standby mode
 *         -  standby mode# This bit configs pmc side delay after touch  suspend done. It uses LPO 128K for timing and 1 cycle is about 8us.
 *         - 0b : no delay
 *         - 1b : wait 0~1 LPO cycles
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetTkctlTkSuspDlySel(const PmcRegType *obj)
{
    return ((obj->TKCTL & PMC_TKCTL_TKSUSPDLYSEL_MASK) >> PMC_TKCTL_TKSUSPDLYSEL_SHIFT);
}
/*! \brief Sets the touch suspend delay selection @ standby mode
 *
 * This function sets the touch  suspend delay selection @ standby mode.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of touch  suspend delay selection @ standby mode
 *                    -  standby mode# This bit configs pmc side delay after touch  suspend done. It uses LPO 128K for timing and 1 cycle is about 8us.
 *                    - 0b : no delay
 *                    - 1b : wait 0~1 LPO cycles
 */
__attribute__((always_inline)) static inline void PmcReg_SetTkctlTkSuspDlySel(PmcRegType *obj, uint8_t value)
{
    uint32_t tmp = obj->TKCTL;
    tmp &= ~PMC_TKCTL_TKSUSPDLYSEL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_TKCTL_TKSUSPDLYSEL_SHIFT)) & PMC_TKCTL_TKSUSPDLYSEL_MASK);
    obj->TKCTL = tmp;
}
/*! \brief Gets the PMC Key Value
 *
 * This function gets the current PMC Key Value.
 * In order to config RWP registers, writing  0x1015_FF11 to KEY_VAL to unlock key. When key is locked, RWP registers are read only.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return PMC Key Value
 *         - 0x1015_FF11 : key is unlocked
 *         - others : key is locked
 */
__attribute__((always_inline)) static inline uint32_t PmcReg_GetKeyVal(const PmcRegType *obj)
{
    return ((obj->KEY & PMC_KEY_KEY_VAL_MASK) >> PMC_KEY_KEY_VAL_SHIFT);
}
/*! \brief Sets the PMC Key Value
 *
 * This function sets the PMC Key Value.
 * In order to config RWP registers, writing  0x1015_FF11 to KEY_VAL to unlock key. When key is locked, RWP registers are read only.
 *
 * \param[in] obj : pointer to PMC register instance
 * \param[in] value : the value of PMC Key Value
 *                    - 0x1015_FF11 : key is unlocked
 *                    - others : key is locked
 */
__attribute__((always_inline)) static inline void PmcReg_SetKeyVal(PmcRegType *obj, uint32_t value)
{
    uint32_t tmp = obj->KEY;
    tmp &= ~PMC_KEY_KEY_VAL_MASK;
    tmp |= (((uint32_t)(((uint32_t)(value)) << PMC_KEY_KEY_VAL_SHIFT)) & PMC_KEY_KEY_VAL_MASK);
    obj->KEY = tmp;
}
/*! \brief Gets the PMC Public Register Unlock
 *
 * This function gets the current PMC Public Register Unlock.
 * For all registers that has write protection, PUB_UNLOCK must be 1 to grant write access. When PUB_UNLOCK is 0, write access is ignored, and read access executes normally. Write to PUB_KEY to change PUB_UNLOCK bit.
 *
 * \param[in] obj : pointer to PMC register instance
 * \return PMC Public Register Unlock
 *         - 0b : write protected registers are locked
 *         - 1b : write protected registers are unlocked
 */
__attribute__((always_inline)) static inline uint8_t PmcReg_GetUnlock(const PmcRegType *obj)
{
    return ((obj->UNLOCK & PMC_UNLOCK_UNLOCK_MASK) >> PMC_UNLOCK_UNLOCK_SHIFT);
}

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* _PMC_REG_H_ */
