From b4ad53727137ffaec3dfec94d91e0d42457f01f1 Mon Sep 17 00:00:00 2001 From: sunbeam Date: Mon, 9 Dec 2024 13:33:35 +0800 Subject: [PATCH] =?UTF-8?q?=E6=9B=B4=E6=96=B0SDK=E8=87=B32.2.1?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- cva_asw_m0146/SDK/middleware/isotp/isotp.c | 9 +- cva_asw_m0146/SDK/middleware/isotp/isotp.h | 2 +- cva_asw_m0146/SDK/middleware/nvm/nvm_extra.h | 12 +- .../devices/CVM014x/drivers/adc/adc_drv.c | 16 +- .../devices/CVM014x/drivers/adc/adc_drv.h | 19 - .../devices/CVM014x/drivers/cmp/cmp_drv.c | 33 - .../devices/CVM014x/drivers/cmp/cmp_drv.h | 3 - .../drivers/cpu/startup/system_M014x.c | 12 + .../drivers/cpu/startup/system_M014x.h | 2 +- .../devices/CVM014x/drivers/edma/edma_drv.c | 1 + .../devices/CVM014x/drivers/eim/eim_drv.c | 2 +- .../devices/CVM014x/drivers/erm/erm_drv.h | 22 +- .../devices/CVM014x/drivers/fccu/fccu_drv.c | 4 +- .../devices/CVM014x/drivers/flash/flash_drv.c | 62 +- .../devices/CVM014x/drivers/flash/flash_drv.h | 46 +- .../CVM014x/drivers/flexcan/flexcan_drv.c | 36 +- .../devices/CVM014x/drivers/pins/pins_drv.c | 4 +- .../CVM014x/drivers/pwmlite/pwmlite_drv.c | 80 +- .../devices/CVM014x/drivers/spi/spi_drv.c | 6 +- .../devices/CVM014x/drivers/uart/uart_drv.h | 6 +- .../platform/devices/CVM014x/reg/adc_reg.h | 156 ++- .../platform/devices/CVM014x/reg/axbs_reg.h | 4 +- .../platform/devices/CVM014x/reg/cache_reg.h | 78 +- .../platform/devices/CVM014x/reg/cmp_reg.h | 59 +- .../platform/devices/CVM014x/reg/edma_reg.h | 4 + .../platform/devices/CVM014x/reg/erm_reg.h | 8 +- .../platform/devices/CVM014x/reg/fccu_reg.h | 4 +- .../devices/CVM014x/reg/flexcan_reg.h | 1135 +++++++++++++++-- .../platform/devices/CVM014x/reg/ftfc_reg.h | 24 +- .../platform/devices/CVM014x/reg/i2c_reg.h | 35 +- .../platform/devices/CVM014x/reg/port_reg.h | 2 + .../platform/devices/CVM014x/reg/uart_reg.h | 24 + .../platform/devices/CVM014x/reg/wdg_reg.h | 8 - 33 files changed, 1430 insertions(+), 488 deletions(-) diff --git a/cva_asw_m0146/SDK/middleware/isotp/isotp.c b/cva_asw_m0146/SDK/middleware/isotp/isotp.c index 80b2317..11b9443 100644 --- a/cva_asw_m0146/SDK/middleware/isotp/isotp.c +++ b/cva_asw_m0146/SDK/middleware/isotp/isotp.c @@ -653,10 +653,13 @@ void IsoTp_HandleIncomingCanMsg(IsoTpType *obj, uint32_t id, const uint8_t *data else { /* Send FC when BS reaches limit */ - if(0 == --obj->receiveBlockSizeCount) + if(obj->blockSize > 0) { - obj->receiveBlockSizeCount = obj->blockSize; - IsoTp_SendFlowControl(obj, ISOTP_PCI_FLOW_STATUS_CONTINUE, obj->receiveBlockSizeCount, ISOTP_DEFAULT_ST_MIN); + if(0 == --obj->receiveBlockSizeCount) + { + obj->receiveBlockSizeCount = obj->blockSize; + IsoTp_SendFlowControl(obj, ISOTP_PCI_FLOW_STATUS_CONTINUE, obj->receiveBlockSizeCount, ISOTP_DEFAULT_ST_MIN); + } } } } diff --git a/cva_asw_m0146/SDK/middleware/isotp/isotp.h b/cva_asw_m0146/SDK/middleware/isotp/isotp.h index c9fe255..c485b89 100644 --- a/cva_asw_m0146/SDK/middleware/isotp/isotp.h +++ b/cva_asw_m0146/SDK/middleware/isotp/isotp.h @@ -54,7 +54,7 @@ extern "C" { /*! \brief The STmin parameter value specifies the minimum time gap allowed between * the transmission of consecutive frame network protocol data units */ -#define ISOTP_DEFAULT_ST_MIN (0) +#define ISOTP_DEFAULT_ST_MIN (1) /*! \brief This parameter indicate how many FC N_PDU WTs can be transmitted by the * receiver in a row. diff --git a/cva_asw_m0146/SDK/middleware/nvm/nvm_extra.h b/cva_asw_m0146/SDK/middleware/nvm/nvm_extra.h index c9dc991..c28e76b 100644 --- a/cva_asw_m0146/SDK/middleware/nvm/nvm_extra.h +++ b/cva_asw_m0146/SDK/middleware/nvm/nvm_extra.h @@ -89,12 +89,12 @@ typedef enum */ typedef enum { - NVM_STATUS_IDLE = 0x00, - NVM_STATUS_READ = 0x01, - NVM_STATUS_WRITE = 0x02, - NVM_STATUS_GC = 0x03, - NVM_STATUS_UNKNOW = 0x04, - NVM_STATUS_ERROR = 0x05, + NVM_STATUS_IDLE = 0x01, + NVM_STATUS_READ = 0x02, + NVM_STATUS_WRITE = 0x03, + NVM_STATUS_GC = 0x04, + NVM_STATUS_UNKNOW = 0x05, + NVM_STATUS_ERROR = 0x06, } Nvm_StatusType; /*! \brief Define the type of virtual function for Notification. diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/adc/adc_drv.c b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/adc/adc_drv.c index a9bca93..609bebf 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/adc/adc_drv.c +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/adc/adc_drv.c @@ -223,10 +223,9 @@ void AdcDrv_Configure(AdcDrvType *obj, const AdcDrv_ConfigType *userConfig) /* enable DMA */ AdcReg_SetSc2DmaEn(obj->adcReg, userConfig->dmaEnable); - /* select the conversion trigger source */ - AdcReg_SetSc2AdTrg(obj->adcReg, (uint8_t)userConfig->trgSrcCfg.trgSrc); + /* Enable trigger*/ + AdcReg_SetSc2AdTrg(obj->adcReg, 1); - /*! \note If ADCDRV_SW_TRIGGER is selected, hwTrgSrc, pretrgSrc, swPretrgSrc will be ignored.*/ if(obj->adcNumber == ADCDRV_INSTANCE_0) { /* select hardware trigger source */ @@ -303,8 +302,6 @@ void AdcDrv_GetDefaultConfig(AdcDrv_ConfigType *userConfig) userConfig->interleaveMode.state[i] = false; } - /*! \note If ADCDRV_SW_TRIGGER is selected, hwTrgSrc, pretrgSrc, swPretrgSrc will be ignored.*/ - userConfig->trgSrcCfg.trgSrc = ADCDRV_SW_TRIGGER; userConfig->trgSrcCfg.hwTrgSrc = ADCDRV_HW_TRGSRC_PDB; userConfig->trgSrcCfg.swPretrgSrc = ADCDRV_SWPRETRG_PRETRIGGER_0; userConfig->trgSrcCfg.pretrgSrc = ADCDRV_PRETRG_PDB_PRETRIGGER; @@ -316,11 +313,6 @@ void AdcDrv_GetDefaultConfig(AdcDrv_ConfigType *userConfig) } } -void AdcDrv_SwTrg(AdcDrvType *obj) -{ - AdcReg_SwTrig(obj->adcReg); -} - void AdcDrv_ClrLockTrg(AdcDrvType *obj) { AdcReg_ClrTrg(obj->adcReg); @@ -384,10 +376,6 @@ void AdcDrv_GetConfig(AdcDrvType *obj, AdcDrv_ConfigType *currentConfig) /* get enable DMA */ currentConfig->dmaEnable = AdcReg_GetSc2DmaEn(obj->adcReg); - /* get the conversion trigger source */ - currentConfig->trgSrcCfg.trgSrc = (AdcDrv_TrgMode)AdcReg_GetSc2AdTrg(obj->adcReg); - - /*! \note If ADCDRV_SW_TRIGGER is selected, hwTrgSrc, pretrgSrc, swPretrgSrc will be ignored.*/ if(obj->adcNumber == ADCDRV_INSTANCE_0) { /* get hardware trigger source */ diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/adc/adc_drv.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/adc/adc_drv.h index c4925fd..9539c2f 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/adc/adc_drv.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/adc/adc_drv.h @@ -66,15 +66,6 @@ typedef enum } AdcDrv_SelfTestValue; -/*! \brief ADC type of conversion trigger selection - */ -typedef enum -{ - ADCDRV_SW_TRIGGER = 0x0U, /*!< Conversion trigger select software trigger.*/ - ADCDRV_HW_TRIGGER = 0x1U, /*!< Conversion trigger select hardware trigger.*/ - -} AdcDrv_TrgMode; - /*! \brief ADC type of resolution selection */ typedef enum @@ -138,7 +129,6 @@ typedef enum ADCDRV_INCHN_LPVBG = 0x19U, /*!< LPVBG.*/ ADCDRV_INCHN_VBG = 0x1AU, /*!< VBG.*/ ADCDRV_INCHN_LDO_VOLT = 0x1BU, /*!< monitor_ldo_volt.*/ - ADCDRV_INCHN_SUPPLY_VOLT = 0x1CU, /*!< monitor_supply_volt.*/ ADCDRV_INCHN_SELF_TEST_VOLTAGE = 0x1DU, /*!< selftest_volt.*/ ADCDRV_INCHN_DISABLE = 0x1FU, /*!< Module is disabled.*/ } AdcDrv_InChnType; @@ -208,7 +198,6 @@ typedef struct _AdcDrv_InitParamsType_ */ typedef struct _AdcDrv_TrgSrcCfgType_ { - AdcDrv_TrgMode trgSrc; /*!< Conversion trigger select*/ AdcDrv_HwTrgSrc hwTrgSrc; /*!< Selects hardware trigger source for ADC.*/ ADCDRV_SwPretrgSrc swPretrgSrc; /*!< Selects software pretrigger sources for ADC*/ ADCDRV_PretrgSrc pretrgSrc; /*!< Selects pretrigger sources for ADC*/ @@ -326,14 +315,6 @@ extern void AdcDrv_GetConfig(AdcDrvType *obj, AdcDrv_ConfigType *currentConfig); */ extern void AdcDrv_ClrLockTrg(AdcDrvType *obj); -/*! \brief ADC software trigger - * - * This function for ADC clear lock trigger - * - * \param[in] obj : pointer to ADC driver instance - */ -extern void AdcDrv_SwTrg(AdcDrvType *obj); - /*! \brief Get ADC data result * * This function for get ADC data result diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cmp/cmp_drv.c b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cmp/cmp_drv.c index 597d384..6736f6a 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cmp/cmp_drv.c +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cmp/cmp_drv.c @@ -105,16 +105,6 @@ void CmpDrv_ConfigureNormal(CmpDrvType *obj, const CmpDrv_ConfigType *userConfig CmpReg_SetOffsetReg(obj->reg, userConfig->normalCfg.hystOffsetState); CmpReg_SetLpfselReg(obj->reg, userConfig->normalCfg.lpfsel); - /* Configuration of self test voltage generator */ - if(userConfig->normalCfg.testVEnable) - { - CmpReg_SetStpdReg(obj->reg, CMP_TEST_VOLTAGE_ENABLE); - } - else - { - CmpReg_SetStpdReg(obj->reg, CMP_TEST_VOLTAGE_DISABLE); - } - /* Configuration of DAC */ CmpReg_SetVrselReg(obj->reg, userConfig->dacCfg.dacVoltInSel); CmpReg_SetVoselReg(obj->reg, userConfig->dacCfg.dacVoltScale); @@ -160,16 +150,6 @@ void CmpDrv_ConfigureTriggerMode(CmpDrvType *obj, const CmpDrv_ConfigType *userC CmpReg_SetOffsetReg(obj->reg, userConfig->normalCfg.hystOffsetState); CmpReg_SetLpfselReg(obj->reg, userConfig->normalCfg.lpfsel); - /* Configuration of self test voltage generator */ - if(userConfig->normalCfg.testVEnable) - { - CmpReg_SetStpdReg(obj->reg, CMP_TEST_VOLTAGE_ENABLE); - } - else - { - CmpReg_SetStpdReg(obj->reg, CMP_TEST_VOLTAGE_DISABLE); - } - /* Configuration of DAC */ CmpReg_SetVrselReg(obj->reg, userConfig->dacCfg.dacVoltInSel); CmpReg_SetVoselReg(obj->reg, userConfig->dacCfg.dacVoltScale); @@ -217,16 +197,6 @@ void CmpDrv_GetConfig(const CmpDrvType *obj, CmpDrv_ConfigType *userConfig) userConfig->normalCfg.hystOffsetState = (CmpDrv_OffsetType)(CmpReg_GetOffsetReg(obj->reg)); userConfig->normalCfg.lpfsel = (CmpDrv_LpfselType)(CmpReg_GetLpfselReg(obj->reg)); - /* Get configuration of self test voltage generator */ - if(CmpReg_GetStpdReg(obj->reg) == CMP_TEST_VOLTAGE_DISABLE) - { - userConfig->normalCfg.testVEnable = false; - } - else - { - userConfig->normalCfg.testVEnable = true; - } - /* Configuration of DAC */ userConfig->dacCfg.dacVoltInSel = (CmpDrv_VrselType)(CmpReg_GetVrselReg(obj->reg)); userConfig->dacCfg.dacVoltScale = CmpReg_GetVoselReg(obj->reg); @@ -264,9 +234,6 @@ void CmpDrv_GetDefaultConfig(CmpDrv_ConfigType *userConfig) userConfig->normalCfg.hystOffsetState = CMPDRV_OFFSET_LEVEL_0; userConfig->normalCfg.lpfsel = CMPDRV_LPFSEL_10MHz; - /* Get configuration of self test voltage generator */ - userConfig->normalCfg.testVEnable = false; - /* Configuration of DAC */ userConfig->dacCfg.dacVoltInSel = CMPDRV_VRSEL_VIN1; userConfig->dacCfg.dacVoltScale = 127U; diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cmp/cmp_drv.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cmp/cmp_drv.h index 5def185..c22bc0d 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cmp/cmp_drv.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cmp/cmp_drv.h @@ -102,8 +102,6 @@ typedef enum { CMPDRV_DAC = 0U, /*!< IN0, from the 8-bit DAC output*/ CMPDRV_MUX = 1U, /*!< IN1, from the analog 8-1 mux(P/N MUX)*/ - CMPDRV_TEST0 = 2U, /*!< from the test signal 0*/ - CMPDRV_TEST1 = 3U, /*!< from the test signal 1*/ } CmpDrv_InPortType; /*! \brief CMP type of channel selection. @@ -177,7 +175,6 @@ typedef struct _CmpDrv_NormalCfgType_ CmpDrv_HystctrType hystLvl; /*!< Comparator hard block hysteresis control */ CmpDrv_OffsetType hystOffsetState; /*!< Comparator hard block offset control */ CmpDrv_LpfselType lpfsel; /*!< CMP input channel low-pass filer cut-off frequency select signal */ - bool testVEnable; /*!< Self Test Voltage Generator Power Down enable */ } CmpDrv_NormalCfgType; /*! \brief Definition of configuration of CMP driver of the analog mux diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cpu/startup/system_M014x.c b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cpu/startup/system_M014x.c index 0a891a8..aba706e 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cpu/startup/system_M014x.c +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cpu/startup/system_M014x.c @@ -48,6 +48,18 @@ void SystemInit(void) AcgReg_SetLockKey(ACG, 0xFA8623E4); /* Unlock ACG */ ScgReg_SetLockKey(SCG, 0x53436D65); /* Unlock SCG */ + /* Switch system clock to default clock */ + if(AcgReg_GetStSysSt(ACG) == 2) + { + /* Flash AHB bus read access time configure */ + FtfcReg_SetFcnfgBusReadTm(FTFC, 0); /* 1T required */ + AcgReg_SetSysSrcSys(ACG, 0); + while(AcgReg_GetStSysSt(ACG) != 0) + { + ; + } + } + #if defined (_USE_EXT_OSC_) /* Use External oscillator */ AcgReg_SetOscRange(ACG, 3); /* set SOSC frequency range(use max value when SOSC as the clock source of the PLL) */ diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cpu/startup/system_M014x.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cpu/startup/system_M014x.h index 72eaf6b..fd272e4 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cpu/startup/system_M014x.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cpu/startup/system_M014x.h @@ -36,7 +36,7 @@ extern "C" { ******************************************************************************/ /* Value of the external crystal or oscillator clock frequency in Hz */ -#define CPU_XTAL_CLK_HZ (8000000u) +#define CPU_XTAL_CLK_HZ (16000000u) #if CPU_XTAL_CLK_HZ > 40000000 #error "The external crystal or oscillator clock frequency is out of range." #endif diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/edma/edma_drv.c b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/edma/edma_drv.c index cf128cd..fed482a 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/edma/edma_drv.c +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/edma/edma_drv.c @@ -736,6 +736,7 @@ void EDmaDrv_PushConfigToSTcd(const EDmaDrv_TransferConfigType *config, EDmaDrv_ stcd->DADDR = config->destAddr; stcd->DOFF = config->destOffset; stcd->CITER = (uint16_t)config->loopTransferConfig->majorLoopIterationCount; + stcd->BITER = (uint16_t)config->loopTransferConfig->majorLoopIterationCount; if(config->scatterGatherEnable) { stcd->DLAST_SGA = (int32_t)config->scatterGatherNextDescAddr; diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/eim/eim_drv.c b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/eim/eim_drv.c index 1a5641c..49b77cb 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/eim/eim_drv.c +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/eim/eim_drv.c @@ -244,7 +244,7 @@ void EimDrv_EnableChannel(EimDrvType *obj, EimDrv_ChnSelType chnNum, bool enable } else { - chnStatusCtrl &= (0 << chnNum); + chnStatusCtrl &= ~(1 << chnNum); } /* Config Error in channel num enable */ EimReg_SetChnEnable(obj->reg, chnStatusCtrl); diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/erm/erm_drv.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/erm/erm_drv.h index bc55975..206dab3 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/erm/erm_drv.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/erm/erm_drv.h @@ -51,17 +51,17 @@ extern "C" { */ typedef enum { - ERMDRV_CH0_RECOVER_IRQ = 0U, /*!< ERM channel0 SRAML single recover Irq enable */ - ERMDRV_CH0_NONRECOVER_IRQ = 1U, /*!< ERM channel0 SRAML single non-recover Irq enable */ - ERMDRV_CH1_RECOVER_IRQ = 2U, /*!< ERM channel1 SRAMU single recover Irq enable */ - ERMDRV_CH1_NONRECOVER_IRQ = 3U, /*!< ERM channel1 SRAMU single non-recover Irq enabl */ - ERMDRV_CH2_RECOVER_IRQ = 4U, /*!< ERM channel2 FTFC single recover Irq enable */ - ERMDRV_CH2_NONRECOVER_IRQ = 5U, /*!< ERM channel2 FTFC single non-recover Irq enabl */ - ERMDRV_CH3_RECOVER_IRQ = 6U, /*!< ERM channel3 FLASH AXBS single recover Irq enable */ - ERMDRV_CH3_NONRECOVER_IRQ = 7U, /*!< ERM channel3 FLASH AXBS single non-recover Irq enabl */ - ERMDRV_CH4_RECOVER_IRQ = 8U, /*!< ERM channel4 CACHE single recover Irq enable */ - ERMDRV_CH4_NONRECOVER_IRQ = 9U, /*!< ERM channel4 CACHE single non-recover Irq enabl */ - ERMDRV_CH_TOTAL_NUM = 10U /*!< ERM channel total num */ + ERMDRV_CH0_RECOVER_IRQ = 0U, /*!< ERM channel0 SRAML single-bit recover Irq enable */ + ERMDRV_CH0_NONRECOVER_IRQ = 1U, /*!< ERM channel0 SRAML multi-bits non-recover Irq enable */ + ERMDRV_CH1_RECOVER_IRQ = 2U, /*!< ERM channel1 SRAMU single-bit recover Irq enable */ + ERMDRV_CH1_NONRECOVER_IRQ = 3U, /*!< ERM channel1 SRAMU multi-bits non-recover Irq enabl */ + ERMDRV_CH2_RECOVER_IRQ = 4U, /*!< ERM channel2 FTFC single-bit recover Irq enable */ + ERMDRV_CH2_NONRECOVER_IRQ = 5U, /*!< ERM channel2 FTFC multi-bits non-recover Irq enabl */ + ERMDRV_CH3_RECOVER_IRQ = 6U, /*!< ERM channel3 FLASH AXBS single-bit recover Irq enable */ + ERMDRV_CH3_NONRECOVER_IRQ = 7U, /*!< ERM channel3 FLASH AXBS multi-bits non-recover Irq enabl */ + ERMDRV_CH4_RECOVER_IRQ = 8U, /*!< ERM channel4 CACHE single-bit recover Irq enable */ + ERMDRV_CH4_NONRECOVER_IRQ = 9U, /*!< ERM channel4 CACHE multi-bits non-recover Irq enabl */ + ERMDRV_CH_TOTAL_NUM = 10U /*!< ERM channel total num */ } ErmDrv_ChnNumType; /*! \brief Definition ERM channel number diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/fccu/fccu_drv.c b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/fccu/fccu_drv.c index d18a3aa..3e20f48 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/fccu/fccu_drv.c +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/fccu/fccu_drv.c @@ -316,10 +316,10 @@ void FccuDrv_GetChnConfig(FccuDrvType *obj, FccuDrv_ChnCtrlType *chnCtrl) chnCtrl->chnNmiEn = FccuReg_GetNmiEn(obj->regFccu); /* Get all channel exception Error Injection status */ - chnCtrl->chnErrInEn = FccuReg_GetEOutEn(obj->regFccu); + chnCtrl->chnErrInEn = FccuReg_GetChE(obj->regFccu); /* Get all channel EOut status */ - chnCtrl->chnEOutEn = FccuReg_GetChE(obj->regFccu); + chnCtrl->chnEOutEn = FccuReg_GetEOutEn(obj->regFccu); /* Get all channel EOut Error type status */ chnCtrl->chnErrTypeSet = FccuReg_GetTypeAlarm(obj->regFccu); diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/flash/flash_drv.c b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/flash/flash_drv.c index 5677430..1f1b1fb 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/flash/flash_drv.c +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/flash/flash_drv.c @@ -56,7 +56,7 @@ void FlashDrv_Init(FlashDrvType *obj, struct _FtfcRegType_ *reg) } else { - obj->dflashsize = FEATURE_DFLASH_SIZE + 0x20000; /* No extra dflash occupied if EEPROM not available */ + obj->dflashsize = FEATURE_DFLASH_SIZE + 0x20000; /* No extra dflash occupied if EEEPROM not available */ } } @@ -78,7 +78,7 @@ void FlashDrv_GetDefaultConfig(FlashDrv_ConfigType *userconfig) userconfig->pflashbase = 0x0; userconfig->pflashsize = FEATURE_PFLASH_SIZE; userconfig->dflashbase = 0x10020000 - FEATURE_DFLASH_SIZE; - userconfig->dflashsize = FEATURE_DFLASH_SIZE + 0x20000; /* No extra dflash occupied if EEPROM not available */ + userconfig->dflashsize = FEATURE_DFLASH_SIZE + 0x20000; /* No extra dflash occupied if EEEPROM not available */ } void FlashDrv_Configure(FlashDrvType *obj, @@ -284,7 +284,7 @@ FlashDrv_Status FlashDrv_CheckEccState(FlashDrvType *obj, uint32_t *destaddr) FtfcReg_SetFccob(obj->reg, 5 + i, 0xFF); } FlashDrv_CommandSequence(obj); - ret = (FtfcReg_GetFstatFtfcDedF(obj->reg) == 1) ? FLASHDRV_STATUS_ERROR : FLASHDRV_STATUS_SUCCESS; + ret = ((FtfcReg_GetFstatFtfcSecF(obj->reg) | FtfcReg_GetFstatFtfcDedF(obj->reg)) == 1) ? FLASHDRV_STATUS_ERROR : FLASHDRV_STATUS_SUCCESS; } } return ret; @@ -301,7 +301,7 @@ FlashDrv_Status FlashDrv_ProgramPhrase(FlashDrvType *obj, uint32_t *destaddr, ui ret = FLASHDRV_STATUS_ERROR; } - if((dest >= obj->pflashbase && dest < obj->dflashbase) || (dest >= (obj->dflashbase + obj->dflashsize))) + if((dest >= (obj->pflashbase + obj->pflashsize) && dest < obj->dflashbase) || (dest >= (obj->dflashbase + obj->dflashsize))) { ret = FLASHDRV_STATUS_ERROR; } @@ -416,7 +416,7 @@ FlashDrv_Status FlashDrv_ProgramSection(FlashDrvType *obj, uint32_t *destaddr, u FlashDrv_Status ret = FLASHDRV_STATUS_SUCCESS; uint32_t dest = (uint32_t)destaddr; uint32_t sctsz = 1024, i = 0, offset = 0; - bool eeramrdy = false; + bool eeeramrdy = false; uint8_t *pfastram, *pdata; if(!IS_ALIGNED(dest, 256) || !IS_ALIGNED(len, 256)) @@ -442,9 +442,9 @@ FlashDrv_Status FlashDrv_ProgramSection(FlashDrvType *obj, uint32_t *destaddr, u ret = FLASHDRV_STATUS_ERROR; } - eeramrdy = (FtfcReg_GetFstatEeeRamRdy(obj->reg) == 1); + eeeramrdy = (FtfcReg_GetFstatEeeRamRdy(obj->reg) == 1); - if(eeramrdy) + if(eeeramrdy) { FlashDrv_SetFlexRam(obj, false); } @@ -478,7 +478,7 @@ FlashDrv_Status FlashDrv_ProgramSection(FlashDrvType *obj, uint32_t *destaddr, u ret = FlashDrv_CommandSequence(obj); } } - if(eeramrdy) + if(eeeramrdy) { FlashDrv_SetFlexRam(obj, true); } @@ -491,7 +491,7 @@ FlashDrv_Status FlashDrv_ProgramSectionFast(FlashDrvType *obj, uint32_t *destadd FlashDrv_Status ret = FLASHDRV_STATUS_SUCCESS; uint32_t dest = (uint32_t)destaddr; uint32_t sctsz = 1024; - bool eeramrdy = false; + bool eeeramrdy = false; if(!IS_ALIGNED(dest, 256) || !IS_ALIGNED(len, 256)) { @@ -516,9 +516,9 @@ FlashDrv_Status FlashDrv_ProgramSectionFast(FlashDrvType *obj, uint32_t *destadd ret = FLASHDRV_STATUS_ERROR; } - eeramrdy = (FtfcReg_GetFstatEeeRamRdy(obj->reg) == 1); + eeeramrdy = (FtfcReg_GetFstatEeeRamRdy(obj->reg) == 1); - if(eeramrdy) + if(eeeramrdy) { FlashDrv_SetFlexRam(obj, false); } @@ -542,7 +542,7 @@ FlashDrv_Status FlashDrv_ProgramSectionFast(FlashDrvType *obj, uint32_t *destadd ret = FlashDrv_CommandSequence(obj); } } - if(eeramrdy) + if(eeeramrdy) { FlashDrv_SetFlexRam(obj, true); } @@ -825,7 +825,7 @@ void FlashDrv_SetCmdDoneIrqEn(FlashDrvType *obj, bool en) FtfcReg_SetFcnfgCcifIE(obj->reg, en ? 1 : 0); } -FlashDrv_Status FlashDrv_SetFlexRam(FlashDrvType *obj, bool eeramen) +FlashDrv_Status FlashDrv_SetFlexRam(FlashDrvType *obj, bool eeeramen) { FlashDrv_Status ret = FLASHDRV_STATUS_SUCCESS; @@ -837,15 +837,15 @@ FlashDrv_Status FlashDrv_SetFlexRam(FlashDrvType *obj, bool eeramen) { FlashDrv_ClearCommandState(obj); FtfcReg_SetFccob(obj->reg, 0, FLASHDRV_OPCMD_SETFRAM); - FtfcReg_SetFccob(obj->reg, 1, eeramen ? 1 : 0); + FtfcReg_SetFccob(obj->reg, 1, eeeramen ? 1 : 0); ret = FlashDrv_CommandSequence(obj); - if(eeramen && !FtfcReg_GetFstatEeeRamRdy(obj->reg)) + if(eeeramen && !FtfcReg_GetFstatEeeRamRdy(obj->reg)) { ret |= FLASHDRV_STATUS_ERROR; } - if(!eeramen && !FtfcReg_GetFstatRamRdy(obj->reg)) + if(!eeeramen && !FtfcReg_GetFstatRamRdy(obj->reg)) { ret |= FLASHDRV_STATUS_ERROR; } @@ -858,12 +858,12 @@ FlashDrv_Status FlashDrv_UpdateEeeRam(FlashDrvType *obj, uint32_t offset, uint8_ { FlashDrv_Status ret = FLASHDRV_STATUS_SUCCESS; - uint8_t *p_dst_eram8 = 0; - uint16_t *p_dst_eram16 = 0; - uint32_t *p_dst_eram32 = 0; - uint8_t *p_src8 = 0; - uint16_t *p_src16 = 0; - uint32_t *p_src32 = 0; + uint8_t *pdsteram8 = 0; + uint16_t *pdsteram16 = 0; + uint32_t *pdsteram32 = 0; + uint8_t *psrc8 = 0; + uint16_t *psrc16 = 0; + uint32_t *psrc32 = 0; uint32_t i = 0, cnt = 0; if(!(obj->eeevld) || FtfcReg_GetFstatRamRdy(obj->reg) == 1 || FtfcReg_GetFstatEeeFlov(obj->reg) == 1 || FtfcReg_GetEfProtecion(obj->reg) != 0x0) @@ -885,16 +885,16 @@ FlashDrv_Status FlashDrv_UpdateEeeRam(FlashDrvType *obj, uint32_t offset, uint8_ { FtfcReg_SetFcnfgAutoGc(obj->reg, 1); } - p_dst_eram8 = (uint8_t *)(FLASHDRV_FLEXRAM_ADDR + offset); + pdsteram8 = (uint8_t *)(FLASHDRV_FLEXRAM_ADDR + offset); if(IS_ALIGNED(offset, (uint32_t)4) && IS_ALIGNED(sz, (uint32_t)4)) { - p_dst_eram32 = (uint32_t *)p_dst_eram8; - p_src32 = (uint32_t *)srcdata; + pdsteram32 = (uint32_t *)pdsteram8; + psrc32 = (uint32_t *)srcdata; cnt = sz / 4; for(i = 0; i < cnt; i++) { - p_dst_eram32[i] = p_src32[i]; + pdsteram32[i] = psrc32[i]; while(0 == FtfcReg_GetFstatEeeRamRdy(obj->reg)) { } @@ -902,12 +902,12 @@ FlashDrv_Status FlashDrv_UpdateEeeRam(FlashDrvType *obj, uint32_t offset, uint8_ } else if(IS_ALIGNED(offset, (uint32_t)2) && IS_ALIGNED(sz, (uint32_t)2)) { - p_dst_eram16 = (uint16_t *)p_dst_eram8; - p_src16 = (uint16_t *)srcdata; + pdsteram16 = (uint16_t *)pdsteram8; + psrc16 = (uint16_t *)srcdata; cnt = sz / 2; for(i = 0; i < cnt; i++) { - p_dst_eram16[i] = p_src16[i]; + pdsteram16[i] = psrc16[i]; while(0 == FtfcReg_GetFstatEeeRamRdy(obj->reg)) { } @@ -915,11 +915,11 @@ FlashDrv_Status FlashDrv_UpdateEeeRam(FlashDrvType *obj, uint32_t offset, uint8_ } else { - p_src8 = (uint8_t *)srcdata; + psrc8 = (uint8_t *)srcdata; cnt = sz; for(i = 0; i < cnt; i++) { - p_dst_eram8[i] = p_src8[i]; + pdsteram8[i] = psrc8[i]; while(0 == FtfcReg_GetFstatEeeRamRdy(obj->reg)) { } diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/flash/flash_drv.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/flash/flash_drv.h index ac86922..b57cdbb 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/flash/flash_drv.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/flash/flash_drv.h @@ -253,7 +253,7 @@ extern FlashDrv_Status FlashDrv_Read1sBlock(FlashDrvType *obj, * or should be a total sector. Both the start addr and the size of the section * are supposed to be 8-aligned. * - * NOTE:if the target section is in EEE backup region, the read1s sequence will be aborted. + * NOTE:if the target section is in eee backup region, the read1s sequence will be aborted. * * \param[in] obj : pointer to Flash driver instance * \param[in] destaddr : pointer to a memory address in pflash or dflash:8-aligned. @@ -268,7 +268,7 @@ extern FlashDrv_Status FlashDrv_Read1sSection(FlashDrvType *obj, * This function checked a phrase-data[8bytes] progrmmed as expected value. * The phrase addr is supposed to be 8-aligned. * - * NOTE:if the target phrae is in EEE backup region, the check sequence will be aborted. + * NOTE:if the target phrae is in eee backup region, the check sequence will be aborted. * * \param[in] obj : pointer to Flash driver instance. * \param[in] destaddr : pointer to a memory address in pflash or dflash,8-aligned. @@ -295,7 +295,7 @@ extern FlashDrv_Status FlashDrv_CheckEccState(FlashDrvType *obj, * value. The phrase addr is supposed to be 8-aligned. * * NOTE: 1.make sure targeted phrase is erased and not proteted before - * programmed; 2.if the target phrase is in pflash or EEE backup region, the check sequence will be aborted. + * programmed; 2.if the target phrase is in eee backup region, the check sequence will be aborted. * * \param[in] obj : pointer to Flash driver instance. * \param[in] destaddr : pointer to a memory address in dflash,8-aligned. @@ -370,7 +370,7 @@ extern FlashDrv_Status FlashDrv_ProgramSection(FlashDrvType *obj, * supposed to be 256-aligned. The programmed data is supposed to be prepared already in the flexram. * * NOTE: 1.make sure targeted section is erased and not proteted before -* programmed; 2.if the target section is in EEE backup region, +* programmed; 2.if the target section is in eee backup region, * the program sequence will be aborted.3.the programmed data has been placed in the flexram with * correct offset(offset = dest & (FLASHDRV_SECTOR_SIZE - 1)) while ram ready. * @@ -510,24 +510,24 @@ extern void FlashDrv_IRQHandler(FlashDrvType *obj); */ extern void FlashDrv_SetCmdDoneIrqEn(FlashDrvType *obj, bool en); -/*! \brief sets the flexram as emulated ee-ram or system-ram. +/*! \brief sets the flexram as eee-ram or system-ram. * * \param[in] obj : pointer to Flash driver instance. - * \param[in] eeramen : control emulated ee_ram enabled or disabled, - * --if emulated ee_ram enabled, UpdateEeRam will take effect; - * --if emulated ee_ram disabled, the flex_ram will be used as system ram + * \param[in] eeeramen : control eee_ram enabled or disabled, + * --if eee_ram enabled, UpdateEeRam will take effect; + * --if eee_ram disabled, the flex_ram will be used as system ram */ -extern FlashDrv_Status FlashDrv_SetFlexRam(FlashDrvType *obj, bool eeramen); +extern FlashDrv_Status FlashDrv_SetFlexRam(FlashDrvType *obj, bool eeeramen); -/*! \brief updates ee_ram with expected data +/*! \brief updates eee_ram with expected data * *NOTE: 1.makesure the auto_gc(SCG0_Inst:TRIM_AUTO_GC_EN) enabled before this function called to * avoid data overflowing and lost - * 2.makesure the emulated ee-ram is enabled otherwise the new data will be lost + * 2.makesure the eee-ram is enabled otherwise the new data will be lost * * \param[in] obj : pointer to Flash driver instance. - * \param[in] offset : indicates the targeted position in the emulated ee-ram, range is [0 ~ 4096] - * \param[in] srcdata : pointer to srcdata which will be wrote intoemulated ee-ram + * \param[in] offset : indicates the targeted position in the eee-ram, range is [0 ~ 4096] + * \param[in] srcdata : pointer to srcdata which will be wrote into eee-ram * \param[in] sz: len of srcdata in byte */ extern FlashDrv_Status FlashDrv_UpdateEeeRam(FlashDrvType *obj, uint32_t offset, uint8_t *srcdata, uint32_t sz); @@ -554,25 +554,25 @@ extern bool FlashDrv_GetEeeAutoGcEn(FlashDrvType *obj); */ extern void FlashDrv_SetEeeAutoGcEn(FlashDrvType *obj, bool eeegcen); -/*! \brief Get Eee enable state +/*! \brief Get eee enable state * - * This function gets the Eee enable state + * This function gets the eee enable state * * \param[in] obj : pointer to Flash driver instance - * \return Eee enable state - * - false : Eee not enabled in Eeprom Cfg field.If EEE enable expected, progroram InfoRegion with correct data and then POR - * - true : Eee enabled in Eeprom Cfg field + * \return eee enable state + * - false : eee not enabled in eeeprom Cfg field.If EEE enable expected, progroram InfoRegion with correct data and then POR + * - true : eee enabled in eeeprom Cfg field */ extern bool FlashDrv_GetEeeEn(FlashDrvType *obj); -/*! \brief Get Eee_ram ready state +/*! \brief Get eee_ram ready state * - * This function gets the Eeerst enable state + * This function gets the eeerst enable state * * \param[in] obj : pointer to Flash driver instance - * \return Eee_ram ready state - * - false : Eee_ram not ready. - * - true : Eee_ram ready. + * \return eee_ram ready state + * - false : eee_ram not ready. + * - true : eee_ram ready. */ extern bool FlashDrv_GetEeeRamRdy(FlashDrvType *obj); diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/flexcan/flexcan_drv.c b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/flexcan/flexcan_drv.c index 7f36a6b..58ccb0e 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/flexcan/flexcan_drv.c +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/flexcan/flexcan_drv.c @@ -88,7 +88,7 @@ static inline uint32_t FlexCanDrv_GetMsgBufStartAddr(FlexCanDrvType *obj, uint16 } else if(msgBufSizeSel == FLEXCANDRV_MB_SIZE_BYTE_32) { - addr += (msgBufSize * msgBufId + (4 * (msgBufId / 12))) * 4; + addr += (msgBufSize * msgBufId + (8 * (msgBufId / 12))) * 4; } else { @@ -528,7 +528,10 @@ static bool FlexCanDrv_SetEnhanceRxFifoFilterInMask(FlexCanDrvType *obj, const F } else { - nfe = nexif - 1u; + if(extIdNum > 0u) + { + nfe = nexif - 1u; + } } FlexCanReg_SetEnhanceRxFifoFilterElementNum(obj->flexCanReg, nfe); @@ -610,7 +613,6 @@ static bool FlexCanDrv_SetEnhanceRxFifoFilterInMask(FlexCanDrvType *obj, const F { /* use the last filter value to fill the space for aligning with two element as one group */ FlexCanReg_SetEnhanceRxFifoElement(obj->flexCanReg, filterElementIdx, filter); - filterElementIdx++; } break; @@ -667,7 +669,10 @@ static bool FlexCanDrv_SetEnhanceRxFifoFilterInRange(FlexCanDrvType *obj, const } else { - nfe = nexif - 1u; + if(extIdNum > 0u) + { + nfe = nexif - 1u; + } } FlexCanReg_SetEnhanceRxFifoFilterElementNum(obj->flexCanReg, nfe); @@ -829,13 +834,11 @@ static bool FlexCanDrv_SetEnhanceRxFifoFilterInRange(FlexCanDrvType *obj, const filterMin |= (0x00ul << 27); filterMin |= (controllerCfg->msgCfg[lastValidRxIdIndex].msgId << 16); FlexCanReg_SetEnhanceRxFifoElement(obj->flexCanReg, filterElementIdx, filterMin); - filterElementIdx++; break; case 0x02: /* Use the last element filter value to fill */ FlexCanReg_SetEnhanceRxFifoElement(obj->flexCanReg, filterElementIdx, filterMin); - filterElementIdx++; break; case 0x03: @@ -845,7 +848,6 @@ static bool FlexCanDrv_SetEnhanceRxFifoFilterInRange(FlexCanDrvType *obj, const /* Use the last element filter value to fill */ FlexCanReg_SetEnhanceRxFifoElement(obj->flexCanReg, filterElementIdx, filterMin); - filterElementIdx++; break; default: @@ -899,7 +901,10 @@ static bool FlexCanDrv_SetEnhanceRxFifoFilterInWithoutMask(FlexCanDrvType *obj, } else { - nfe = nexif - 1u; + if(extIdNum > 0u) + { + nfe = nexif - 1u; + } } FlexCanReg_SetEnhanceRxFifoFilterElementNum(obj->flexCanReg, nfe); @@ -1016,13 +1021,11 @@ static bool FlexCanDrv_SetEnhanceRxFifoFilterInWithoutMask(FlexCanDrvType *obj, filter |= (0x00ul << 27); FlexCanReg_SetEnhanceRxFifoElement(obj->flexCanReg, filterElementIdx, filter); - filterElementIdx++; break; case 0x02: /* Use the last element filter value to fill */ FlexCanReg_SetEnhanceRxFifoElement(obj->flexCanReg, filterElementIdx, filter); - filterElementIdx++; break; case 0x03: @@ -1035,7 +1038,6 @@ static bool FlexCanDrv_SetEnhanceRxFifoFilterInWithoutMask(FlexCanDrvType *obj, /* Use the last element filter value to fill */ FlexCanReg_SetEnhanceRxFifoElement(obj->flexCanReg, filterElementIdx, filter); - filterElementIdx++; break; default: @@ -1140,6 +1142,12 @@ void FlexCanDrv_Configure(FlexCanDrvType *obj, const FlexCanDrv_ControllerCfgTyp /* disable FlexCan module */ FlexCanReg_SetModuleDisable(obj->flexCanReg, true); + /* make sure that the module has enter into low power mode successfully */ + while(FlexCanReg_GetLowPowerAck(obj->flexCanReg) == 0) + { + + } + /* configure FlexCan clock source */ FlexCanReg_SetClockSource(obj->flexCanReg, controllerCfg->clkSrc); @@ -1309,8 +1317,6 @@ void FlexCanDrv_Configure(FlexCanDrvType *obj, const FlexCanDrv_ControllerCfgTyp FlexCanReg_SetSelfWakeupEnable(obj->flexCanReg, 1U); /* enable edge(self) wakeup interrupt */ FlexCanReg_SetWakeupIntMask(obj->flexCanReg, 1U); - /* enable doze mode request */ - FlexCanReg_SetDozeMode(obj->flexCanReg, 1U); } else { @@ -1318,8 +1324,6 @@ void FlexCanDrv_Configure(FlexCanDrvType *obj, const FlexCanDrv_ControllerCfgTyp FlexCanReg_SetSelfWakeupEnable(obj->flexCanReg, 0U); /* disable edge(self) wakeup interrupt */ FlexCanReg_SetWakeupIntMask(obj->flexCanReg, 0U); - /* disable doze mode request */ - FlexCanReg_SetDozeMode(obj->flexCanReg, 0U); } /* BusOff recovery */ @@ -1867,7 +1871,7 @@ void FlexCanDrv_BitTimingCalc(FlexCanDrv_BitTimingType *bitTimingPara, const float optSamplePntToler = 0.25; /* set the maximum & minimum value for all bit timing parameters */ - if(isFd) + if(isFd == false) { maxPrescaler = FLEXCAN_CBT_EPRESDIV_MASK >> FLEXCAN_CBT_EPRESDIV_SHIFT; maxTseg1 = (FLEXCAN_CBT_EPROPSEG_MASK >> FLEXCAN_CBT_EPROPSEG_SHIFT) + (FLEXCAN_CBT_EPSEG1_MASK >> FLEXCAN_CBT_EPSEG1_SHIFT); diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/pins/pins_drv.c b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/pins/pins_drv.c index 06c2613..eb36205 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/pins/pins_drv.c +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/pins/pins_drv.c @@ -73,11 +73,10 @@ void PinsDrv_SetPullSel(PinsDrvType *obj, uint32_t pin, PinsDrv_InternalPullMode void PinsDrv_SetMuxModeSel(PinsDrvType *obj, uint32_t pin, PinsDrv_MuxType mux) { - PortReg_SetPcrMux(obj->port, pin, mux); - /* analog feature */ if(mux == PINSDRV_PIN_DISABLED) { + PortReg_SetPcrMux(obj->port, pin, mux); /* Analog pin, need enable analog feature */ PortReg_SetPcrAen(obj->port, pin, 1); } @@ -85,6 +84,7 @@ void PinsDrv_SetMuxModeSel(PinsDrvType *obj, uint32_t pin, PinsDrv_MuxType mux) { /* Other functions, must disable analog feature */ PortReg_SetPcrAen(obj->port, pin, 0); + PortReg_SetPcrMux(obj->port, pin, mux); } } diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/pwmlite/pwmlite_drv.c b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/pwmlite/pwmlite_drv.c index 77b45d7..e7a9992 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/pwmlite/pwmlite_drv.c +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/pwmlite/pwmlite_drv.c @@ -52,18 +52,32 @@ const setPwmLiteMuxFunc c_pwmLiteMuxFuncTable[PWMLITEDRV_MUX_PAD_PWM_NUM] = { SimReg_SetPwmCtrl1PwmFunc7, }; +const PwmLiteDrv_PwmMuxPadNumType c_pwmLiteMuxPadIndex[] = { + PWMLITEDRV_MUX_PAD_PWM0, + PWMLITEDRV_MUX_PAD_PWM1, + PWMLITEDRV_MUX_PAD_PWM2, + PWMLITEDRV_MUX_PAD_PWM3, + PWMLITEDRV_MUX_PAD_PWM4, + PWMLITEDRV_MUX_PAD_PWM5, + PWMLITEDRV_MUX_PAD_PWM6, + PWMLITEDRV_MUX_PAD_PWM7, +}; +#define PWMLITE_PWMMUXINDEX_MAX (sizeof(c_pwmLiteMuxPadIndex) / sizeof(PwmLiteDrv_PwmMuxPadNumType)) + /******************************************************************************* * the function prototypes ******************************************************************************/ void PwmLiteDrv_Init(PwmLiteDrvType *obj, struct _PwmLiteRegType_ *pwmLiteReg, struct _SimRegType_ *simReg) { + uint16_t i; + obj->pwmLiteReg = pwmLiteReg; obj->simReg = simReg; /* disable the mux pwm output */ - for(PwmLiteDrv_PwmMuxPadNumType padNum = (PwmLiteDrv_PwmMuxPadNumType)0; padNum < PWMLITEDRV_MUX_PAD_PWM_NUM; padNum++) + for(i = 0; i < PWMLITE_PWMMUXINDEX_MAX; i++) { - PwmLiteDrv_OutputMux(obj, PWMLITEDRV_MUX_PWM_CH_INVALID, padNum); + PwmLiteDrv_OutputMux(obj, PWMLITEDRV_MUX_PWM_CH_INVALID, c_pwmLiteMuxPadIndex[i]); } } @@ -85,14 +99,16 @@ void PwmLiteDrv_GetDefaultModuleConfig(PwmLiteDrv_ModuleConfigType *ModuleConfig void PwmLiteDrv_ConfigChannel(PwmLiteDrvType *obj, uint8_t channel, const PwmLiteDrv_ChannelConfigType *userConfig) { + if(channel >= PWMLITEDRV_PWM_CH_NUM) + { + return; + } /* disable the module first */ PwmLiteDrv_DisableModule(obj); /* Set the pwm channels to target pad channel through SIM */ PwmLiteDrv_OutputMux(obj, userConfig->pwmMuxType.channelNumber, userConfig->pwmMuxType.padNumber); - /* Set pwm threshold0 value */ - PwmLiteReg_SetChThr0(obj->pwmLiteReg, channel, userConfig->threshold0); - /* Set pwm threshold1 value */ - PwmLiteReg_SetChThr1(obj->pwmLiteReg, channel, userConfig->threshold1); + /* Set pwm threshold0/1 value */ + PwmLiteDrv_UpdatePwmThresholdAtRunning(obj, channel, userConfig->threshold0, userConfig->threshold1); /* Set pwm threshold0 behavior */ PwmLiteReg_SetChCtrl0(obj->pwmLiteReg, channel, userConfig->behavior0); /* Set pwm threshold1 behavior */ @@ -129,18 +145,54 @@ void PwmLiteDrv_Pause(PwmLiteDrvType *obj) void PwmLiteDrv_UpdatePwmThresholdAtRunning(PwmLiteDrvType *obj, uint8_t channel, uint32_t threshold0, uint32_t threshold1) { - /* Set pwm threshold0 value */ - PwmLiteReg_SetChThr0(obj->pwmLiteReg, channel, threshold0); - /* Set pwm threshold1 value */ - PwmLiteReg_SetChThr1(obj->pwmLiteReg, channel, threshold1); + uint32_t prd = PwmLiteReg_GetPrdPeriod(obj->pwmLiteReg); + if(threshold1 == threshold0) /* DUTY: 0% */ + { + /* Set pwm threshold0 value */ + PwmLiteReg_SetChThr0(obj->pwmLiteReg, channel, (prd + 0x1u)); + /* Set pwm threshold1 value */ + PwmLiteReg_SetChThr1(obj->pwmLiteReg, channel, 0x0u); + } + else if(threshold1 - threshold0 == prd) /* DUTY: 100% */ + { + /* Set pwm threshold0 value */ + PwmLiteReg_SetChThr0(obj->pwmLiteReg, channel, 0x0u); + /* Set pwm threshold1 value */ + PwmLiteReg_SetChThr1(obj->pwmLiteReg, channel, (prd + 0x1u)); + } + else /* DUTY: 0~100% */ + { + /* Set pwm threshold0 value */ + PwmLiteReg_SetChThr0(obj->pwmLiteReg, channel, threshold0); + /* Set pwm threshold1 value */ + PwmLiteReg_SetChThr1(obj->pwmLiteReg, channel, threshold1); + } } void PwmLiteDrv_UpdatePwmThresholdAtSync(PwmLiteDrvType *obj, uint8_t channel, uint32_t threshold0, uint32_t threshold1) { - /* Set pwm threshold0 value */ - PwmLiteReg_SetChThr0(obj->pwmLiteReg, channel, threshold0); - /* Set pwm threshold1 value */ - PwmLiteReg_SetChThr1(obj->pwmLiteReg, channel, threshold1); + uint32_t prd = PwmLiteReg_GetPrdPeriod(obj->pwmLiteReg); + if(threshold1 == threshold0) /* DUTY: 0% */ + { + /* Set pwm threshold0 value */ + PwmLiteReg_SetChThr0(obj->pwmLiteReg, channel, (prd + 0x1u)); + /* Set pwm threshold1 value */ + PwmLiteReg_SetChThr1(obj->pwmLiteReg, channel, 0x0u); + } + else if(threshold1 - threshold0 == prd) /* DUTY: 100% */ + { + /* Set pwm threshold0 value */ + PwmLiteReg_SetChThr0(obj->pwmLiteReg, channel, 0x0u); + /* Set pwm threshold1 value */ + PwmLiteReg_SetChThr1(obj->pwmLiteReg, channel, (prd + 0x1u)); + } + else /* DUTY: 0~100% */ + { + /* Set pwm threshold0 value */ + PwmLiteReg_SetChThr0(obj->pwmLiteReg, channel, threshold0); + /* Set pwm threshold1 value */ + PwmLiteReg_SetChThr1(obj->pwmLiteReg, channel, threshold1); + } PwmLiteDrv_TrigSync(obj); } diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/spi/spi_drv.c b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/spi/spi_drv.c index 69bf29e..df2be79 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/spi/spi_drv.c +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/spi/spi_drv.c @@ -625,7 +625,7 @@ bool SpiDrv_MasterSyncTransfer(SpiDrvType *obj, SpiDrv_FrameSizeBitType frameSiz tTxFreeNums = SPIDRV_TX_FIFO_SIZE - SpiReg_GetTxFifoCounter(obj->reg); - if(tTxFreeNums > txFrameNums) + if(tTxFreeNums >= txFrameNums) { uint32_t tTcr = 0, tTimeout = 0; uint16_t x = 0; @@ -1312,6 +1312,7 @@ bool SpiDrv_AsyncBitDataWriteIntoHwTxBuffer(SpiDrvType *obj, uint16_t txBitNums, obj->reg->TDR = tDataAligned.wordData; tRestBitNums -= 32u; tBufferIdx += 4u; + while(SpiDrv_GetStatus(obj, SPIDRV_STATUS_TX_DATA) == false); } else if(tRestBitNums >= (SPIDRV_FRAME_SIZE_HALF_WORD + 1u)) { @@ -1375,6 +1376,7 @@ bool SpiDrv_AsyncBitDataWriteIntoHwTxBuffer(SpiDrvType *obj, uint16_t txBitNums, tRestBitNums = 0u; obj->reg->TDR = tDataAligned.wordData; + while(SpiDrv_GetStatus(obj, SPIDRV_STATUS_TX_DATA) == false); } else if(tRestBitNums >= (SPIDRV_FRAME_SIZE_BYTE + 1u)) { @@ -1405,12 +1407,14 @@ bool SpiDrv_AsyncBitDataWriteIntoHwTxBuffer(SpiDrvType *obj, uint16_t txBitNums, obj->reg->TDR = tDataAligned.wordData; tRestBitNums = 0u; tBufferIdx += 1u; + while(SpiDrv_GetStatus(obj, SPIDRV_STATUS_TX_DATA) == false); } else { obj->reg->TDR = (((uint8_t *)pTxBuffer)[tBufferIdx]); tRestBitNums = 0; tBufferIdx++; + while(SpiDrv_GetStatus(obj, SPIDRV_STATUS_TX_DATA) == false); } timeOutCnt = 0; diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/uart/uart_drv.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/uart/uart_drv.h index 37fd490..047a9df 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/uart/uart_drv.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/uart/uart_drv.h @@ -356,13 +356,13 @@ extern uint8_t UartDrv_GetTxCounter(const UartDrvType *obj); */ extern void UartDrv_ClearTxFifo(const UartDrvType *obj); -/*! \brief clear all data of Tx FIFO +/*! \brief clear all data of Rx FIFO * - * This function clears all data of Tx FIFO + * This function clears all data of Rx FIFO * * \param[in] obj : pointer to UART driver instance */ -extern void UartDrv_ClearTxFifo(const UartDrvType *obj); +extern void UartDrv_ClearRxFifo(const UartDrvType *obj); /*! \brief Set the threshold value of Rx FIFO * diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/adc_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/adc_reg.h index e1a4470..dada684 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/adc_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/adc_reg.h @@ -526,42 +526,26 @@ __attribute__((always_inline)) static inline uint8_t AdcReg_GetSc2AdAct(const Ad return ((obj->SC2 & ADC_SC2_ADACT_MASK) >> ADC_SC2_ADACT_SHIFT); } -/*! \brief Gets the Conversion Trigger Select +/*! \brief Gets the Conversion Trigger state * - * This function gets the current Conversion Trigger Select. - * Selects the type of trigger used for initiating a conversion. Two types of - * triggers can be selected: - * - Software trigger: When software trigger is selected, a conversion is - * initiated following a write to SC00. - * - Hardware trigger: When hardware trigger is selected, a conversion is - * initiated following the assertion of the ADHWT input after a pulse of the - * ADHWTSn input. + * This function gets the current Conversion Trigger state. * * \param[in] obj : pointer to ADC register instance * \return Conversion Trigger Select - * - 0b : Software trigger selected. - * - 1b : Hardware trigger selected. + * - 0b : trigger disable. + * - 1b : trigger enable. */ __attribute__((always_inline)) static inline uint8_t AdcReg_GetSc2AdTrg(const AdcRegType *obj) { return ((obj->SC2 & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT); } -/*! \brief Sets the Conversion Trigger Select - * - * This function sets the Conversion Trigger Select. - * Selects the type of trigger used for initiating a conversion. Two types of - * triggers can be selected: - * - Software trigger: When software trigger is selected, a conversion is - * initiated following a write to SC00. - * - Hardware trigger: When hardware trigger is selected, a conversion is - * initiated following the assertion of the ADHWT input after a pulse of the - * ADHWTSn input. +/*! \brief Sets the Conversion Trigger state * * \param[in] obj : pointer to ADC register instance - * \param[in] value : the value of Conversion Trigger Select - * - 0b : Software trigger selected. - * - 1b : Hardware trigger selected. + * \param[in] value : the value of Conversion Trigger state select + * - 0b : trigger disable. + * - 1b : trigger enable. */ __attribute__((always_inline)) static inline void AdcReg_SetSc2AdTrg(AdcRegType *obj, uint8_t value) { @@ -1345,31 +1329,37 @@ __attribute__((always_inline)) static inline void AdcReg_SetScAIEn(AdcRegType *o * \param[in] obj : pointer to ADC register instance * \param[in] channel : the channel number * \return Input channel select - * - 0x0 : External channel 0 is selected as ADC input - * - 0x1 : External channel 1 is selected as ADC input - * - 0x2 : External channel 2 is selected as ADC input - * - 0x3 : External channel 3 is selected as ADC input - * - 0x4 : External channel 4 is selected as ADC input - * - 0x5 : External channel 5 is selected as ADC input - * - 0x6 : External channel 6 is selected as ADC input - * - 0x7 : External channel 7 is selected as ADC input - * - 0x8 : External channel 8 is selected as ADC input - * - 0x9 : External channel 9 is selected as ADC input - * - 0xA : External channel 10 is selected as ADC input - * - 0xB : External channel 11 is selected as ADC input - * - 0xC : External channel 12 is selected as ADC input - * - 0xD : External channel 13 is selected as ADC input - * - 0xE : External channel 14 is selected as ADC input - * - 0xF : External channel 15 is selected as ADC input - * - 0x10 : VBUF_TSEN_LPVBG - * - 0x11 : VBUF_TSEN_LPVBG - * - 0x12 : VBG - * - 0x13 : monitor ldo output - * - 0x14 : monitor supply voltage(0.5*supply_voltage) - * - 0x15 : AVSS - * - 0x16 : AVSS - * - 0x17 : Self Test Voltage - * - 0x18 ~ 0x1E : Reserved + * - 0x00 : External channel 0 is selected as ADC input + * - 0x01 : External channel 1 is selected as ADC input + * - 0x02 : External channel 2 is selected as ADC input + * - 0x03 : External channel 3 is selected as ADC input + * - 0x04 : External channel 4 is selected as ADC input + * - 0x05 : External channel 5 is selected as ADC input + * - 0x06 : External channel 6 is selected as ADC input + * - 0x07 : External channel 7 is selected as ADC input + * - 0x08 : External channel 8 is selected as ADC input + * - 0x09 : External channel 9 is selected as ADC input + * - 0x0A : External channel 10 is selected as ADC input + * - 0x0B : External channel 11 is selected as ADC input + * - 0x0C : External channel 12 is selected as ADC input + * - 0x0D : External channel 13 is selected as ADC input + * - 0x0E : External channel 14 is selected as ADC input + * - 0x0F : External channel 15 is selected as ADC input + * - 0x10 : External channel 16 is selected as ADC input + * - 0x11 : External channel 17 is selected as ADC input + * - 0x12 : External channel 18 is selected as ADC input + * - 0x13 : External channel 19 is selected as ADC input + * - 0x14 : External channel 20 is selected as ADC input + * - 0x15 : External channel 21 is selected as ADC input + * - 0x16 : External channel 22 is selected as ADC input + * - 0x17 : External channel 23 is selected as ADC input + * - 0x18 : Reserved + * - 0x19 : LPVBG + * - 0x1A : VBG + * - 0x1B : monitor ldo output + * - 0x1C : Reserved + * - 0x1D : Self Test Voltage + * - 0x1E : Reserved * - 0x1F : Module is disabled */ __attribute__((always_inline)) static inline uint8_t AdcReg_GetScAdCh(const AdcRegType *obj, uint8_t channel) @@ -1393,32 +1383,38 @@ __attribute__((always_inline)) static inline uint8_t AdcReg_GetScAdCh(const AdcR * \param[in] obj : pointer to ADC register instance * \param[in] channel : the channel number * \param[in] value : the value of Input channel select - * - 0x0 : External channel 0 is selected as ADC input - * - 0x1 : External channel 1 is selected as ADC input - * - 0x2 : External channel 2 is selected as ADC input - * - 0x3 : External channel 3 is selected as ADC input - * - 0x4 : External channel 4 is selected as ADC input - * - 0x5 : External channel 5 is selected as ADC input - * - 0x6 : External channel 6 is selected as ADC input - * - 0x7 : External channel 7 is selected as ADC input - * - 0x8 : External channel 8 is selected as ADC input - * - 0x9 : External channel 9 is selected as ADC input - * - 0xA : External channel 10 is selected as ADC input - * - 0xB : External channel 11 is selected as ADC input - * - 0xC : External channel 12 is selected as ADC input - * - 0xD : External channel 13 is selected as ADC input - * - 0xE : External channel 14 is selected as ADC input - * - 0xF : External channel 15 is selected as ADC input - * - 0x10 : VBUF_TSEN_LPVBG - * - 0x11 : VBUF_TSEN_LPVBG - * - 0x12 : VBG - * - 0x13 : monitor ldo output - * - 0x14 : monitor supply voltage(0.5*supply_voltage) - * - 0x15 : AVSS - * - 0x16 : AVSS - * - 0x17 : Self Test Voltage - * - 0x18 ~ 0x1E : Reserved - * - 0x1F : Module is disabled + * - 0x00 : External channel 0 is selected as ADC input + * - 0x01 : External channel 1 is selected as ADC input + * - 0x02 : External channel 2 is selected as ADC input + * - 0x03 : External channel 3 is selected as ADC input + * - 0x04 : External channel 4 is selected as ADC input + * - 0x05 : External channel 5 is selected as ADC input + * - 0x06 : External channel 6 is selected as ADC input + * - 0x07 : External channel 7 is selected as ADC input + * - 0x08 : External channel 8 is selected as ADC input + * - 0x09 : External channel 9 is selected as ADC input + * - 0x0A : External channel 10 is selected as ADC input + * - 0x0B : External channel 11 is selected as ADC input + * - 0x0C : External channel 12 is selected as ADC input + * - 0x0D : External channel 13 is selected as ADC input + * - 0x0E : External channel 14 is selected as ADC input + * - 0x0F : External channel 15 is selected as ADC input + * - 0x10 : External channel 16 is selected as ADC input + * - 0x11 : External channel 17 is selected as ADC input + * - 0x12 : External channel 18 is selected as ADC input + * - 0x13 : External channel 19 is selected as ADC input + * - 0x14 : External channel 20 is selected as ADC input + * - 0x15 : External channel 21 is selected as ADC input + * - 0x16 : External channel 22 is selected as ADC input + * - 0x17 : External channel 23 is selected as ADC input + * - 0x18 : Reserved + * - 0x19 : LPVBG + * - 0x1A : VBG + * - 0x1B : monitor ldo output + * - 0x1C : Reserved + * - 0x1D : Self Test Voltage + * - 0x1E : Reserved + * - 0x1F : Module is disabled */ __attribute__((always_inline)) static inline void AdcReg_SetScAdCh(AdcRegType *obj, uint8_t channel, uint8_t value) { @@ -1441,16 +1437,6 @@ __attribute__((always_inline)) static inline uint16_t AdcReg_GetRData(const AdcR return ((obj->R[channel] & ADC_R_DATA_MASK) >> ADC_R_DATA_SHIFT); } -/*! \brief Software trigger ADC - * This function for software trigger ADC. - * \param[in] obj : pointer to ADC register instance - */ -__attribute__((always_inline)) static inline void AdcReg_SwTrig(AdcRegType *obj) -{ - uint32_t tmp = obj->SC[0]; - obj->SC[0] = tmp; -} - /*! \brief Abort ADC chn * This function for software trigger ADC. * \param[in] obj : pointer to ADC register instance diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/axbs_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/axbs_reg.h index 260e0a2..5632b6b 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/axbs_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/axbs_reg.h @@ -162,7 +162,7 @@ __attribute__((always_inline)) static inline void AxbsReg_SetCsrMErr0(AxbsRegTyp * - 0b : No error has occurred for AXBS master 1 interface. * - 1b : An error has occurred for AXBS master 1 interface. */ -__attribute__((always_inline)) static inline uint8_t AxbsReg_GetCsrMerr1(const AxbsRegType *obj) +__attribute__((always_inline)) static inline uint8_t AxbsReg_GetCsrMErr1(const AxbsRegType *obj) { return ((obj->CSR & AXBS_CSR_MERR1_MASK) >> AXBS_CSR_MERR1_SHIFT); } @@ -181,7 +181,7 @@ __attribute__((always_inline)) static inline uint8_t AxbsReg_GetCsrMerr1(const A * - 0b : No effect * - 1b : Clear the error flag */ -__attribute__((always_inline)) static inline void AxbsReg_SetCsrMerr1(AxbsRegType *obj, uint8_t value) +__attribute__((always_inline)) static inline void AxbsReg_SetCsrMErr1(AxbsRegType *obj, uint8_t value) { /* Clear the affected bit-field and write '0' to the w1c bits to avoid side-effects */ uint32_t tmp = obj->CSR & AXBS_CSR_AHB_REG_VLD_MASK; diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/cache_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/cache_reg.h index 0c214f4..5edc710 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/cache_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/cache_reg.h @@ -48,12 +48,12 @@ extern "C" { #define CACHE_CTRL_MCNT_EN_MASK (0x40u) #define CACHE_CTRL_MCNT_EN_SHIFT (6u) #define CACHE_CTRL_MCNT_EN_WIDTH (1u) -#define CACHE_CTRL_DED_IE_MASK (0x20u) -#define CACHE_CTRL_DED_IE_SHIFT (5u) -#define CACHE_CTRL_DED_IE_WIDTH (1u) -#define CACHE_CTRL_SEC_IE_MASK (0x10u) -#define CACHE_CTRL_SEC_IE_SHIFT (4u) -#define CACHE_CTRL_SEC_IE_WIDTH (1u) +#define CACHE_CTRL_DED_ERM_EN_MASK (0x20u) +#define CACHE_CTRL_DED_ERM_EN_SHIFT (5u) +#define CACHE_CTRL_DED_ERM_EN_WIDTH (1u) +#define CACHE_CTRL_SEC_ERM_EN_MASK (0x10u) +#define CACHE_CTRL_SEC_ERM_EN_SHIFT (4u) +#define CACHE_CTRL_SEC_ERM_EN_WIDTH (1u) #define CACHE_CTRL_PFB_EN_MASK (0x04u) #define CACHE_CTRL_PFB_EN_SHIFT (2u) #define CACHE_CTRL_PFB_EN_WIDTH (1u) @@ -264,71 +264,69 @@ __attribute__((always_inline)) static inline void CacheReg_SetCtrlMCntEn(CacheRe obj->CTRL = tmp; } -/*! \brief Gets the cache ecc ded interrupt enable +/*! \brief Gets the configuration of cache ecc ded to erm * - * This function gets the current cache ecc ded interrupt enable. - * control the interrupt enable for ecc ded error + * This function gets the current configuration of cache ecc ded to erm. * * \param[in] obj : pointer to CACHE register instance - * \return cache ecc ded interrupt enable - * - 0b : disable ecc ded error interrupt - * - 1b : enable ecc ded error interrupt + * \return cache ecc ded to erm configuration + * - 0b : ecc ded to erm is disabled + * - 1b : ecc ded to erm is enabled */ -__attribute__((always_inline)) static inline uint8_t CacheReg_GetCtrlDedIE(const CacheRegType *obj) +__attribute__((always_inline)) static inline uint8_t CacheReg_GetCtrlDedErmEn(const CacheRegType *obj) { - return ((obj->CTRL & CACHE_CTRL_DED_IE_MASK) >> CACHE_CTRL_DED_IE_SHIFT); + return ((obj->CTRL & CACHE_CTRL_DED_ERM_EN_MASK) >> CACHE_CTRL_DED_ERM_EN_SHIFT); } -/*! \brief Sets the cache ecc ded interrupt enable +/*! \brief Sets the cache ecc ded to erm enable * - * This function sets the cache ecc ded interrupt enable. - * control the interrupt enable for ecc ded error + * This function sets the cache ecc ded to erm enable. + * control the enable for ecc ded to erm * * \param[in] obj : pointer to CACHE register instance - * \param[in] value : the value of cache ecc ded interrupt enable - * - 0b : disable ecc ded error interrupt - * - 1b : enable ecc ded error interrupt + * \param[in] value : the value of cache ecc ded to erm enable + * - 0b : disable ecc ded to erm + * - 1b : enable ecc ded to erm */ -__attribute__((always_inline)) static inline void CacheReg_SetCtrlDedIE(CacheRegType *obj, uint8_t value) +__attribute__((always_inline)) static inline void CacheReg_SetCtrlDedErmEn(CacheRegType *obj, uint8_t value) { uint32_t tmp = obj->CTRL; - tmp &= ~CACHE_CTRL_DED_IE_MASK; - tmp |= (((uint32_t)(((uint32_t)(value)) << CACHE_CTRL_DED_IE_SHIFT)) & CACHE_CTRL_DED_IE_MASK); + tmp &= ~CACHE_CTRL_DED_ERM_EN_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << CACHE_CTRL_DED_ERM_EN_SHIFT)) & CACHE_CTRL_DED_ERM_EN_MASK); obj->CTRL = tmp; } -/*! \brief Gets the cache ecc sec interrupt enable + /*! \brief Gets the configuration of cache ecc sec to erm * - * This function gets the current cache ecc sec interrupt enable. - * control the interrupt enable for ecc sec error + * This function gets the current configuration of cache ecc sec to erm. * * \param[in] obj : pointer to CACHE register instance - * \return cache ecc sec interrupt enable - * - 0b : disable ecc sec error interrupt - * - 1b : enable ecc sec error interrupt + * \return cache ecc sec to erm configuration + * - 0b : ecc sec to erm is disabled + * - 1b : ecc sec to erm is enabled */ -__attribute__((always_inline)) static inline uint8_t CacheReg_GetCtrlSecIE(const CacheRegType *obj) +__attribute__((always_inline)) static inline uint8_t CacheReg_GetCtrlSecErmEn(const CacheRegType *obj) { - return ((obj->CTRL & CACHE_CTRL_SEC_IE_MASK) >> CACHE_CTRL_SEC_IE_SHIFT); + return ((obj->CTRL & CACHE_CTRL_SEC_ERM_EN_MASK) >> CACHE_CTRL_SEC_ERM_EN_SHIFT); } -/*! \brief Sets the cache ecc sec interrupt enable + /*! \brief Sets the cache ecc sec to erm enable * - * This function sets the cache ecc sec interrupt enable. - * control the interrupt enable for ecc sec error + * This function sets the cache ecc sec to erm enable. + * control the enable for ecc sec to erm * * \param[in] obj : pointer to CACHE register instance - * \param[in] value : the value of cache ecc sec interrupt enable - * - 0b : disable ecc sec error interrupt - * - 1b : enable ecc sec error interrupt + * \param[in] value : the value of cache ecc sec to erm enable + * - 0b : disable ecc sec to erm + * - 1b : enable ecc sec to erm */ -__attribute__((always_inline)) static inline void CacheReg_SetCtrlSecIE(CacheRegType *obj, uint8_t value) +__attribute__((always_inline)) static inline void CacheReg_SetCtrlSecErmEn(CacheRegType *obj, uint8_t value) { uint32_t tmp = obj->CTRL; - tmp &= ~CACHE_CTRL_SEC_IE_MASK; - tmp |= (((uint32_t)(((uint32_t)(value)) << CACHE_CTRL_SEC_IE_SHIFT)) & CACHE_CTRL_SEC_IE_MASK); + tmp &= ~CACHE_CTRL_SEC_ERM_EN_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << CACHE_CTRL_SEC_ERM_EN_SHIFT)) & CACHE_CTRL_SEC_ERM_EN_MASK); obj->CTRL = tmp; } diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/cmp_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/cmp_reg.h index ae1ecd8..0b36899 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/cmp_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/cmp_reg.h @@ -213,11 +213,6 @@ extern "C" { #define CMP_C2_RRE_SHIFT (31u) #define CMP_C2_RRE_WIDTH (1u) -/* C3 Bit Fields */ -#define CMP_C3_STPD_MASK (0x1u) -#define CMP_C3_STPD_SHIFT (0u) -#define CMP_C3_STPD_WIDTH (1u) - /* C4 Bit Fields */ #define CMP_C4_LOCK_KEY_MASK (0xFFFFFFFFu) #define CMP_C4_LOCK_KEY_SHIFT (0u) @@ -230,11 +225,11 @@ extern "C" { */ typedef struct _CmpRegType_ { - volatile uint32_t C0; /*!< CMP control register 0, offset: 0x0 */ - volatile uint32_t C1; /*!< CMP control register 1, offset: 0x4 */ - volatile uint32_t C2; /*!< CMP control register 2, offset: 0x8 */ - volatile uint32_t C3; /*!< CMP control register 3, offset: 0xC */ - volatile uint32_t C4; /*!< CMP control register 4, offset: 0x10 */ + volatile uint32_t C0; /*!< CMP control register 0, offset: 0x0 */ + volatile uint32_t C1; /*!< CMP control register 1, offset: 0x4 */ + volatile uint32_t C2; /*!< CMP control register 2, offset: 0x8 */ + const volatile uint32_t C3; /*!< CMP control register 3, offset: 0xC */ + volatile uint32_t C4; /*!< CMP control register 4, offset: 0x10 */ } CmpRegType; /******************************************************************************* @@ -1479,8 +1474,6 @@ __attribute__((always_inline)) static inline void CmpReg_SetChn7Reg(CmpRegType * * \return the current CMP INNSEL register configuration. * - 00b: IN0, from the 8-bit DAC output * - 01b: IN1, from the analog 8-1 mux - * - 10b: test signal 0 - * - 11b: test signal 1 */ __attribute__((always_inline)) static inline uint8_t CmpReg_GetInnselReg(const CmpRegType *obj) { @@ -1498,8 +1491,6 @@ __attribute__((always_inline)) static inline uint8_t CmpReg_GetInnselReg(const C * \param[in] value : expected CMP INNSEL register configuration * - 00b: IN0, from the 8-bit DAC output * - 01b: IN1, from the analog 8-1 mux - * - 10b: test signal 0 - * - 11b: test signal 1 */ __attribute__((always_inline)) static inline void CmpReg_SetInnselReg(CmpRegType *obj, uint8_t value) { @@ -1519,8 +1510,6 @@ __attribute__((always_inline)) static inline void CmpReg_SetInnselReg(CmpRegType * \return the current CMP INPSEL register configuration. * - 00b: IN0, from the 8-bit DAC output * - 01b: IN1, from the analog 8-1 mux - * - 10b: test signal 0 - * - 11b: test signal 1 */ __attribute__((always_inline)) static inline uint8_t CmpReg_GetInpselReg(const CmpRegType *obj) { @@ -1538,8 +1527,6 @@ __attribute__((always_inline)) static inline uint8_t CmpReg_GetInpselReg(const C * \param[in] value : expected CMP INPSEL register configuration * - 00b: IN0, from the 8-bit DAC output * - 01b: IN1, from the analog 8-1 mux - * - 10b: test signal 0 - * - 11b: test signal 1 */ __attribute__((always_inline)) static inline void CmpReg_SetInpselReg(CmpRegType *obj, uint8_t value) { @@ -2319,42 +2306,6 @@ __attribute__((always_inline)) static inline void CmpReg_SetRreReg(CmpRegType *o obj->C2 = tmp; } -/*! \brief Get the current CMP STPD register configuration - * - * This function gets the current CMP STPD register configuration. - * If data size is less than 32 bits, the least significant bits are used for - * the correct value. - * - * \param[in] obj : pointer to CMP register instance - * \return the current CMP STPD register configuration. - * 0b: Self Test Voltage Genetor work, Self Test Voltage available. - * 1b: Self Test Voltage Genetor power off. - */ -__attribute__((always_inline)) static inline uint8_t CmpReg_GetStpdReg(const CmpRegType *obj) -{ - return ((obj->C3 & CMP_C3_STPD_MASK) >> CMP_C3_STPD_SHIFT); -} - -/*! \brief Set CMP STPD configuration - * - * This function writes new configuration to CMP STPD register - * If configuration size is less than 32 bits, the least significant bits are used for - * the correct value. - * This register write protect by CMP_C4_LOCK_KEY - * - * \param[in] obj : pointer to CMP register instance - * \param[in] value : expected CMP STPD register configuration - * 0b: Self Test Voltage Genetor work, Self Test Voltage available. - * 1b: Self Test Voltage Genetor power off. - */ -__attribute__((always_inline)) static inline void CmpReg_SetStpdReg(CmpRegType *obj, uint8_t value) -{ - uint32_t tmp = obj->C3; - tmp &= ~(CMP_C3_STPD_MASK); - tmp |= (((uint32_t)(((uint32_t)(value)) << CMP_C3_STPD_SHIFT)) & CMP_C3_STPD_MASK); - obj->C3 = tmp; -} - #ifdef __cplusplus } #endif /* extern "C" */ diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/edma_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/edma_reg.h index ee9f270..a1dbb8d 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/edma_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/edma_reg.h @@ -1379,6 +1379,8 @@ __attribute__((always_inline)) static inline void EDmaReg_ClearErrorIntStatusFla uint8_t cerrTmp = 0; cerrTmp |= (((uint8_t)(((uint8_t)(channel)) << EDMA_CERR_CERR_SHIFT)) & EDMA_CERR_CERR_MASK); obj->CERR = cerrTmp; + /* Read back to avoid problem */ + (void)obj->CERR; } /*! \brief Clear all bits in ERR @@ -1413,6 +1415,8 @@ __attribute__((always_inline)) static inline void EDmaReg_ClearIntStatusFlag(EDm uint8_t cintTmp = 0; cintTmp |= (((uint8_t)(((uint8_t)(channel)) << EDMA_CINT_CINT_SHIFT)) & EDMA_CINT_CINT_MASK); obj->CINT = cintTmp; + /* Read back to avoid problem */ + (void)obj->CINT; } /*! \brief Clear all bits in interrupt diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/erm_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/erm_reg.h index 10537b3..49568c2 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/erm_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/erm_reg.h @@ -38,7 +38,7 @@ extern "C" { /* Size of Reserved Registers Arrays */ #define ERM_REG_CR0_RESEERVED_CONUT (0x3) #define ERM_REG_SR_RESEERVED_CONUT (0x3B) -#define ERM_REG_CH3ST2_RESEERVED_CONUT (0x3) +#define ERM_REG_CH3ST2_RESEERVED_CONUT (0x2) /* Error Value */ #define ERM_RES_ERR_8B (0xFFu) @@ -69,7 +69,7 @@ extern "C" { #define ERM_CHx_ST0_WIDTH (32u) /* CHx(0~2) ST1 Bit Fields */ -#define ERM_CHx_ST1_MASK (0xFFu) +#define ERM_CHx_ST1_MASK (0xFF000000u) #define ERM_CHx_ST1_SHIFT (24u) #define ERM_CHx_ST1_WIDTH (8u) @@ -271,7 +271,7 @@ __attribute__((always_inline)) static inline uint8_t ErmReg_GetErrNum(const ErmR */ __attribute__((always_inline)) static inline void ErmReg_ClrErrNum(ErmRegType *obj, uint8_t chn, uint8_t errNumClr) { - obj->STATUS[chn].ST2 |= (uint32_t)errNumClr << ERM_CHx_ST2_SHIFT; + obj->STATUS[chn].ST2 = (uint32_t)errNumClr << ERM_CHx_ST2_SHIFT; } /*! \brief Get ERM channel4 ERR Number . @@ -296,7 +296,7 @@ __attribute__((always_inline)) static inline uint8_t ErmReg_GetErrChn4Num(const */ __attribute__((always_inline)) static inline void ErmReg_ClrErrChn4Num(ErmRegType *obj, uint8_t errNumClr) { - obj->CH4_ST2 |= (uint32_t)errNumClr << ERM_CHx_ST2_SHIFT; + obj->CH4_ST2 = (uint32_t)errNumClr << ERM_CHx_ST2_SHIFT; } #ifdef __cplusplus diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/fccu_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/fccu_reg.h index 005f83f..4b0ea77 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/fccu_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/fccu_reg.h @@ -932,7 +932,7 @@ __attribute__((always_inline)) static inline uint8_t FccuReg_GetIrqStCfgTO(FccuR */ __attribute__((always_inline)) static inline uint8_t FccuReg_GetIrqStAlarm(FccuRegType *obj) { - return ((obj->IRQ_ST & FCCU_IRQ_ST_ALARM_MASK) >> FCCU_IRQ_ST_CFG_TO_SHIFT); + return ((obj->IRQ_ST & FCCU_IRQ_ST_ALARM_MASK) >> FCCU_IRQ_ST_ALARM_SHIFT); } /*! \brief Sets the ALARM FSM interrupt status @@ -948,6 +948,7 @@ __attribute__((always_inline)) static inline void FccuReg_SetIrqStAlarm(FccuRegT { /* Clear the affected bit-field and write '0' to the w1c bits to avoid side-effects */ obj->IRQ_ST = (((uint32_t)(((uint32_t)(value)) << FCCU_IRQ_ST_ALARM_SHIFT)) & FCCU_IRQ_ST_ALARM_MASK); + (void)obj->IRQ_ST; } /*! \brief Sets the CFG FSM timeout interrupt status @@ -963,6 +964,7 @@ __attribute__((always_inline)) static inline void FccuReg_SetIrqStCfgTO(FccuRegT { /* Clear the affected bit-field and write '0' to the w1c bits to avoid side-effects */ obj->IRQ_ST = (((uint32_t)(((uint32_t)(value)) << FCCU_IRQ_ST_CFG_TO_SHIFT)) & FCCU_IRQ_ST_CFG_TO_MASK); + (void)obj->IRQ_ST; } /*! \brief Gets the ALARM state timer register diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/flexcan_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/flexcan_reg.h index d1cf98d..261c009 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/flexcan_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/flexcan_reg.h @@ -79,52 +79,85 @@ extern "C" { /* MCR register */ #define FLEXCAN_MCR_MDIS_SHIFT (31U) #define FLEXCAN_MCR_MDIS_MASK (0x1UL << FLEXCAN_MCR_MDIS_SHIFT) +#define FLEXCAN_MCR_MDIS_WIDTH (1u) #define FLEXCAN_MCR_FRZ_SHIFT (30U) #define FLEXCAN_MCR_FRZ_MASK (0x1UL << FLEXCAN_MCR_FRZ_SHIFT) +#define FLEXCAN_MCR_FRZ_WIDTH (1u) #define FLEXCAN_MCR_RFEN_SHIFT (29U) #define FLEXCAN_MCR_RFEN_MASK (0x1UL << FLEXCAN_MCR_RFEN_SHIFT) +#define FLEXCAN_MCR_RFEN_WIDTH (1u) #define FLEXCAN_MCR_HALT_SHIFT (28U) #define FLEXCAN_MCR_HALT_MASK (0x1UL << FLEXCAN_MCR_HALT_SHIFT) +#define FLEXCAN_MCR_HALT_WIDTH (1u) #define FLEXCAN_MCR_NOTRDY_SHIFT (27U) #define FLEXCAN_MCR_NOTRDY_MASK (0x1UL << FLEXCAN_MCR_NOTRDY_SHIFT) #define FLEXCAN_MCR_WAKMSK_SHIFT (26U) #define FLEXCAN_MCR_WAKMSK_MASK (0x1UL << FLEXCAN_MCR_WAKMSK_SHIFT) #define FLEXCAN_MCR_SOFTRST_SHIFT (25U) #define FLEXCAN_MCR_SOFTRST_MASK (0x1UL << FLEXCAN_MCR_SOFTRST_SHIFT) +#define FLEXCAN_MCR_SOFTRST_WIDTH (1u) #define FLEXCAN_MCR_FRZACK_SHIFT (24U) #define FLEXCAN_MCR_FRZACK_MASK (0x1UL << FLEXCAN_MCR_FRZACK_SHIFT) +#define FLEXCAN_MCR_FRZACK_WIDTH (1u) #define FLEXCAN_MCR_SUPV_SHIFT (23U) #define FLEXCAN_MCR_SUPV_MASK (0x1UL << FLEXCAN_MCR_SUPV_SHIFT) +#define FLEXCAN_MCR_SUPV_WIDTH (1u) #define FLEXCAN_MCR_SLFWAK_SHIFT (22U) #define FLEXCAN_MCR_SLFWAK_MASK (0x1UL << FLEXCAN_MCR_SLFWAK_SHIFT) +#define FLEXCAN_MCR_SLFWAK_WIDTH (1u) #define FLEXCAN_MCR_WRNEN_SHIFT (21U) #define FLEXCAN_MCR_WRNEN_MASK (0x1UL << FLEXCAN_MCR_WRNEN_SHIFT) +#define FLEXCAN_MCR_WRNEN_WIDTH (1u) #define FLEXCAN_MCR_LPMACK_SHIFT (20U) #define FLEXCAN_MCR_LPMACK_MASK (0x1UL << FLEXCAN_MCR_LPMACK_SHIFT) +#define FLEXCAN_MCR_LPMACK_WIDTH (1u) #define FLEXCAN_MCR_WAKSRC_SHIFT (19U) #define FLEXCAN_MCR_WAKSRC_MASK (0x1UL << FLEXCAN_MCR_WAKSRC_SHIFT) +#define FLEXCAN_MCR_WAKSRC_WIDTH (1u) #define FLEXCAN_MCR_DOZE_SHIFT (18U) #define FLEXCAN_MCR_DOZE_MASK (0x1UL << FLEXCAN_MCR_DOZE_SHIFT) +#define FLEXCAN_MCR_DOZE_WIDTH (1u) #define FLEXCAN_MCR_SRXDIS_SHIFT (17U) #define FLEXCAN_MCR_SRXDIS_MASK (0x1UL << FLEXCAN_MCR_SRXDIS_SHIFT) +#define FLEXCAN_MCR_SRXDIS_WIDTH (1u) #define FLEXCAN_MCR_IRQM_SHIFT (16U) #define FLEXCAN_MCR_IRQM_MASK (0x1UL << FLEXCAN_MCR_IRQM_SHIFT) +#define FLEXCAN_MCR_IRMQ_WIDTH (1u) #define FLEXCAN_MCR_DMA_SHIFT (15U) #define FLEXCAN_MCR_DMA_MASK (0x1UL << FLEXCAN_MCR_DMA_SHIFT) +#define FLEXCAN_MCR_DMA_WIDTH (1u) #define FLEXCAN_MCR_PNET_EN_MASK (0x4000u) #define FLEXCAN_MCR_PNET_EN_SHIFT (14) #define FLEXCAN_MCR_PNET_EN_WIDTH (1) +#define FLEXCAN_MCR_LPRIOEN_MASK (0x2000u) +#define FLEXCAN_MCR_LPRIOEN_SHIFT (13u) +#define FLEXCAN_MCR_LPRIOEN_WIDTH (1u) #define FLEXCAN_MCR_AEN_SHIFT (12U) #define FLEXCAN_MCR_AEN_MASK (0x1UL << FLEXCAN_MCR_AEN_SHIFT) #define FELXCAN_MCR_AEN_WIDTH (1U) #define FLEXCAN_MCR_FDEN_SHIFT (11U) #define FLEXCAN_MCR_FDEN_MASK (0x1UL << FLEXCAN_MCR_FDEN_SHIFT) +#define FLEXCAN_MCR_FDEN_WIDTH (1u) #define FLEXCAN_MCR_IDAM_SHIFT (8U) #define FLEXCAN_MCR_IDAM_MASK (0x3UL << FLEXCAN_MCR_IDAM_SHIFT) +#define FLEXCAN_MCR_IDAM_WIDTH (2U) #define FLEXCAN_MCR_MAXMB_SHIFT (0U) #define FLEXCAN_MCR_MAXMB_MASK (0x7FUL << FLEXCAN_MCR_MAXMB_SHIFT) +#define FLEXCAN_MCR_MAXMB_WIDTH (7u) /* CTRL1 register */ +#define FLEXCAN_CTRL1_PRESDIV_MASK (0xFF000000u) +#define FLEXCAN_CTRL1_PRESDIV_SHIFT (24u) +#define FLEXCAN_CTRL1_PRESDIV_WIDTH (8u) +#define FLEXCAN_CTRL1_RJW_MASK (0xC00000u) +#define FLEXCAN_CTRL1_RJW_SHIFT (22u) +#define FLEXCAN_CTRL1_RJW_WIDTH (2u) +#define FLEXCAN_CTRL1_PSEG1_MASK (0x380000u) +#define FLEXCAN_CTRL1_PSEG1_SHIFT (19u) +#define FLEXCAN_CTRL1_PSEG1_WIDTH (3u) +#define FLEXCAN_CTRL1_PSEG2_MASK (0x70000u) +#define FLEXCAN_CTRL1_PSEG2_SHIFT (16u) +#define FLEXCAN_CTRL1_PSEG2_WIDTH (3u) #define FLEXCAN_CTRL1_BOFFMSK_SHIFT (15U) #define FLEXCAN_CTRL1_BOFFMSK_MASK (0x1UL << FLEXCAN_CTRL1_BOFFMSK_SHIFT) #define FLEXCAN_CTRL1_BOFFMSK_WIDTH (1U) @@ -133,8 +166,10 @@ extern "C" { #define FLEXCAN_CTRL1_ERRMSK_WIDTH (1UL) #define FLEXCAN_CTRL1_CLKSRC_SHIFT (13U) #define FLEXCAN_CTRL1_CLKSRC_MASK (0x1UL << FLEXCAN_CTRL1_CLKSRC_SHIFT) +#define FLEXCAN_CTRL1_CLKSRC_WIDTH (1u) #define FLEXCAN_CTRL1_LPB_SHIFT (12U) #define FLEXCAN_CTRL1_LPB_MASK (0x1UL << FLEXCAN_CTRL1_LPB_SHIFT) +#define FLEXCAN_CTRL1_LPB_WIDTH (1u) #define FLEXCAN_CTRL1_TWRNMSK_SHIFT (11U) #define FLEXCAN_CTRL1_TWRNMSK_MASK (0x1UL << FLEXCAN_CTRL1_TWRNMSK_SHIFT) #define FLEXCAN_CTRL1_TWRNMSK_WIDTH (1U) @@ -156,57 +191,43 @@ extern "C" { #define FLEXCAN_CTRL1_LOM_SHIFT (3U) #define FLEXCAN_CTRL1_LOM_MASK (0x1UL << FLEXCAN_CTRL1_LOM_SHIFT) #define FLEXCAN_CTRL1_LOM_WIDTH (1U) +#define FLEXCAN_CTRL1_PROPSEG_MASK (0x07u) +#define FLEXCAN_CTRL1_PROPSEG_SHIFT (0u) +#define FLEXCAN_CTRL1_PROPSEG_WIDTH (3u) -/* CTRL2 register */ -#define FLEXCAN_CTRL2_TSTAMPCAP_MASK (0xC0u) -#define FLEXCAN_CTRL2_TSTAMPCAP_SHIFT (6) -#define FLEXCAN_CTRL2_TSTAMPCAP_WIDTH (2) +/* TIMER register */ +#define FLEXCAN_TIMER_TIMER_MASK (0xFFFFu) +#define FLEXCAN_TIMER_TIMER_SHIFT (0u) +#define FLEXCAN_TIMER_TIMER_WIDTH (16u) -#define FLEXCAN_CTRL2_MBTSBASE_MASK (0x300u) -#define FLEXCAN_CTRL2_MBTSBASE_SHIFT (8) -#define FLEXCAN_CTRL2_MBTSBASE_WIDTH (2) -#define FLEXCAN_CTRL2_EDFLTDIS_MASK (0x800u) -#define FLEXCAN_CTRL2_EDFLTDIS_SHIFT (11) -#define FLEXCAN_CTRL2_EDFLTDIS_WIDTH (1) -#define FLEXCAN_CTRL2_ISOCANFDEN_MASK (0x1000u) -#define FLEXCAN_CTRL2_ISOCANFDEN_SHIFT (12) -#define FLEXCAN_CTRL2_ISOCANFDEN_WIDTH (1) -#define FLEXCAN_CTRL2_BTE_MASK (0x2000u) -#define FLEXCAN_CTRL2_BTE_SHIFT (13) -#define FLEXCAN_CTRL2_BTE_WIDTH (1) -#define FLEXCAN_CTRL2_PREXCEN_MASK (0x4000u) -#define FLEXCAN_CTRL2_PREXCEN_SHIFT (14) -#define FLEXCAN_CTRL2_PREXCEN_WIDTH (1) -#define FLEXCAN_CTRL2_TIMER_SRC_MASK (0x8000u) -#define FLEXCAN_CTRL2_TIMER_SRC_SHIFT (15) -#define FLEXCAN_CTRL2_TIMER_SRC_WIDTH (1) -#define FLEXCAN_CTRL2_EACEN_MASK (0x10000u) -#define FLEXCAN_CTRL2_EACEN_SHIFT (16) -#define FLEXCAN_CTRL2_EACEN_WIDTH (1) -#define FLEXCAN_CTRL2_RRS_MASK (0x20000u) -#define FLEXCAN_CTRL2_RRS_SHIFT (17) -#define FLEXCAN_CTRL2_RRS_WIDTH (1) -#define FLEXCAN_CTRL2_MRP_MASK (0x40000u) -#define FLEXCAN_CTRL2_MRP_SHIFT (18) -#define FLEXCAN_CTRL2_MRP_WIDTH (1) -#define FLEXCAN_CTRL2_TASD_MASK (0xF80000u) -#define FLEXCAN_CTRL2_TASD_SHIFT (19) -#define FLEXCAN_CTRL2_TASD_WIDTH (5) -#define FLEXCAN_CTRL2_RFFN_MASK (0xF000000u) -#define FLEXCAN_CTRL2_RFFN_SHIFT (24) -#define FLEXCAN_CTRL2_RFFN_WIDTH (4) -#define FLEXCAN_CTRL2_WRMFRZ_MASK (0x10000000u) -#define FLEXCAN_CTRL2_WRMFRZ_SHIFT (28) -#define FLEXCAN_CTRL2_WRMFRZ_WIDTH (1) -#define FLEXCAN_CTRL2_ECRWRE_MASK (0x20000000u) -#define FLEXCAN_CTRL2_ECRWRE_SHIFT (29) -#define FLEXCAN_CTRL2_ECRWRE_WIDTH (1) -#define FLEXCAN_CTRL2_BOFFDONEMSK_MASK (0x40000000u) -#define FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT (30) -#define FLEXCAN_CTRL2_BOFFDONEMSK_WIDTH (1) -#define FLEXCAN_CTRL2_ERRMSK_FAST_MASK (0x80000000u) -#define FLEXCAN_CTRL2_ERRMSK_FAST_SHIFT (31) -#define FLEXCAN_CTRL2_ERRMSK_FAST_WIDTH (1) +/* RXMGMASK register */ +#define FLEXCAN_RXMGMASK_MG_MASK (0xFFFFFFFFu) +#define FLEXCAN_RXMGMASK_MG_SHIFT (0u) +#define FLEXCAN_RXMGMASK_MG_WIDTH (32u) + +/* RX14MASK register */ +#define FLEXCAN_RX14MASK_RX14M_MASK (0xFFFFFFFFu) +#define FLEXCAN_RX14MASK_RX14M_SHIFT (0u) +#define FLEXCAN_RX14MASK_RX14M_WIDTH (32u) + +/* RX15MASK register */ +#define FLEXCAN_RX15MASK_RX15M_MASK (0xFFFFFFFFu) +#define FLEXCAN_RX15MASK_RX15M_SHIFT (0u) +#define FLEXCAN_RX15MASK_RX15M_WIDTH (32u) + +/* ECR register */ +#define FLEXCAN_ECR_RXERRCNTFAST_MASK (0xFF000000u) +#define FLEXCAN_ECR_RXERRCNTFAST_SHIFT (24u) +#define FLEXCAN_ECR_RXERRCNTFAST_WIDTH (8u) +#define FLEXCAN_ECR_TXERRCNTFAST_MASK (0xFF0000u) +#define FLEXCAN_ECR_TXERRCNTFAST_SHIFT (16u) +#define FLEXCAN_ECR_TXERRCNTFAST_WIDTH (8u) +#define FLEXCAN_ECR_RXERRCNT_MASK (0xFF00u) +#define FLEXCAN_ECR_RXERRCNT_SHIFT (8u) +#define FLEXCAN_ECR_RXERRCNT_WIDTH (8u) +#define FLEXCAN_ECR_TXERRCNT_MASK (0xFFu) +#define FLEXCAN_ECR_TXERRCNT_SHIFT (0u) +#define FLEXCAN_ECR_TXERRCNT_WIDTH (8u) /* ESR1 register */ #define FLEXCAN_ESR1_BIT1ERR_FAST_SHIFT (31U) @@ -288,27 +309,160 @@ extern "C" { #define FLEXCAN_ESR1_WAKINT_MASK (0x1UL << FLEXCAN_ESR1_WAKINT_SHIFT) #define FLEXCAN_ESR1_WAKINT_WIDTH (1U) +/* CTRL2 register */ +#define FLEXCAN_CTRL2_ERRMSKFAST_MASK (0x80000000u) +#define FLEXCAN_CTRL2_ERRMSKFAST_SHIFT (31u) +#define FLEXCAN_CTRL2_ERRMSKFAST_WIDTH (1u) +#define FLEXCAN_CTRL2_BOFFDONEMSK_MASK (0x40000000u) +#define FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT (30u) +#define FLEXCAN_CTRL2_BOFFDONEMSK_WIDTH (1u) +#define FLEXCAN_CTRL2_ECRWRE_SHIFT (29U) +#define FLEXCAN_CTRL2_ECRWRE_MASK (0x1UL << FLEXCAN_CTRL2_ECRWRE_SHIFT) +#define FLEXCAN_CTRL2_ECRWRE_WIDTH (1u) +#define FLEXCAN_CTRL2_WRMFRZ_SHIFT (28U) +#define FLEXCAN_CTRL2_WRMFRZ_MASK (0x1UL << FLEXCAN_CTRL2_WRMFRZ_SHIFT) +#define FLEXCAN_CTRL2_WRMFRZ_WIDTH (1u) +#define FLEXCAN_CTRL2_RFFN_SHIFT (24U) +#define FLEXCAN_CTRL2_RFFN_MASK (0xFUL << FLEXCAN_CTRL2_RFFN_SHIFT) +#define FLEXCAN_CTRL2_RFFN_WIDTH (4U) +#define FLEXCAN_CTRL2_TASD_MASK (0xF80000u) +#define FLEXCAN_CTRL2_TASD_SHIFT (19u) +#define FLEXCAN_CTRL2_TASD_WIDTH (5u) +#define FLEXCAN_CTRL2_MRP_MASK (0x40000u) +#define FLEXCAN_CTRL2_MRP_SHIFT (18u) +#define FLEXCAN_CTRL2_MRP_WIDTH (1u) +#define FLEXCAN_CTRL2_RRS_MASK (0x20000u) +#define FLEXCAN_CTRL2_RRS_SHIFT (17u) +#define FLEXCAN_CTRL2_RRS_WIDTH (1u) +#define FLEXCAN_CTRL2_EACEN_MASK (0x10000u) +#define FLEXCAN_CTRL2_EACEN_SHIFT (16u) +#define FLEXCAN_CTRL2_EACEN_WIDTH (1u) +#define FLEXCAN_CTRL2_TIMERSRC_MASK (0x8000u) +#define FLEXCAN_CTRL2_TIMERSRC_SHIFT (15u) +#define FLEXCAN_CTRL2_TIMERSRC_WIDTH (1u) +#define FLEXCAN_CTRL2_PREXCEN_MASK (0x4000u) +#define FLEXCAN_CTRL2_PREXCEN_SHIFT (14u) +#define FLEXCAN_CTRL2_PREXCEN_WIDTH (1u) +#define FLEXCAN_CTRL2_BTE_MASK (0x2000u) +#define FLEXCAN_CTRL2_BTE_SHIFT (13) +#define FLEXCAN_CTRL2_BTE_WIDTH (1) +#define FLEXCAN_CTRL2_ISOCANFDEN_SHIFT (12U) +#define FLEXCAN_CTRL2_ISOCANFDEN_MASK (0x1UL << FLEXCAN_CTRL2_ISOCANFDEN_SHIFT) +#define FLEXCAN_CTRL2_ISOCANFDEN_WIDTH (1u) +#define FLEXCAN_CTRL2_EDFLTDIS_MASK (0x800u) +#define FLEXCAN_CTRL2_EDFLTDIS_SHIFT (11u) +#define FLEXCAN_CTRL2_EDFLTDIS_WIDTH (1u) +#define FLEXCAN_CTRL2_MBTSBASE_MASK (0x300u) +#define FLEXCAN_CTRL2_MBTSBASE_SHIFT (8) +#define FLEXCAN_CTRL2_MBTSBASE_WIDTH (2) +#define FLEXCAN_CTRL2_TSTAMPCAP_MASK (0xC0u) +#define FLEXCAN_CTRL2_TSTAMPCAP_SHIFT (6) +#define FLEXCAN_CTRL2_TSTAMPCAP_WIDTH (2) + +/* ESR2 register */ +#define FLEXCAN_ESR2_LPTM_MASK (0x7F0000u) +#define FLEXCAN_ESR2_LPTM_SHIFT (16u) +#define FLEXCAN_ESR2_LPTM_WIDTH (7u) +#define FLEXCAN_ESR2_VPS_MASK (0x4000u) +#define FLEXCAN_ESR2_VPS_SHIFT (14u) +#define FLEXCAN_ESR2_VPS_WIDTH (1u) +#define FLEXCAN_ESR2_IMB_MASK (0x2000u) +#define FLEXCAN_ESR2_IMB_SHIFT (13u) +#define FLEXCAN_ESR2_IMB_WIDTH (1u) + +/* CRCR register */ +#define FLEXCAN_CRCR_MBCRC_MASK (0x7F0000u) +#define FLEXCAN_CRCR_MBCRC_SHIFT (16u) +#define FLEXCAN_CRCR_MBCRC_WIDTH (7u) +#define FLEXCAN_CRCR_TXCRC_MASK (0x7FFFu) +#define FLEXCAN_CRCR_TXCRC_SHIFT (0u) +#define FLEXCAN_CRCR_TXCRC_WIDTH (15u) + +/* RXFGMASK register */ +#define FLEXCAN_RXFGMASK_FGM_MASK (0xFFFFFFFFu) +#define FLEXCAN_RXFGMASK_FGM_SHIFT (0u) +#define FLEXCAN_RXFGMASK_FGM_WIDTH (32u) + +/* RXFIR register */ +#define FLEXCAN_RXFIR_IDHIT_MASK (0x1FFu) +#define FLEXCAN_RXFIR_IDHIT_SHIFT (0u) +#define FLEXCAN_RXFIR_IDHIT_WIDTH (9u) + /* CBT register */ #define FLEXCAN_CBT_BTF_SHIFT (31U) #define FLEXCAN_CBT_BTF_MASK (0x1UL << FLEXCAN_CBT_BTF_SHIFT) +#define FLEXCAN_CBT_BTF_WIDTH (1u) #define FLEXCAN_CBT_EPRESDIV_SHIFT (21U) #define FLEXCAN_CBT_EPRESDIV_MASK (0x3FFUL << FLEXCAN_CBT_EPRESDIV_SHIFT) +#define FLEXCAN_CBT_EPRESDIV_WIDTH (10u) #define FLEXCAN_CBT_ERJW_SHIFT (16U) #define FLEXCAN_CBT_ERJW_MASK (0x1FUL << FLEXCAN_CBT_ERJW_SHIFT) +#define FLEXCAN_CBT_ERJW_WIDTH (5u) #define FLEXCAN_CBT_EPROPSEG_SHIFT (10U) #define FLEXCAN_CBT_EPROPSEG_MASK (0x3FUL << FLEXCAN_CBT_EPROPSEG_SHIFT) +#define FLEXCAN_CBT_EPROPSEG_WIDTH (6u) #define FLEXCAN_CBT_EPSEG1_SHIFT (5U) #define FLEXCAN_CBT_EPSEG1_MASK (0x1FUL << FLEXCAN_CBT_EPSEG1_SHIFT) +#define FLEXCAN_CBT_EPSEG1_WIDTH (5u) #define FLEXCAN_CBT_EPSEG2_SHIFT (0U) #define FLEXCAN_CBT_EPSEG2_MASK (0x1FUL << FLEXCAN_CBT_EPSEG2_SHIFT) +/* IMASK4 register */ +#define FLEXCAN_IMASK4_BUF127TO96M_MASK (0xFFFFFFFFu) +#define FLEXCAN_IMASK4_BUF127TO96M_SHIFT (0u) +#define FLEXCAN_IMASK4_BUF127TO96M_WIDTH (32u) + +/* IMASK3 register */ +#define FLEXCAN_IMASK3_BUF95TO64M_MASK (0xFFFFFFFFu) +#define FLEXCAN_IMASK3_BUF95TO64M_SHIFT (0u) +#define FLEXCAN_IMASK3_BUF95TO64M_WIDTH (32u) + +/* IFLAG4 register */ +#define FLEXCAN_IFLAG4_BUF127TO96_MASK (0xFFFFFFFFu) +#define FLEXCAN_IFLAG4_BUF127TO96_SHIFT (0u) +#define FLEXCAN_IFLAG4_BUF127TO96_WIDTH (32u) + +/* IFLAG3 register */ +#define FLEXCAN_IFLAG3_BUF95TO64_MASK (0xFFFFFFFFu) +#define FLEXCAN_IFLAG3_BUF95TO64_SHIFT (0u) +#define FLEXCAN_IFLAG3_BUF95TO64_WIDTH (32u) + +/* RXIMRN register */ +#define FLEXCAN_RXIMRN_MI_MASK (0xFFFFFFFFu) +#define FLEXCAN_RXIMRN_MI_SHIFT (0u) +#define FLEXCAN_RXIMRN_MI_WIDTH (32u) + /* MECR register */ #define FLEXCAN_MECR_ECRWRDIS_SHIFT (31U) #define FLEXCAN_MECR_ECRWRDIS_MASK (0x1UL << FLEXCAN_MECR_ECRWRDIS_SHIFT) +#define FLEXCAN_MECR_ECRWRDIS_WIDTH (1u) +#define FLEXCAN_MECR_HANCEIMSK_MASK (0x80000u) +#define FLEXCAN_MECR_HANCEIMSK_SHIFT (19u) +#define FLEXCAN_MECR_HANCEIMSK_WIDTH (1u) +#define FLEXCAN_MECR_FANCEIMSK_MASK (0x40000u) +#define FLEXCAN_MECR_FANCEIMSK_SHIFT (18u) +#define FLEXCAN_MECR_FANCEIMSK_WIDTH (1u) +#define FLEXCAN_MECR_CEIMSK_MASK (0x10000u) +#define FLEXCAN_MECR_CEIMSK_SHIFT (16u) +#define FLEXCAN_MECR_CEIMSK_WIDTH (1u) +#define FLEXCAN_MECR_HAERRIE_MASK (0x8000u) +#define FLEXCAN_MECR_HAERRIE_SHIFT (15u) +#define FLEXCAN_MECR_HAERRIE_WIDTH (1u) +#define FLEXCAN_MECR_FAERRIE_MASK (0x4000u) +#define FLEXCAN_MECR_FAERRIE_SHIFT (14u) +#define FLEXCAN_MECR_FAERRIE_WIDTH (1u) +#define FLEXCAN_MECR_EXTERRIE_MASK (0x2000u) +#define FLEXCAN_MECR_EXTERRIE_SHIFT (13u) +#define FLEXCAN_MECR_EXTERRIE_WIDTH (1u) +#define FLEXCAN_MECR_RERRDIS_MASK (0x200u) +#define FLEXCAN_MECR_RERRDIS_SHIFT (9u) +#define FLEXCAN_MECR_RERRDIS_WIDTH (1u) #define FLEXCAN_MECR_ECCDIS_SHIFT (8U) #define FLEXCAN_MECR_ECCDIS_MASK (0x1UL << FLEXCAN_MECR_ECCDIS_SHIFT) +#define FLEXCAN_MECR_ECCDIS_WIDTH (1u) #define FLEXCAN_MECR_NCEFAFRZ_SHIFT (7U) #define FLEXCAN_MECR_NCEFAFRZ_MASK (0x1UL << FLEXCAN_MECR_NCEFAFRZ_SHIFT) +#define FLEXCAN_MECR_NCEFAFRZ_WIDTH (1u) /* EPRS register */ #define FLEXCAN_EPRS_EDPRESDIV_SHIFT (16U) @@ -343,30 +497,56 @@ extern "C" { /* FDCTRL register */ #define FLEXCAN_FDCTRL_FDRATE_SHIFT (31U) #define FLEXCAN_FDCTRL_FDRATE_MASK (0x1UL << FLEXCAN_FDCTRL_FDRATE_SHIFT) +#define FLEXCAN_FDCTRL_FDRATE_WIDTH (1u) #define FLEXCAN_FDCTRL_MBDSR3_SHIFT (25U) #define FLEXCAN_FDCTRL_MBDSR3_MASK (0x3UL << FLEXCAN_FDCTRL_MBDSR3_SHIFT) +#define FLEXCAN_FDCTRL_MBDSR3_WIDTH (2u) #define FLEXCAN_FDCTRL_MBDSR2_SHIFT (22U) #define FLEXCAN_FDCTRL_MBDSR2_MASK (0x3UL << FLEXCAN_FDCTRL_MBDSR2_SHIFT) +#define FLEXCAN_FDCTRL_MBDSR2_WIDTH (2u) #define FLEXCAN_FDCTRL_MBDSR1_SHIFT (19U) #define FLEXCAN_FDCTRL_MBDSR1_MASK (0x3UL << FLEXCAN_FDCTRL_MBDSR1_SHIFT) +#define FLEXCAN_FDCTRL_MBDSR1_WIDTH (2u) #define FLEXCAN_FDCTRL_MBDSR0_SHIFT (16U) #define FLEXCAN_FDCTRL_MBDSR0_MASK (0x3UL << FLEXCAN_FDCTRL_MBDSR0_SHIFT) +#define FLEXCAN_FDCTRL_MBDSR0_WIDTH (2u) #define FLEXCAN_FDCTRL_TDCEN_SHIFT (15U) #define FLEXCAN_FDCTRL_TDCEN_MASK (0x1UL << FLEXCAN_FDCTRL_TDCEN_SHIFT) +#define FLEXCAN_FDCTRL_TDCEN_WIDTH (1u) +#define FLEXCAN_FDCTRL_TDCFAIL_MASK (0x4000u) +#define FLEXCAN_FDCTRL_TDCFAIL_SHIFT (14u) +#define FLEXCAN_FDCTRL_TDCFAIL_WIDTH (1u) #define FLEXCAN_FDCTRL_TDCOFF_SHIFT (8U) #define FLEXCAN_FDCTRL_TDCOFF_MASK (0x1FUL << FLEXCAN_FDCTRL_TDCOFF_SHIFT) +#define FLEXCAN_FDCTRL_TDCOFF_WIDTH (5u) +#define FLEXCAN_FDCTRL_TDCVAL_MASK (0x3Fu) +#define FLEXCAN_FDCTRL_TDCVAL_SHIFT (0u) +#define FLEXCAN_FDCTRL_TDCVAL_WIDTH (6u) /* FDCBT register */ #define FLEXCAN_FDCBT_FPRESDIV_SHIFT (20U) #define FLEXCAN_FDCBT_FPRESDIV_MASK (0x3FFUL << FLEXCAN_FDCBT_FPRESDIV_SHIFT) +#define FLEXCAN_FDCBT_FPRESDIV_WIDTH (10u) #define FLEXCAN_FDCBT_FRJW_SHIFT (16U) #define FLEXCAN_FDCBT_FRJW_MASK (0x7UL << FLEXCAN_FDCBT_FRJW_SHIFT) +#define FLEXCAN_FDCBT_FPJW_WIDTH (3u) #define FLEXCAN_FDCBT_FPROPSEG_SHIFT (10U) #define FLEXCAN_FDCBT_FPROPSEG_MASK (0x1FUL << FLEXCAN_FDCBT_FPROPSEG_SHIFT) +#define FLEXCAN_FDCBT_FPROPSEG_WIDTH (5u) #define FLEXCAN_FDCBT_FPSEG1_SHIFT (5U) #define FLEXCAN_FDCBT_FPSEG1_MASK (0x7UL << FLEXCAN_FDCBT_FPSEG1_SHIFT) +#define FLEXCAN_FDCBT_FPSEG1_WIDTH (3u) #define FLEXCAN_FDCBT_FPSEG2_SHIFT (0U) #define FLEXCAN_FDCBT_FPSEG2_MASK (0x7UL << FLEXCAN_FDCBT_FPSEG2_SHIFT) +#define FLEXCAN_FDCBT_FPSEG2_WIDTH (3u) + +/* FDCRC register */ +#define CAN_FDCRC_FDMBCRC_MASK (0x7F000000u) +#define CAN_FDCRC_FDMBCRC_SHIFT (24u) +#define CAN_FDCRC_FDMBCRC_WIDTH (7u) +#define CAN_FDCRC_FDTXCRC_MASK (0x1FFFFFu) +#define CAN_FDCRC_FDTXCRC_SHIFT (0u) +#define CAN_FDCRC_FDTXCRC_WIDTH (21u) /* ERFCR register */ #define FLEXCAN_ERFCR_ERFEN_SHIFT (31U) @@ -425,20 +605,6 @@ extern "C" { #define FLEXCAN_ERFSR_ERFEL_MASK (0x3FUL << FLEXCAN_ERFSR_ERFEL_SHIFT) #define FLEXCAN_ERFSR_ERFEL_WIDTH (6U) -/* ECR Bit Fields */ -#define FLEXCAN_ECR_TXERRCNT_MASK (0xFFu) -#define FLEXCAN_ECR_TXERRCNT_SHIFT (0) -#define FLEXCAN_ECR_TXERRCNT_WIDTH (8) -#define FLEXCAN_ECR_RXERRCNT_MASK (0xFF00u) -#define FLEXCAN_ECR_RXERRCNT_SHIFT (8) -#define FLEXCAN_ECR_RXERRCNT_WIDTH (8) -#define FLEXCAN_ECR_TXERRCNT_FAST_MASK (0xFF0000u) -#define FLEXCAN_ECR_TXERRCNT_FAST_SHIFT (16) -#define FLEXCAN_ECR_TXERRCNT_FAST_WIDTH (8) -#define FLEXCAN_ECR_RXERRCNT_FAST_MASK (0xFF000000u) -#define FLEXCAN_ECR_RXERRCNT_FAST_SHIFT (24) -#define FLEXCAN_ECR_RXERRCNT_FAST_WIDTH (8) - /******************************************************************************* * the typedefs ******************************************************************************/ @@ -962,6 +1128,18 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetSelfReceptionDis obj->MCR = tempReg; } +/*! \brief Get rx individual mask + * + * \param[in] obj : pointer to FlexCAN register instance + * \return individual mask enable + * -0b : individual mask disable + * -1b : individual mask enable + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetIndividualMaskEnable(const FlexCanRegType *obj) +{ + return ((obj->MCR & FLEXCAN_MCR_IRQM_MASK) >> FLEXCAN_MCR_IRQM_SHIFT); +} + /*! \brief Set rx individual mask * * \param[in] obj : pointer to FlexCAN register instance @@ -979,6 +1157,18 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetIndividualMaskEn obj->MCR = tempReg; } +/*! \brief Get rx fifo dma enable or disable + * + * \param[in] obj : pointer to FlexCAN register instance + * \return rx fifo dma enable + * -0b : rx fifo dma disable + * -1b : rx fifo dma enable + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetRxFIFODmaEnable(const FlexCanRegType *obj) +{ + return ((obj->MCR & FLEXCAN_MCR_DMA_MASK) >> FLEXCAN_MCR_DMA_SHIFT); +} + /*! \brief Set rx fifo dma enable or disable * * \param[in] obj : pointer to FlexCAN register instance @@ -996,6 +1186,34 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetRxFIFODmaEnable( obj->MCR = tempReg; } +/*! \brief Get local priority enable + * + * \param[in] obj : pointer to FlexCAN register instance + * \return local priority enable + * -0b : local priority disable + * -1b : local priority enable + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetMcrLprioen(const FlexCanRegType *obj) +{ + return ((obj->MCR & FLEXCAN_MCR_LPRIOEN_MASK) >> FLEXCAN_MCR_LPRIOEN_SHIFT); +} + +/*! \brief Set local priority enable + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] enable : local priority enable + * -0b : local priority disable + * -1b : local priority enable + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetMcrLprioen(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->MCR; + + tmp &= ~FLEXCAN_MCR_LPRIOEN_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_MCR_LPRIOEN_SHIFT)) & FLEXCAN_MCR_LPRIOEN_MASK); + obj->MCR = tmp; +} + /*! \brief Set rx acceptance id mode * * \param[in] obj : pointer to FlexCAN register instance @@ -1167,6 +1385,110 @@ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdEnable(Flex return enable; } +/*! \brief Get prescaler division factor + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: prescaler division factor + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl1Presdiv(const FlexCanRegType *obj) +{ + return ((obj->CTRL1 & FLEXCAN_CTRL1_PRESDIV_MASK) >> FLEXCAN_CTRL1_PRESDIV_SHIFT); +} + +/*! \brief Set prescaler division factor + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : prescaler division factor + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl1Presdiv(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->CTRL1; + + tmp &= ~FLEXCAN_CTRL1_PRESDIV_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL1_PRESDIV_SHIFT)) & FLEXCAN_CTRL1_PRESDIV_MASK); + obj->CTRL1 = tmp; +} + +/*! \brief Get resync jump width + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: resync jump width + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl1Rjw(const FlexCanRegType *obj) +{ + return ((obj->CTRL1 & FLEXCAN_CTRL1_RJW_MASK) >> FLEXCAN_CTRL1_RJW_SHIFT); +} + +/*! \brief Set resync jump width + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : resync jump width + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl1Rjw(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->CTRL1; + + tmp &= ~FLEXCAN_CTRL1_RJW_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL1_RJW_SHIFT)) & FLEXCAN_CTRL1_RJW_MASK); + obj->CTRL1 = tmp; +} + +/*! \brief Get phase segment 1 + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: phase segment 1 + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl1Pseg1(const FlexCanRegType *obj) +{ + return ((obj->CTRL1 & FLEXCAN_CTRL1_PSEG1_MASK) >> FLEXCAN_CTRL1_PSEG1_SHIFT); +} + +/*! \brief Set phase segment 1 + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : phase segment 1 + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl1Pseg1(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->CTRL1; + + tmp &= ~FLEXCAN_CTRL1_PSEG1_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL1_PSEG1_SHIFT)) & FLEXCAN_CTRL1_PSEG1_MASK); + obj->CTRL1 = tmp; +} + +/*! \brief Get phase segment 2 + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: phase segment 2 + */ +__attribute__((always_inline)) static inline uint8_t CanReg_GetCtrl1Pseg2(const FlexCanRegType *obj) +{ + return ((obj->CTRL1 & FLEXCAN_CTRL1_PSEG2_MASK) >> FLEXCAN_CTRL1_PSEG2_SHIFT); +} + +/*! \brief Set phase segment 2 + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : phase segment 2 + */ +__attribute__((always_inline)) static inline void CanReg_SetCtrl1Pseg2(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->CTRL1; + + tmp &= ~FLEXCAN_CTRL1_PSEG2_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL1_PSEG2_SHIFT)) & FLEXCAN_CTRL1_PSEG2_MASK); + obj->CTRL1 = tmp; +} + /*! \brief Set bus off interrupt enable * * @@ -1229,6 +1551,19 @@ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetErrorIntEnabl return (uint8_t)(((obj->CTRL1) & FLEXCAN_CTRL1_ERRMSK_MASK) >> FLEXCAN_CTRL1_ERRMSK_SHIFT); } +/*! \brief Get module clock source + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: module clock source + * -0b : The PE clock source is the oscillator clock. + * -1b : The PE clock source is the peripheral clock. + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetClockSource(const FlexCanRegType *obj) +{ + return ((obj->CTRL1 & FLEXCAN_CTRL1_CLKSRC_MASK) >> FLEXCAN_CTRL1_CLKSRC_SHIFT); +} + /*! \brief Selects the clock source to the PE submodule to be either the peripheral clock or the oscillator clock * * @@ -1248,6 +1583,19 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetClockSource(Flex obj->CTRL1 = tempReg; } +/*! \brief Get can loop back mode + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: can loop back mode + * 0b - disable + * 1b - enable + */ +__attribute__((always_inline)) static inline uint8_t CanReg_GetLoopbackMode(const FlexCanRegType *obj) +{ + return ((obj->CTRL1 & FLEXCAN_CTRL1_LPB_MASK) >> FLEXCAN_CTRL1_LPB_SHIFT); +} + /*! \brief Set can loop back mode * * @@ -1329,6 +1677,19 @@ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetRxWarnIntEnab return (uint8_t)(((obj->CTRL1) & FLEXCAN_CTRL1_RWRNMSK_MASK) >> FLEXCAN_CTRL1_RWRNMSK_SHIFT); } +/*! \brief Get CAN bit sampling mode + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: CAN bit sampling mode + * -0b : one sample is used to determine the bit value + * -1b : three samples are used to determine the value of the received bit + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetBitSamplingType(const FlexCanRegType *obj) +{ + return ((obj->CTRL1 & FLEXCAN_CTRL1_SMP_MASK) >> FLEXCAN_CTRL1_SMP_SHIFT); +} + /*! \brief Set bus off automatic recovering enable * * @@ -1478,6 +1839,32 @@ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetListenOnlyMod return (uint8_t)(((obj->CTRL1) & FLEXCAN_CTRL1_LOM_MASK) >> FLEXCAN_CTRL1_LOM_SHIFT); } +/*! \brief Get propagation segment + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: propagation segment length + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl1Propseg(const FlexCanRegType *obj) +{ + return ((obj->CTRL1 & FLEXCAN_CTRL1_PROPSEG_MASK) >> FLEXCAN_CTRL1_PROPSEG_SHIFT); +} + +/*! \brief Set propagation segment + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : propagation segment length + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl1Propseg(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->CTRL1; + + tmp &= ~FLEXCAN_CTRL1_PROPSEG_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL1_PROPSEG_SHIFT)) & FLEXCAN_CTRL1_PROPSEG_MASK); + obj->CTRL1 = tmp; +} + /*! \brief Get free running timer * * @@ -1490,6 +1877,62 @@ __attribute__((always_inline)) static inline uint32_t FlexCanReg_GetFreeRunningT return obj->TIMER; } +/*! \brief Get receive error counter for fast bits + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: receive error counter for fast bits + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEcrRxerrcntfast(const FlexCanRegType *obj) +{ + return ((obj->ECR & FLEXCAN_ECR_RXERRCNTFAST_MASK) >> FLEXCAN_ECR_RXERRCNTFAST_SHIFT); +} + +/*! \brief Set receive error counter for fast bits + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : receive error counter for fast bits + * + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetEcrRxerrcntfast(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->ECR; + + tmp &= ~FLEXCAN_ECR_RXERRCNTFAST_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_ECR_RXERRCNTFAST_SHIFT)) & FLEXCAN_ECR_RXERRCNTFAST_MASK); + obj->ECR = tmp; +} + +/*! \brief Get transmit error counter for fast bits + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: transmit error counter for fast bits + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEcrTxerrcntfast(const FlexCanRegType *obj) +{ + return ((obj->ECR & FLEXCAN_ECR_TXERRCNTFAST_MASK) >> FLEXCAN_ECR_TXERRCNTFAST_SHIFT); +} + +/*! \brief Set transmit error counter for fast bits + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : transmit error counter for fast bits + * + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetEcrTxerrcntfast(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->ECR; + + tmp &= ~FLEXCAN_ECR_TXERRCNTFAST_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_ECR_TXERRCNTFAST_SHIFT)) & FLEXCAN_ECR_TXERRCNTFAST_MASK); + obj->ECR = tmp; +} + /*! \brief Set fast error interrupt enable * * @@ -1502,8 +1945,8 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetFastErrIntEnable { uint32_t tempReg; tempReg = obj->CTRL2; - tempReg &= (~FLEXCAN_CTRL2_ERRMSK_FAST_MASK); - tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL2_ERRMSK_FAST_SHIFT) & FLEXCAN_CTRL2_ERRMSK_FAST_MASK; + tempReg &= (~FLEXCAN_CTRL2_ERRMSKFAST_MASK); + tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL2_ERRMSKFAST_SHIFT) & FLEXCAN_CTRL2_ERRMSKFAST_MASK; obj->CTRL2 = tempReg; } @@ -1518,7 +1961,20 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetFastErrIntEnable */ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFastErrIntEnable(FlexCanRegType *obj) { - return (uint8_t)(((obj->CTRL2) & FLEXCAN_CTRL2_ERRMSK_FAST_MASK) >> FLEXCAN_CTRL2_ERRMSK_FAST_SHIFT); + return (uint8_t)(((obj->CTRL2) & FLEXCAN_CTRL2_ERRMSKFAST_MASK) >> FLEXCAN_CTRL2_ERRMSKFAST_SHIFT); +} + +/*! \brief Get error correction configuration register write enable + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: error correction configuration register write enable + * 0: error correction configuration register write disable + * 1: error correction configuration register write enable + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetMemErrCtrlRegWriteEnable(const FlexCanRegType *obj) +{ + return ((obj->CTRL2 & FLEXCAN_CTRL2_ECRWRE_MASK) >> FLEXCAN_CTRL2_ECRWRE_SHIFT); } /*! \brief Correction Configuration Register Write Enable @@ -1539,6 +1995,19 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetMemErrCtrlRegWri obj->CTRL2 = tempReg; } +/*! \brief Get write access to memory in freeze mode enable + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: write access to memory in freeze mode enable + * 0: write access to memory in freeze mode disable + * 1: write access to memory in freeze mode enable + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFreezeModeWriteAcc(const FlexCanRegType *obj) +{ + return ((obj->CTRL2 & FLEXCAN_CTRL2_WRMFRZ_MASK) >> FLEXCAN_CTRL2_WRMFRZ_SHIFT); +} + /*! \brief Set freeze mode * * @@ -1569,8 +2038,8 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetFreeRunTimerSrc( { uint32_t tempReg; tempReg = obj->CTRL2; - tempReg &= (~FLEXCAN_CTRL2_TIMER_SRC_MASK); - tempReg |= (((uint32_t)val) << FLEXCAN_CTRL2_TIMER_SRC_SHIFT) & FLEXCAN_CTRL2_TIMER_SRC_MASK; + tempReg &= (~FLEXCAN_CTRL2_TIMERSRC_MASK); + tempReg |= (((uint32_t)val) << FLEXCAN_CTRL2_TIMERSRC_SHIFT) & FLEXCAN_CTRL2_TIMERSRC_MASK; obj->CTRL2 = tempReg; } @@ -1584,7 +2053,7 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetFreeRunTimerSrc( */ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFreeRunTimerSrc(FlexCanRegType *obj) { - return (uint8_t)(((obj->CTRL2) & FLEXCAN_CTRL2_TIMER_SRC_MASK) >> FLEXCAN_CTRL2_TIMER_SRC_SHIFT); + return (uint8_t)(((obj->CTRL2) & FLEXCAN_CTRL2_TIMERSRC_MASK) >> FLEXCAN_CTRL2_TIMERSRC_SHIFT); } /*! \brief Set mailboxes reception priority @@ -1616,6 +2085,72 @@ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetMailboxesRece return (uint8_t)(((obj->CTRL2) & FLEXCAN_CTRL2_MRP_MASK) >> FLEXCAN_CTRL2_MRP_SHIFT); } +/*! \brief Get remote request storing + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: remote request storing + * 0: remote response frame is generated + * 1: remote request frame is stored + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Rrs(const FlexCanRegType *obj) +{ + return ((obj->CTRL2 & FLEXCAN_CTRL2_RRS_MASK) >> FLEXCAN_CTRL2_RRS_SHIFT); +} + +/*! \brief Set remote request storing + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : remote request storing + * 0: remote response frame is generated + * 1: remote request frame is stored + * + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Rrs(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->CTRL2; + + tmp &= ~FLEXCAN_CTRL2_RRS_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_RRS_SHIFT)) & FLEXCAN_CTRL2_RRS_MASK); + obj->CTRL2 = tmp; +} + +/*! \brief Get entire frame arbitration field comparison enable for rx mailboxes + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: entire frame arbitration field comparison enable for rx mailboxes + * 0: rx mailbox filter's IDE bit is always compared and RTR is never + * compared, regardless of mask bits + * 1: enable the comparison of both the IDE and RTR bits of an + * Rx mailbox filter with the corresponding bits of the incoming + * frame. Mask bits do apply + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Eacen(const FlexCanRegType *obj) +{ + return ((obj->CTRL2 & FLEXCAN_CTRL2_EACEN_MASK) >> FLEXCAN_CTRL2_EACEN_SHIFT); +} + +/*! \brief Set entire frame arbitration field comparison enable for rx mailboxes + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : entire frame arbitration field comparison enable for rx mailboxes + * 0: rx mailbox filter's IDE bit is always compared and RTR is never + * compared, regardless of mask bits + * 1: enable the comparison of both the IDE and RTR bits of an + * Rx mailbox filter with the corresponding bits of the incoming + * frame. Mask bits do apply + * + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Eacen(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->CTRL2; + + tmp &= ~FLEXCAN_CTRL2_EACEN_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_EACEN_SHIFT)) & FLEXCAN_CTRL2_EACEN_MASK); + obj->CTRL2 = tmp; +} + /*! \brief Set number of legacy rx fifo filter * * \param[in] obj : pointer to FlexCAN register instance @@ -1641,6 +2176,32 @@ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetLegacyRxFifoF return (uint8_t)(((obj->CTRL2) & FLEXCAN_CTRL2_RFFN_MASK) >> FLEXCAN_CTRL2_RFFN_SHIFT); } +/*! \brief Get Tx arbitration start delay + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: Tx arbitration start delay + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Tasd(const FlexCanRegType *obj) +{ + return ((obj->CTRL2 & FLEXCAN_CTRL2_TASD_MASK) >> FLEXCAN_CTRL2_TASD_SHIFT); +} + +/*! \brief Set Tx arbitration start delay + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : Tx arbitration start delay + * + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Tasd(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->CTRL2; + + tmp &= ~FLEXCAN_CTRL2_TASD_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_TASD_SHIFT)) & FLEXCAN_CTRL2_TASD_MASK); + obj->CTRL2 = tmp; +} + /*! \brief Set bus off done interrupt mask * * \param[in] obj : pointer to FlexCAN register instance @@ -1702,23 +2263,6 @@ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEnhBitTimingE return (uint8_t)(((obj->CTRL2) & FLEXCAN_CTRL2_BTE_MASK) >> FLEXCAN_CTRL2_BTE_SHIFT); } -/*! \brief Set iso fd enable or disable - * - * \param[in] obj : pointer to FlexCAN register instance - * \param[in] enable : iso fd enable - * -1b : enabled - * -0b : disabled - */ -__attribute__((always_inline)) static inline void FlexCanReg_SetIsoFdEnalbe(FlexCanRegType *obj, uint8_t enable) -{ - uint32_t tempReg; - tempReg = obj->CTRL2; - tempReg &= (~FLEXCAN_CTRL2_ISOCANFDEN_MASK); - tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL2_ISOCANFDEN_SHIFT) & FLEXCAN_CTRL2_ISOCANFDEN_MASK; - - obj->CTRL2 = tempReg; -} - /*! \brief Set free running timer base * * \param[in] obj : pointer to FlexCAN register instance @@ -1881,8 +2425,8 @@ __attribute__((always_inline)) static inline void FlexCanReg_ClearBusOffDoneIntF * * \param[in] obj : pointer to FlexCAN register instance * \return: synch status - * - 0 : flexcan is synchronized to the can bus - * - 1 : flexcan is not synchronized to the can bus + * - 0 : flexcan is not synchronized to the can bus + * - 1 : flexcan is synchronized to the can bus * */ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetSynchFlag(FlexCanRegType *obj) @@ -2019,6 +2563,25 @@ __attribute__((always_inline)) static inline void FlexCanReg_ClearEdgeWakeIntFla obj->ESR1 = FLEXCAN_ESR1_WAKINT_MASK; } +/*! \brief Get Rx mailboxes global mask + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: Rx mailboxes global mask + * + */ +__attribute__((always_inline)) static inline uint32_t FlexCanReg_GetRxMailboxGlobalMask(FlexCanRegType *obj) +{ + return obj->RXMGMASK; +} + +/*! \brief Set Rx mailboxes global mask + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] mask : Rx mailboxes global mask + * + */ __attribute__((always_inline)) static inline void FlexCanReg_SetRxMailboxGlobalMask(FlexCanRegType *obj, uint32_t mask) { obj->RXMGMASK = mask; @@ -2432,6 +2995,28 @@ __attribute__((always_inline)) static inline uint32_t FlexCanReg_GetRxFifoGlobal return (obj->RXFGMASK); } +/*! \brief Get identifier acceptance filter hit indicator + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: identifier acceptance filter hit indicator + * + */ +__attribute__((always_inline)) static inline uint16_t FlexCanReg_GetRxfirIdhit(const FlexCanRegType *obj) +{ + return ((obj->RXFIR & FLEXCAN_RXFIR_IDHIT_MASK) >> FLEXCAN_RXFIR_IDHIT_SHIFT); +} + +/*! \brief Get extended bit timing format enable + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: extended bit timing format enable + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetExtendedBitTimingEnable(const FlexCanRegType *obj) +{ + return ((obj->CBT & FLEXCAN_CBT_BTF_MASK) >> FLEXCAN_CBT_BTF_SHIFT); +} + /*! \brief Set Extended bit timing feature * * \param[in] obj : pointer to FlexCAN register instance @@ -2450,6 +3035,17 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetExtendedBitTimin obj->CBT = tempReg; } +/*! \brief Get extended prescaler division factor + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: extended prescaler division factor + * + */ +__attribute__((always_inline)) static inline uint16_t FlexCanReg_GetExtPresalerDivision(const FlexCanRegType *obj) +{ + return ((obj->CBT & FLEXCAN_CBT_EPRESDIV_MASK) >> FLEXCAN_CBT_EPRESDIV_SHIFT); +} + /*! \brief Set Extended presaler div * * \param[in] obj : pointer to FlexCAN register instance @@ -2466,6 +3062,17 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetExtPresalerDivis obj->CBT = tempReg; } +/*! \brief Get extended resync jump width + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: extended resync jump width + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetExtResyncJumpWidth(const FlexCanRegType *obj) +{ + return ((obj->CBT & FLEXCAN_CBT_ERJW_MASK) >> FLEXCAN_CBT_ERJW_SHIFT); +} + /*! \brief Set extended resynce jump width * * \param[in] obj : pointer to FlexCAN register instance @@ -2482,6 +3089,17 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetExtResyncJumpWid obj->CBT = tempReg; } +/*! \brief Get extended propagation segment + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: extended propagation segment + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetExtPorpSeg(const FlexCanRegType *obj) +{ + return ((obj->CBT & FLEXCAN_CBT_EPROPSEG_MASK) >> FLEXCAN_CBT_EPROPSEG_SHIFT); +} + /*! \brief Set extended porp seg * * \param[in] obj : pointer to FlexCAN register instance @@ -2498,6 +3116,17 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetExtPorpSeg(FlexC obj->CBT = tempReg; } +/*! \brief Get extended phase segment 1 + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: extended phase segment 1 + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetExtPhaseSeg1(const FlexCanRegType *obj) +{ + return ((obj->CBT & FLEXCAN_CBT_EPSEG1_MASK) >> FLEXCAN_CBT_EPSEG1_SHIFT); +} + /*! \brief Set extended phase seg1 * * \param[in] obj : pointer to FlexCAN register instance @@ -2514,6 +3143,17 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetExtPhaseSeg1(Fle obj->CBT = tempReg; } +/*! \brief Get extended phase segment 2 + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: extended phase segment 2 + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetExtPhaseSeg2(const FlexCanRegType *obj) +{ + return ((obj->CBT & FLEXCAN_CBT_EPSEG2_MASK) >> FLEXCAN_CBT_EPSEG2_SHIFT); +} + /*! \brief Set extended phase seg2 * * \param[in] obj : pointer to FlexCAN register instance @@ -2603,6 +3243,19 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetNonCorrErrToFrzM obj->MECR = tempReg; } +/*! \brief Get bit rate switch enable + * + * \param[in] obj : pointer to FlexCAN register instance + * \return : bit rate switch enable + * 0: transmit a frame in nominal rate, the BRS bit in the Tx MB has no effect + * 1: transmit a frame with bit rate switching if the BRS bit in the Tx MB is + * recessive + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdRateSwitch(const FlexCanRegType *obj) +{ + return ((obj->FDCTRL & FLEXCAN_FDCTRL_FDRATE_MASK) >> FLEXCAN_FDCTRL_FDRATE_SHIFT); +} + /*! \brief Set fd rate switch * * \param[in] obj : pointer to FlexCAN register instance @@ -2689,6 +3342,19 @@ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetRegionDataSiz return retVal; } +/*! \brief Get bit rate switch enable + * + * \param[in] obj : pointer to FlexCAN register instance + * \return : bit rate switch enable + * 0: transmit a frame in nominal rate, the BRS bit in the Tx MB has no effect + * 1: transmit a frame with bit rate switching if the BRS bit in the Tx MB is + * recessive + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetTdcEnable(const FlexCanRegType *obj) +{ + return ((obj->FDCTRL & FLEXCAN_FDCTRL_TDCEN_MASK) >> FLEXCAN_FDCTRL_TDCEN_SHIFT); +} + /*! \brief Set Transceiver Delay Compensation Enable * * \param[in] obj : pointer to FlexCAN register instance @@ -2706,6 +3372,41 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetTdcEnable(FlexCa obj->FDCTRL = tempReg; } +/*! \brief Get transceiver delay compensation fail + * + * \param[in] obj : pointer to FlexCAN register instance + * \return : transceiver delay compensation fail + * 0: measured loop delay is in range + * 1: transmit a frame with bit rate switching if the BRS bit in the Tx MB is + * recessive + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdctrlTdcfail(const FlexCanRegType *obj) +{ + return ((obj->FDCTRL & FLEXCAN_FDCTRL_TDCFAIL_MASK) >> FLEXCAN_FDCTRL_TDCFAIL_SHIFT); +} + +/*! \brief Clear transceiver delay compensation fail + * + * \param[in] obj : pointer to FlexCAN register instance + */ +__attribute__((always_inline)) static inline void FlexCanReg_ClearFdctrlTdcfail(FlexCanRegType *obj) +{ + uint32_t tmp = obj->FDCTRL; + + tmp |= (((uint32_t)(((uint32_t)(1)) << FLEXCAN_FDCTRL_TDCFAIL_SHIFT)) & FLEXCAN_FDCTRL_TDCFAIL_MASK); + obj->FDCTRL = tmp; +} + +/*! \brief Get transceiver delay compensation offset + * + * \param[in] obj : pointer to FlexCAN register instance + * \return : transceiver delay compensation offset + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdctrlTdcoff(const FlexCanRegType *obj) +{ + return ((obj->FDCTRL & FLEXCAN_FDCTRL_TDCOFF_MASK) >> FLEXCAN_FDCTRL_TDCOFF_SHIFT); +} + /*! \brief Set Transceiver Delay Compensation offset * * \param[in] obj : pointer to FlexCAN register instance @@ -2721,6 +3422,26 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetTdcOffset(FlexCa obj->FDCTRL = tempReg; } +/*! \brief Get transceiver delay compensation value + * + * \param[in] obj : pointer to FlexCAN register instance + * \return : transceiver delay compensation value + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdctrlTdcval(const FlexCanRegType *obj) +{ + return ((obj->FDCTRL & FLEXCAN_FDCTRL_TDCVAL_MASK) >> FLEXCAN_FDCTRL_TDCVAL_SHIFT); +} + +/*! \brief Get fast prescaler division factor + * + * \param[in] obj : pointer to FlexCAN register instance + * \return : fast prescaler division factor + */ +__attribute__((always_inline)) static inline uint16_t FlexCanReg_GetFdPrescalerDivision(const FlexCanRegType *obj) +{ + return ((obj->FDCBT & FLEXCAN_FDCBT_FPRESDIV_MASK) >> FLEXCAN_FDCBT_FPRESDIV_SHIFT); +} + /*! \brief Set CAN FD prescaler div * * \param[in] obj : pointer to FlexCAN register instance @@ -2736,6 +3457,16 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetFdPrescalerDivis obj->FDCBT = tempReg; } +/*! \brief Get fast resync jump width + * + * \param[in] obj : pointer to FlexCAN register instance + * \return : fast resync jump width + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdResyncJumpWidth(const FlexCanRegType *obj) +{ + return ((obj->FDCBT & FLEXCAN_FDCBT_FRJW_MASK) >> FLEXCAN_FDCBT_FRJW_SHIFT); +} + /*! \brief Set CAN FD resync jump width * * \param[in] obj : pointer to FlexCAN register instance @@ -2751,6 +3482,16 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetFdResyncJumpWidt obj->FDCBT = tempReg; } +/*! \brief Get fast propagation segment + * + * \param[in] obj : pointer to FlexCAN register instance + * \return : fast propagation segment + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdPorpSeg(const FlexCanRegType *obj) +{ + return ((obj->FDCBT & FLEXCAN_FDCBT_FPROPSEG_MASK) >> FLEXCAN_FDCBT_FPROPSEG_SHIFT); +} + /*! \brief Set CAN FD porp seg * * \param[in] obj : pointer to FlexCAN register instance @@ -2766,6 +3507,16 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetFdPorpSeg(FlexCa obj->FDCBT = tempReg; } +/*! \brief Get fast phase segment 1 + * + * \param[in] obj : pointer to FlexCAN register instance + * \return : fast phase segment 1 + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdPhaseSeg1(const FlexCanRegType *obj) +{ + return ((obj->FDCBT & FLEXCAN_FDCBT_FPSEG1_MASK) >> FLEXCAN_FDCBT_FPSEG1_SHIFT); +} + /*! \brief Set CAN FD phase seg1 * * \param[in] obj : pointer to FlexCAN register instance @@ -2781,6 +3532,16 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetFdPhaseSeg1(Flex obj->FDCBT = tempReg; } +/*! \brief Get fast phase segment 2 + * + * \param[in] obj : pointer to FlexCAN register instance + * \return : fast phase segment 2 + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdPhaseSeg2(const FlexCanRegType *obj) +{ + return ((obj->FDCBT & FLEXCAN_FDCBT_FPSEG2_MASK) >> FLEXCAN_FDCBT_FPSEG2_SHIFT); +} + /*! \brief Set CAN FD phase seg2 * * \param[in] obj : pointer to FlexCAN register instance @@ -2796,6 +3557,26 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetFdPhaseSeg2(Flex obj->FDCBT = tempReg; } +/*! \brief Get crc mailbox number for FD_TXCRC + * + * \param[in] obj : pointer to FlexCAN register instance + * \return : crc mailbox number for FD_TXCRC + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetFdcrcFdmbcrc(const FlexCanRegType *obj) +{ + return ((obj->FDCRC & CAN_FDCRC_FDMBCRC_MASK) >> CAN_FDCRC_FDMBCRC_SHIFT); +} + +/*! \brief Get extended transmitted CRC value + * + * \param[in] obj : pointer to FlexCAN register instance + * \return : extended transmitted CRC value + */ +__attribute__((always_inline)) static inline uint32_t FlexCanReg_GetFdcrcFdtxcrc(const FlexCanRegType *obj) +{ + return ((obj->FDCRC & CAN_FDCRC_FDTXCRC_MASK) >> CAN_FDCRC_FDTXCRC_SHIFT); +} + /*! \brief Set high resolution extended data phase prescaler division factor * * \param[in] obj : pointer to FlexCAN register instance @@ -3409,6 +4190,19 @@ __attribute__((always_inline)) static inline uint32_t FlexCanReg_GetEnhanceRxFif return obj->ERFFEL[elementId]; } +/*! \brief Get protocol exception enable + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: protocol exception enable + * 0: protocol exception disable + * 1: protocol exception enable + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Prexcen(const FlexCanRegType *obj) +{ + return ((obj->CTRL2 & FLEXCAN_CTRL2_PREXCEN_MASK) >> FLEXCAN_CTRL2_PREXCEN_SHIFT); +} + /*! \brief Sets protocol exception enable * * This function sets protocol exception enable @@ -3427,6 +4221,129 @@ __attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Prexcen(Fle obj->CTRL2 = tmp; } +/*! \brief Get ISO CAN FD enable + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: ISO CAN FD enable + * 0: ISO CAN FD disable + * 1: ISO CAN FD enable + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetIsoFdEnalbe(const FlexCanRegType *obj) +{ + return ((obj->CTRL2 & FLEXCAN_CTRL2_ISOCANFDEN_MASK) >> FLEXCAN_CTRL2_ISOCANFDEN_SHIFT); +} + +/*! \brief Set ISO CAN FD enable + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : ISO CAN FD enable + * 0: ISO CAN FD disable + * 1: ISO CAN FD enable + * + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetIsoFdEnalbe(FlexCanRegType *obj, uint8_t enable) +{ + uint32_t tempReg; + tempReg = obj->CTRL2; + tempReg &= (~FLEXCAN_CTRL2_ISOCANFDEN_MASK); + tempReg |= (((uint32_t)enable) << FLEXCAN_CTRL2_ISOCANFDEN_SHIFT) & FLEXCAN_CTRL2_ISOCANFDEN_MASK; + + obj->CTRL2 = tempReg; +} + +/*! \brief Get edge filter enable + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: edge filter enable + * 0: edge filter enable + * 1: edge filter disable + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCtrl2Edfltdis(const FlexCanRegType *obj) +{ + return ((obj->CTRL2 & FLEXCAN_CTRL2_EDFLTDIS_MASK) >> FLEXCAN_CTRL2_EDFLTDIS_SHIFT); +} + +/*! \brief Set edge filter enable + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : edge filter enable + * 0: edge filter enable + * 1: edge filter disable + * + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetCtrl2Edfltdis(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->CTRL2; + + tmp &= ~FLEXCAN_CTRL2_EDFLTDIS_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_CTRL2_EDFLTDIS_SHIFT)) & FLEXCAN_CTRL2_EDFLTDIS_MASK); + obj->CTRL2 = tmp; +} + +/*! \brief Get lowest priority Tx mailbox + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: lowest priority Tx mailbox + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEsr2Lptm(const FlexCanRegType *obj) +{ + return ((obj->ESR2 & FLEXCAN_ESR2_LPTM_MASK) >> FLEXCAN_ESR2_LPTM_SHIFT); +} + +/*! \brief Get valid priority status + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: valid priority status + * 0: contents of IMB and LPTM are invalid + * 1: contents of IMB and LPTM are valid + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEsr2Vps(const FlexCanRegType *obj) +{ + return ((obj->ESR2 & FLEXCAN_ESR2_VPS_MASK) >> FLEXCAN_ESR2_VPS_SHIFT); +} + +/*! \brief Get Inactive mailbox + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: Inactive mailbox + * 0: if CAN_ESR2.VPS is asserted, CAN_ESR2.LPTM is not an inactive mailbox + * 1: if CAN_ESR2.VPS is asserted, there is at least one inactive maibox. + * CAN_ESR2.LPTM content is the number of the first one + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEsr2Imb(const FlexCanRegType *obj) +{ + return ((obj->ESR2 & FLEXCAN_ESR2_IMB_MASK) >> FLEXCAN_ESR2_IMB_SHIFT); +} + +/*! \brief Get CRC mailbox + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: CRC mailbox, indicats the number of the mailbox corresponding to the value + * in the CAN_CRCR.TXCRC field + * + */ +__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetCrcrMbcrc(const FlexCanRegType *obj) +{ + return ((obj->CRCR & FLEXCAN_CRCR_MBCRC_MASK) >> FLEXCAN_CRCR_MBCRC_SHIFT); +} + +/*! \brief Get transmitted CRC mailbox + * + * \param[in] obj : pointer to FlexCAN register instance + * \return: transmitted CRC mailbox, indicats the CRC value of the last transmitted + * message for non-FD frames + * + */ +__attribute__((always_inline)) static inline uint16_t FlexCanReg_GetCrcrTxcrc(const FlexCanRegType *obj) +{ + return ((obj->CRCR & FLEXCAN_CRCR_TXCRC_MASK) >> FLEXCAN_CRCR_TXCRC_SHIFT); +} + /*! \brief Gets transmit error counter for all errors detected in received message * * This function gets transmit error counter for all errors detected in received message @@ -3439,6 +4356,22 @@ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEcrTxerrcnt(c return ((obj->ECR & FLEXCAN_ECR_TXERRCNT_MASK) >> FLEXCAN_ECR_TXERRCNT_SHIFT); } +/*! \brief Set transmit error counter + * + * + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : transmit error counter + * + */ +__attribute__((always_inline)) static inline void FlexCanReg_SetEcrTxerrcnt(FlexCanRegType *obj, uint8_t value) +{ + uint32_t tmp = obj->ECR; + + tmp &= ~FLEXCAN_ECR_TXERRCNT_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_ECR_TXERRCNT_SHIFT)) & FLEXCAN_ECR_TXERRCNT_MASK); + obj->ECR = tmp; +} + /*! \brief Gets receive error counter for all errors detected in received message * * This function gets receive error counter for all errors detected in received message @@ -3451,28 +4384,20 @@ __attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEcrRxerrcnt(c return ((obj->ECR & FLEXCAN_ECR_RXERRCNT_MASK) >> FLEXCAN_ECR_RXERRCNT_SHIFT); } -/*! \brief Gets transmit error counter for fast bits +/*! \brief Set receive error counter * - * This function gets transmit error counter for fast bits * - * \param[in] obj : pointer to CAN register instance - * \return transmit error counter for fast bits + * \param[in] obj : pointer to FlexCAN register instance + * \param[in] value : receive error counter + * */ -__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEcrTxerrcntfast(const FlexCanRegType *obj) +__attribute__((always_inline)) static inline void FlexCanReg_SetEcrRxerrcnt(FlexCanRegType *obj, uint8_t value) { - return ((obj->ECR & FLEXCAN_ECR_TXERRCNT_FAST_MASK) >> FLEXCAN_ECR_TXERRCNT_FAST_SHIFT); -} + uint32_t tmp = obj->ECR; -/*! \brief Gets receive error counter for fast bits - * - * This function gets receive error counter for fast bits - * - * \param[in] obj : pointer to CAN register instance - * \return receive error counter for fast bits - */ -__attribute__((always_inline)) static inline uint8_t FlexCanReg_GetEcrRxerrcntfast(const FlexCanRegType *obj) -{ - return ((obj->ECR & FLEXCAN_ECR_RXERRCNT_FAST_MASK) >> FLEXCAN_ECR_RXERRCNT_FAST_SHIFT); + tmp &= ~FLEXCAN_ECR_RXERRCNT_MASK; + tmp |= (((uint32_t)(((uint32_t)(value)) << FLEXCAN_ECR_RXERRCNT_SHIFT)) & FLEXCAN_ECR_RXERRCNT_MASK); + obj->ECR = tmp; } #ifdef __cplusplus diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/ftfc_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/ftfc_reg.h index 73701d9..de4a938 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/ftfc_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/ftfc_reg.h @@ -63,9 +63,9 @@ extern "C" { #define FTFC_FSTAT_FL_ERRF_MASK (0x400u) /*!FSTAT & FTFC_FSTAT_EERDY_MASK) >> FTFC_FSTAT_EERDY_SHIFT); + return ((obj->FSTAT & FTFC_FSTAT_EEERDY_MASK) >> FTFC_FSTAT_EEERDY_SHIFT); } /*! \brief Gets the emulated eeprom valid flag @@ -679,6 +679,22 @@ __attribute__((always_inline)) static inline void FtfcReg_SetFstatKeyAl1sF(FtfcR obj->FSTAT = tmp; } +/*! \brief Sets the response error flag + * + * This function sets the response error flag. + * + * \param[in] obj : pointer to FTFC register instance + * \param[in] value : the value of the response error flag + * - 0b : no effect + * - 1b : clear the flag + */ +__attribute__((always_inline)) static inline void FtfcReg_SetFstatRspErrF(FtfcRegType *obj, uint8_t value) +{ + uint32_t tmp = 0; + tmp = (((uint32_t)(((uint32_t)(value)) << FTFC_FSTAT_RSPERR_MASK)) & FTFC_FSTAT_RSPERR_SHIFT); + obj->FSTAT = tmp; +} + /*! \brief Gets the flash ahb bus response error flag * * This function gets the current flash ahb bus response error flag. diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/i2c_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/i2c_reg.h index 71311de..33c2268 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/i2c_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/i2c_reg.h @@ -978,6 +978,9 @@ __attribute__((always_inline)) static inline void I2cReg_SetTxFifoThreshold(I2cR __attribute__((always_inline)) static inline void I2cReg_ClearAllInterruptStatus(I2cRegType *obj) { (void)((obj->CLR_INTR & I2C_CLR_XXX_CLR_REQ_MASK) >> I2C_CLR_XXX_CLR_REQ_SHIFT); + + /* Read back to avoid problem */ + (void)obj->CLR_INTR; } /*! \brief clear interrupt status in the RAW_INTR_STAT @@ -990,6 +993,9 @@ __attribute__((always_inline)) static inline void I2cReg_ClearAllInterruptStatus __attribute__((always_inline)) static inline void I2cReg_ClearRxUnderStatus(I2cRegType *obj) { (void)((obj->CLR_RX_UNDER & I2C_CLR_XXX_CLR_REQ_MASK) >> I2C_CLR_XXX_CLR_REQ_SHIFT); + + /* Read back to avoid problem */ + (void)obj->CLR_RX_UNDER; } /*! \brief clear interrupt status in the RAW_INTR_STAT @@ -1002,6 +1008,9 @@ __attribute__((always_inline)) static inline void I2cReg_ClearRxUnderStatus(I2cR __attribute__((always_inline)) static inline void I2cReg_ClearRxOverStatus(I2cRegType *obj) { (void)((obj->CLR_RX_OVER & I2C_CLR_XXX_CLR_REQ_MASK) >> I2C_CLR_XXX_CLR_REQ_SHIFT); + + /* Read back to avoid problem */ + (void)obj->CLR_RX_OVER; } /*! \brief clear interrupt status in the RAW_INTR_STAT @@ -1014,6 +1023,9 @@ __attribute__((always_inline)) static inline void I2cReg_ClearRxOverStatus(I2cRe __attribute__((always_inline)) static inline void I2cReg_ClearTxOverStatus(I2cRegType *obj) { (void)((obj->CLR_TX_OVER & I2C_CLR_XXX_CLR_REQ_MASK) >> I2C_CLR_XXX_CLR_REQ_SHIFT); + + /* Read back to avoid problem */ + (void)obj->CLR_TX_OVER; } /*! \brief clear interrupt status in the RAW_INTR_STAT @@ -1026,6 +1038,9 @@ __attribute__((always_inline)) static inline void I2cReg_ClearTxOverStatus(I2cRe __attribute__((always_inline)) static inline void I2cReg_ClearReadReqStatus(I2cRegType *obj) { (void)((obj->CLR_RD_REQ & I2C_CLR_XXX_CLR_REQ_MASK) >> I2C_CLR_XXX_CLR_REQ_SHIFT); + + /* Read back to avoid problem */ + (void)obj->CLR_RD_REQ; } /*! \brief clear interrupt status in the RAW_INTR_STAT @@ -1038,6 +1053,9 @@ __attribute__((always_inline)) static inline void I2cReg_ClearReadReqStatus(I2cR __attribute__((always_inline)) static inline void I2cReg_ClearTxAbortStatus(I2cRegType *obj) { (void)((obj->CLR_TX_ABRT & I2C_CLR_XXX_CLR_REQ_MASK) >> I2C_CLR_XXX_CLR_REQ_SHIFT); + + /* Read back to avoid problem */ + (void)obj->CLR_TX_ABRT; } /*! \brief clear interrupt status in the RAW_INTR_STAT @@ -1050,6 +1068,9 @@ __attribute__((always_inline)) static inline void I2cReg_ClearTxAbortStatus(I2cR __attribute__((always_inline)) static inline void I2cReg_ClearRxDoneStatus(I2cRegType *obj) { (void)((obj->CLR_RX_DONE & I2C_CLR_XXX_CLR_REQ_MASK) >> I2C_CLR_XXX_CLR_REQ_SHIFT); + + /* Read back to avoid problem */ + (void)obj->CLR_RX_DONE; } /*! \brief clear interrupt status in the RAW_INTR_STAT @@ -1062,6 +1083,9 @@ __attribute__((always_inline)) static inline void I2cReg_ClearRxDoneStatus(I2cRe __attribute__((always_inline)) static inline void I2cReg_ClearActivityStatus(I2cRegType *obj) { (void)((obj->CLR_ACTIVITY & I2C_CLR_XXX_CLR_REQ_MASK) >> I2C_CLR_XXX_CLR_REQ_SHIFT); + + /* Read back to avoid problem */ + (void)obj->CLR_ACTIVITY; } /*! \brief clear interrupt status in the RAW_INTR_STAT @@ -1074,6 +1098,9 @@ __attribute__((always_inline)) static inline void I2cReg_ClearActivityStatus(I2c __attribute__((always_inline)) static inline void I2cReg_ClearStopBitDetectStatus(I2cRegType *obj) { (void)((obj->CLR_STOP_DET & I2C_CLR_XXX_CLR_REQ_MASK) >> I2C_CLR_XXX_CLR_REQ_SHIFT); + + /* Read back to avoid problem */ + (void)obj->CLR_STOP_DET; } /*! \brief clear interrupt status in the RAW_INTR_STAT @@ -1086,6 +1113,9 @@ __attribute__((always_inline)) static inline void I2cReg_ClearStopBitDetectStatu __attribute__((always_inline)) static inline void I2cReg_ClearStartBitDetectStatus(I2cRegType *obj) { (void)((obj->CLR_START_DET & I2C_CLR_XXX_CLR_REQ_MASK) >> I2C_CLR_XXX_CLR_REQ_SHIFT); + + /* Read back to avoid problem */ + (void)obj->CLR_START_DET; } /*! \brief clear interrupt status in the RAW_INTR_STAT @@ -1098,6 +1128,9 @@ __attribute__((always_inline)) static inline void I2cReg_ClearStartBitDetectStat __attribute__((always_inline)) static inline void I2cReg_ClearGeneralCallStatus(I2cRegType *obj) { (void)((obj->CLR_GEN_CALL & I2C_CLR_XXX_CLR_REQ_MASK) >> I2C_CLR_XXX_CLR_REQ_SHIFT); + + /* Read back to avoid problem */ + (void)obj->CLR_GEN_CALL; } /*! \brief Set module enable @@ -1522,4 +1555,4 @@ __attribute__((always_inline)) static inline uint8_t I2cReg_GetSpikeLen(const I2 } #endif /* extern "C" */ -#endif /* _I2C_REG_H_ */ \ No newline at end of file +#endif /* _I2C_REG_H_ */ diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/port_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/port_reg.h index 8ca9037..966f3fc 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/port_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/port_reg.h @@ -188,6 +188,8 @@ __attribute__((always_inline)) static inline void PortReg_SetPcrIsf(PortRegType tmp &= ~PORT_PCR_ISF_MASK; tmp |= (((uint32_t)(((uint32_t)(value)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK); obj->PCR[pin] = tmp; + /* Read back to avoid problem */ + (void)obj->PCR[pin]; } /*! \brief Gets the Interrupt Configuration diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/uart_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/uart_reg.h index c17cd23..4b1497f 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/uart_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/uart_reg.h @@ -1946,6 +1946,8 @@ __attribute__((always_inline)) static inline bool UartReg_GetErrIsrIsEnabled(con __attribute__((always_inline)) static inline void UartReg_ClearTxBreakDoneFlag(UartRegType *obj) { obj->ICR |= UART_ICR_SBRKDCF_MASK; + /* Read back to avoid problem */ + (void)obj->ICR; } /*! \brief Receiver timeout clear flag @@ -1958,6 +1960,8 @@ __attribute__((always_inline)) static inline void UartReg_ClearTxBreakDoneFlag(U __attribute__((always_inline)) static inline void UartReg_ClearRxTimeoutFlag(UartRegType *obj) { obj->ICR |= UART_ICR_RTOCF_MASK; + /* Read back to avoid problem */ + (void)obj->ICR; } /*! \brief CTS clear flag @@ -1970,6 +1974,8 @@ __attribute__((always_inline)) static inline void UartReg_ClearRxTimeoutFlag(Uar __attribute__((always_inline)) static inline void UartReg_ClearCtsFlag(UartRegType *obj) { obj->ICR |= UART_ICR_CTSCF_MASK; + /* Read back to avoid problem */ + (void)obj->ICR; } /*! \brief LIN break detection result (LBDT_DONE and LBDT_FAIL) clear flag @@ -1982,6 +1988,8 @@ __attribute__((always_inline)) static inline void UartReg_ClearCtsFlag(UartRegTy __attribute__((always_inline)) static inline void UartReg_ClearLinBreakDetectedResultFlag(UartRegType *obj) { obj->ICR |= UART_ICR_LBDTCF_MASK; + /* Read back to avoid problem */ + (void)obj->ICR; } /*! \brief Transmission complete clear flag @@ -1994,6 +2002,8 @@ __attribute__((always_inline)) static inline void UartReg_ClearLinBreakDetectedR __attribute__((always_inline)) static inline void UartReg_ClearTxCompletedFlag(UartRegType *obj) { obj->ICR |= UART_ICR_TCCF_MASK; + /* Read back to avoid problem */ + (void)obj->ICR; } /*! \brief Idle line detected clear flag @@ -2006,6 +2016,8 @@ __attribute__((always_inline)) static inline void UartReg_ClearTxCompletedFlag(U __attribute__((always_inline)) static inline void UartReg_ClearIdlelineDetectedFlag(UartRegType *obj) { obj->ICR |= UART_ICR_IDLECF_MASK; + /* Read back to avoid problem */ + (void)obj->ICR; } /*! \brief Overrun error clear flag @@ -2018,6 +2030,8 @@ __attribute__((always_inline)) static inline void UartReg_ClearIdlelineDetectedF __attribute__((always_inline)) static inline void UartReg_ClearOverRunnErrFlag(UartRegType *obj) { obj->ICR |= UART_ICR_ORECF_MASK; + /* Read back to avoid problem */ + (void)obj->ICR; } /*! \brief Noise detected clear flag @@ -2030,6 +2044,8 @@ __attribute__((always_inline)) static inline void UartReg_ClearOverRunnErrFlag(U __attribute__((always_inline)) static inline void UartReg_ClearNoiseDetectedFlag(UartRegType *obj) { obj->ICR |= UART_ICR_NCF_MASK; + /* Read back to avoid problem */ + (void)obj->ICR; } /*! \brief Framing error clear flag @@ -2042,6 +2058,8 @@ __attribute__((always_inline)) static inline void UartReg_ClearNoiseDetectedFlag __attribute__((always_inline)) static inline void UartReg_ClearFrameErrFlag(UartRegType *obj) { obj->ICR |= UART_ICR_FECF_MASK; + /* Read back to avoid problem */ + (void)obj->ICR; } /*! \brief Parity error clear flag @@ -2054,6 +2072,8 @@ __attribute__((always_inline)) static inline void UartReg_ClearFrameErrFlag(Uart __attribute__((always_inline)) static inline void UartReg_ClearParityErrFlag(UartRegType *obj) { obj->ICR |= UART_ICR_PECF_MASK; + /* Read back to avoid problem */ + (void)obj->ICR; } /*! \brief Baud Rate Regiter @@ -2240,6 +2260,8 @@ __attribute__((always_inline)) static inline uint8_t UartReg_GetTxOverflowFlag(c __attribute__((always_inline)) static inline void UartReg_ClearTxOverflowFlag(UartRegType *obj) { obj->FIFO |= UART_FIFO_TXOF_MASK; + /* Read back to avoid problem */ + (void)obj->FIFO; } /*! \brief Get Receiver Buffer Underflow Flag @@ -2271,6 +2293,8 @@ __attribute__((always_inline)) static inline uint8_t UartReg_GetRxUnderflowFlag( __attribute__((always_inline)) static inline void UartReg_ClearRxUnderflowFlag(UartRegType *obj) { obj->FIFO |= UART_FIFO_RXUF_MASK; + /* Read back to avoid problem */ + (void)obj->FIFO; } /*! \brief Transmit FIFO/Buffer Flush diff --git a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/wdg_reg.h b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/wdg_reg.h index d833411..0e323d6 100644 --- a/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/wdg_reg.h +++ b/cva_asw_m0146/SDK/platform/devices/CVM014x/reg/wdg_reg.h @@ -97,14 +97,6 @@ extern "C" { #define WDG_WIN_LOW_SHIFT (0u) #define WDG_WIN_LOW_WIDTH (8u) -/* CSD Bit Fields */ -#define WDG_CSD_CLK_MASK (0x2u) -#define WDG_CSD_CLK_SHIFT (1) -#define WDG_CSD_CLK_WIDTH (1) -#define WDG_CSD_CFG_MASK (0x1u) -#define WDG_CSD_CFG_SHIFT (0) -#define WDG_CSD_CFG_WIDTH (1) - /* TST Bit Fields */ #define WDG_TST_RST_FLG_MASK (0x8u) #define WDG_TST_RST_FLG_SHIFT (3)