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增加强制boot引脚

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This commit is contained in:
sunbeam 2024-11-09 15:05:39 +08:00
parent 8e8b20623e
commit 3d81a0d86a
11 changed files with 41 additions and 28 deletions
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2
CAN_Bootloader/user/CanThread.aardio
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@ -207,7 +207,7 @@ var FuncSendPackage = function(){
data[i+1] = table.remove(Packdata);
}
CANHw.SendMsg(PackID,data);
//sleep(1);
sleep(0.1);
PackNext += 1;
if(PackNext > 0x2f){
PackNext = 0x20;

2
cva_asw_m0146/SDK/platform/devices/CVM014x/drivers/cpu/startup/system_M014x.h
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@ -36,7 +36,7 @@ extern "C" {
******************************************************************************/
/* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL_CLK_HZ (16000000u)
#define CPU_XTAL_CLK_HZ (8000000u)
#if CPU_XTAL_CLK_HZ > 40000000
#error "The external crystal or oscillator clock frequency is out of range."
#endif

2
cva_asw_m0146/settings/cva_asw_m0146.dnx
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@ -25,8 +25,8 @@
<MemConfigValue>e:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0144.ddf</MemConfigValue>
</PlDriver>
<ArmDriver>
<EnforceMemoryConfiguration>1</EnforceMemoryConfiguration>
<EnableCache>0</EnableCache>
<EnforceMemoryConfiguration>1</EnforceMemoryConfiguration>
</ArmDriver>
<DebugChecksum>
<Checksum>3190234441</Checksum>

10
cva_asw_m0146/settings/cva_asw_m0146.wsdt
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File diff suppressed because one or more lines are too long

7
cva_asw_m0146/src/hwctrl.c
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@ -64,11 +64,12 @@ static void hw_clock_init(McuType *obj)
/* Setup the FIRC2 div2 clock */
clockConfig.gating = true;
clockConfig.source = CLOCKDRV_FIRC;
clockConfig.source = CLOCKDRV_SOSC;
clockConfig.div = 1;
ClockDrv_ConfigureClock(&obj->clockDrv, CLOCKDRV_FIRC_DIV2, &clockConfig);
ClockDrv_ConfigureClock(&obj->clockDrv, CLOCKDRV_SOSC_DIV2, &clockConfig);
/* Setup the SPI clock */
clockConfig.gating = true;
clockConfig.source = CLOCKDRV_PLL_DIV2;

4
cva_bootloader_m0146/SDK/platform/devices/CVM014x/drivers/cpu/startup/system_M014x.c
View File

@ -50,7 +50,7 @@ void SystemInit(void)
#if defined (_USE_EXT_OSC_)
/* Use External oscillator */
AcgReg_SetOscRange(ACG, 3); /* set SOSC frequency range(use max value when SOSC as the clock source of the PLL) */
AcgReg_SetOscRange(ACG, 2); /* set SOSC frequency range(use max value when SOSC as the clock source of the PLL) */
AcgReg_SetEnSosc(ACG, 1); /* enable SOSC */
while(AcgReg_GetStSoscRdy(ACG) == 0); /* wait until SOSC is ready */
@ -66,7 +66,7 @@ void SystemInit(void)
*/
AcgReg_SetPllClkIn(ACG, 2);
AcgReg_SetPllPreDiv(ACG, 0);
AcgReg_SetPllM(ACG, 45);
AcgReg_SetPllM(ACG, 90);
AcgReg_SetPllFbkSel(ACG, 0);
AcgReg_SetPllPosDiv(ACG, 3);
/* SCG PLL configuration:

2
cva_bootloader_m0146/SDK/platform/devices/CVM014x/drivers/cpu/startup/system_M014x.h
View File

@ -36,7 +36,7 @@ extern "C" {
******************************************************************************/
/* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL_CLK_HZ (16000000u)
#define CPU_XTAL_CLK_HZ (8000000u)
#if CPU_XTAL_CLK_HZ > 40000000
#error "The external crystal or oscillator clock frequency is out of range."
#endif

3
cva_bootloader_m0146/cva_bootloader_m0146.ewp
View File

@ -228,6 +228,7 @@
<option>
<name>CCDefines</name>
<state>MCU_CVM0144FMLH</state>
<state>_USE_EXT_OSC_</state>
</option>
<option>
<name>CCPreprocFile</name>
@ -694,7 +695,7 @@
<data>
<extensions></extensions>
<cmdline></cmdline>
<hasPrio>0</hasPrio>
<hasPrio>1</hasPrio>
<buildSequence>inputOutputBased</buildSequence>
</data>
</settings>

2
cva_bootloader_m0146/settings/cva_bootloader_m0146.dnx
View File

@ -80,8 +80,8 @@
<MemConfigValue>e:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0144.ddf</MemConfigValue>
</PlDriver>
<ArmDriver>
<EnableCache>0</EnableCache>
<EnforceMemoryConfiguration>1</EnforceMemoryConfiguration>
<EnableCache>0</EnableCache>
</ArmDriver>
<TerminalIO>
<InputSource>1</InputSource>

18
cva_bootloader_m0146/settings/cva_bootloader_m0146.wsdt
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File diff suppressed because one or more lines are too long

17
cva_bootloader_m0146/src/main.c
View File

@ -810,6 +810,13 @@ int main(void)
PinsDrv_SetPullSel(&mcu.ptb, 5, PINSDRV_INTERNAL_PULL_UP);
PinsDrv_WritePin(&mcu.ptb, 5, 0);
//SIT1021 SLP
PinsDrv_SetMuxModeSel(&mcu.ptd, 7, PINSDRV_MUX_AS_GPIO);
PinsDrv_SetPinDirection(&mcu.ptd, 7, 1);
PinsDrv_WritePin(&mcu.ptd, 7, 1);
PinsDrv_SetMuxModeSel(&mcu.ptc, 2, PINSDRV_MUX_AS_GPIO);
PinsDrv_SetPinDirection(&mcu.ptc, 2, 0);
/* UDS init */
Uds_UserInit(&udsObj, &udsParam);
@ -823,8 +830,8 @@ int main(void)
IrqDrv_EnableGlobalInterrupt();
SEGGER_RTT_printf(0,"gCpuClockFrequency = %d\n",gCpuClockFrequency);
while(1)
{
if(gSystick1msEvent > 0u)
@ -835,7 +842,10 @@ int main(void)
{
SBC_WD_Trigger();
}
if (PinsDrv_ReadPin(&mcu.ptc, 2) == 0)
{
Bootloader_EventEmergeBootRequest(true);
}
if (gSystick1msCnt % 500 == 0)
{
ret = SBC_Read_Command(SBC_WD_CTRL);
@ -863,7 +873,8 @@ int main(void)
}
Bootloader_TimingProcess(1);