跳转有问题
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@ -50,7 +50,7 @@ void SystemInit(void)
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#if defined (_USE_EXT_OSC_)
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#if defined (_USE_EXT_OSC_)
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/* Use External oscillator */
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/* Use External oscillator */
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AcgReg_SetOscRange(ACG, 2); /* set SOSC frequency range(use max value when SOSC as the clock source of the PLL) */
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AcgReg_SetOscRange(ACG, 1); /* set SOSC frequency range(use max value when SOSC as the clock source of the PLL) */
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AcgReg_SetEnSosc(ACG, 1); /* enable SOSC */
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AcgReg_SetEnSosc(ACG, 1); /* enable SOSC */
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while(AcgReg_GetStSoscRdy(ACG) == 0); /* wait until SOSC is ready */
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while(AcgReg_GetStSoscRdy(ACG) == 0); /* wait until SOSC is ready */
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@ -62,7 +62,7 @@ void SystemInit(void)
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* - feedback divider : 45
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* - feedback divider : 45
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* - PLL Feedback clock divider pre-scaler : 1
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* - PLL Feedback clock divider pre-scaler : 1
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* - PLL post-divider setting : 3
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* - PLL post-divider setting : 3
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* Final PLL output frequency is 16M(SOSC) * 45 / 3 / 2 = 120M
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* Final PLL output frequency is 8M(SOSC) * 90 / 3 / 2 = 120M
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*/
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*/
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AcgReg_SetPllClkIn(ACG, 2);
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AcgReg_SetPllClkIn(ACG, 2);
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AcgReg_SetPllPreDiv(ACG, 0);
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AcgReg_SetPllPreDiv(ACG, 0);
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@ -68,13 +68,13 @@ define symbol m_data_2_noinit_end = 0x2000EFFF;
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if (isdefinedsymbol(__stack_size__)) {
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if (isdefinedsymbol(__stack_size__)) {
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define symbol __size_cstack__ = __stack_size__;
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define symbol __size_cstack__ = __stack_size__;
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} else {
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} else {
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define symbol __size_cstack__ = 0x00001000;
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define symbol __size_cstack__ = 0x00002000;
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}
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}
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if (isdefinedsymbol(__heap_size__)) {
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if (isdefinedsymbol(__heap_size__)) {
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define symbol __size_heap__ = __heap_size__;
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define symbol __size_heap__ = __heap_size__;
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} else {
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} else {
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define symbol __size_heap__ = 0x00000400;
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define symbol __size_heap__ = 0x00001000;
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}
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}
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define exported symbol __VECTOR_TABLE = m_interrupts_start;
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define exported symbol __VECTOR_TABLE = m_interrupts_start;
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@ -15,16 +15,16 @@
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<WatchCond>_ 0</WatchCond>
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<WatchCond>_ 0</WatchCond>
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<Watch0>_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0</Watch0>
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<Watch0>_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0</Watch0>
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<Watch1>_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0</Watch1>
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<Watch1>_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0</Watch1>
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<LeaveTargetRunning>_ 0</LeaveTargetRunning>
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<CStepIntDis>_ 0</CStepIntDis>
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<jlinkResetStyle>12</jlinkResetStyle>
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<jlinkResetStyle>12</jlinkResetStyle>
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<jlinkResetStrategy>0</jlinkResetStrategy>
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<jlinkResetStrategy>0</jlinkResetStrategy>
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<TraceBufferSize>0x10000</TraceBufferSize>
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<TraceBufferSize>0x10000</TraceBufferSize>
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<TraceStallIfFIFOFull>0x0</TraceStallIfFIFOFull>
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<TraceStallIfFIFOFull>0x0</TraceStallIfFIFOFull>
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<TracePortSize>0x4</TracePortSize>
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<TracePortSize>0x4</TracePortSize>
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<LeaveTargetRunning>_ 0</LeaveTargetRunning>
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<CStepIntDis>_ 0</CStepIntDis>
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</JLinkDriver>
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</JLinkDriver>
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<DebugChecksum>
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<DebugChecksum>
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<Checksum>968150740</Checksum>
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<Checksum>3131505811</Checksum>
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</DebugChecksum>
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</DebugChecksum>
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<Trace1>
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<Trace1>
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<Enabled>0</Enabled>
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<Enabled>0</Enabled>
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@ -80,8 +80,8 @@
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<MemConfigValue>E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0144.ddf</MemConfigValue>
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<MemConfigValue>E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0144.ddf</MemConfigValue>
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</PlDriver>
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</PlDriver>
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<ArmDriver>
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<ArmDriver>
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<EnableCache>0</EnableCache>
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<EnforceMemoryConfiguration>1</EnforceMemoryConfiguration>
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<EnforceMemoryConfiguration>1</EnforceMemoryConfiguration>
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<EnableCache>0</EnableCache>
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</ArmDriver>
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</ArmDriver>
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<TerminalIO>
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<TerminalIO>
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<InputSource>1</InputSource>
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<InputSource>1</InputSource>
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@ -155,15 +155,6 @@
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<ShowTimeSum>1</ShowTimeSum>
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<ShowTimeSum>1</ShowTimeSum>
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<SumSortOrder>0</SumSortOrder>
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<SumSortOrder>0</SumSortOrder>
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</EventLog>
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</EventLog>
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<PowerProbe>
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<Frequency>10000</Frequency>
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<Probe0>I0</Probe0>
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<ProbeSetup0>2 1 1 2 0 0</ProbeSetup0>
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</PowerProbe>
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<TermIOLog>
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<LoggingEnabled>_ 0</LoggingEnabled>
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<LogFile>_ ""</LogFile>
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</TermIOLog>
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<DisassembleMode>
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<DisassembleMode>
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<mode>0</mode>
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<mode>0</mode>
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</DisassembleMode>
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</DisassembleMode>
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@ -172,8 +163,17 @@
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<Bp1>_ 1 "EMUL_CODE" "{$PROJ_DIR$\SDK\middleware\uds\user\uds_service37.c}.67.13" 0 0 1 "" 0 "" 0</Bp1>
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<Bp1>_ 1 "EMUL_CODE" "{$PROJ_DIR$\SDK\middleware\uds\user\uds_service37.c}.67.13" 0 0 1 "" 0 "" 0</Bp1>
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<Count>2</Count>
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<Count>2</Count>
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</Breakpoints2>
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</Breakpoints2>
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<TermIOLog>
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<LoggingEnabled>_ 0</LoggingEnabled>
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<LogFile>_ ""</LogFile>
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</TermIOLog>
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<Aliases>
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<Aliases>
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<Count>0</Count>
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<Count>0</Count>
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<SuppressDialog>0</SuppressDialog>
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<SuppressDialog>0</SuppressDialog>
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</Aliases>
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</Aliases>
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<PowerProbe>
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<Frequency>10000</Frequency>
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<Probe0>I0</Probe0>
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<ProbeSetup0>2 1 1 2 0 0</ProbeSetup0>
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</PowerProbe>
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</settings>
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</settings>
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File diff suppressed because one or more lines are too long
@ -33,9 +33,9 @@ extern "C" {
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* the defines
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* the defines
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******************************************************************************/
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******************************************************************************/
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/* If want to Generate flash driver code in ram, enable the configuration; if not, disable the configuration */
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/* If want to Generate flash driver code in ram, enable the configuration; if not, disable the configuration */
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#define BOOTLOADER_CFG_FLS_CODE_GENERATE_EN (0u)
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#define BOOTLOADER_CFG_FLS_CODE_GENERATE_EN (1u)
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/* Copy flash driver from flash to ram to run if don't get flash driver from out side, only just for debug the flash driver */
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/* Copy flash driver from flash to ram to run if don't get flash driver from out side, only just for debug the flash driver */
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#define BOOTLOADER_CFG_FLS_COPY_AUTO_EN (0u)
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#define BOOTLOADER_CFG_FLS_COPY_AUTO_EN (1u)
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/* Indication value with boot loader request from asw */
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/* Indication value with boot loader request from asw */
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#define BOOTLOADER_CFG_REQ_ACTIVE (0x55AAAA55ul)
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#define BOOTLOADER_CFG_REQ_ACTIVE (0x55AAAA55ul)
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@ -66,7 +66,7 @@ extern "C" {
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#define BOOTLOADER_CFG_FLS_DRV_RAM_CODE_SIZE (BOOTLOADER_CFG_FLS_DRV_RAM_CRC_ADDR - BOOTLOADER_CFG_FLS_DRV_RAM_START_ADDR)
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#define BOOTLOADER_CFG_FLS_DRV_RAM_CODE_SIZE (BOOTLOADER_CFG_FLS_DRV_RAM_CRC_ADDR - BOOTLOADER_CFG_FLS_DRV_RAM_START_ADDR)
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/* The max time stay in boot before can jump to App, unit: ms */
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/* The max time stay in boot before can jump to App, unit: ms */
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#define BOOTLOADER_CFG_BOOT_DURATION_MS (50u)
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#define BOOTLOADER_CFG_BOOT_DURATION_MS (10u)
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/* Erased all sector */
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/* Erased all sector */
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#define BOOTLOADER_CFG_ERASE_ALL (0xFFFFFFFF)
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#define BOOTLOADER_CFG_ERASE_ALL (0xFFFFFFFF)
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@ -98,6 +98,8 @@ typedef struct
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#pragma location = ".no_init"
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#pragma location = ".no_init"
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static uint32_t sBootloader_Req;
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static uint32_t sBootloader_Req;
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#pragma location = ".no_init"
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static uint32_t reboot_times;
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#pragma location = ".bootloaderInfo"
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#pragma location = ".bootloaderInfo"
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__root const Bootloade_CfgInfoType sBootloader_Version = {
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__root const Bootloade_CfgInfoType sBootloader_Version = {
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@ -439,6 +441,8 @@ void SysTick_Handler(void)
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Uds_Tick(&udsObj);
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Uds_Tick(&udsObj);
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}
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}
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void CAN0_ERxFIFO_Handler(void)
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void CAN0_ERxFIFO_Handler(void)
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{
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{
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if(FlexCanDrv_GetEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_DAIE) == true)
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if(FlexCanDrv_GetEnhanceRxFFIsrFlag(flexCanDrv_DemoObj, FLEXCANDRV_ENHANCERXFF_ISR_SRC_DAIE) == true)
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@ -750,6 +754,36 @@ static void ResetS3Timer(UdsType *obj)
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{
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{
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obj->s3ServerTimer.counter = 0;
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obj->s3ServerTimer.counter = 0;
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}
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}
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uint8_t ExtraBootInitFlag,ExtraBootInitDelay;
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static void ExtraBootInit(void)
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{
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uint32_t tTcr = 0;
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ClockDrv_ModuleClkConfigType clockConfig;
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/* Setup the Pll div2 clock */
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clockConfig.gating = true;
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clockConfig.source = CLOCKDRV_PLL;
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clockConfig.div = 1;
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ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PLL_DIV2, &clockConfig);
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/* Setup the SPI clock */
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clockConfig.gating = true;
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clockConfig.source = CLOCKDRV_PLL_DIV2;
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ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_SPI2, &clockConfig);
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tTcr = SpiReg_GetTcr((const SpiRegType *)&mcu.spiDrv2.reg);
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SpiDrv_SetPrescaler(&tTcr,0x03);
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//SEGGER_RTT_printf(0,"ret = %d\n",ret);
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//SEGGER_RTT_printf(0,"-----SBC_SPI_INIT-----\n");
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SBC_SPI_INIT();
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SBC_Init();
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}
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int main(void)
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int main(void)
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{
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{
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FlexCan_FrameStructureType rxMsg;
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FlexCan_FrameStructureType rxMsg;
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@ -757,8 +791,19 @@ int main(void)
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ClockDrv_ModuleClkConfigType clockConfig;
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ClockDrv_ModuleClkConfigType clockConfig;
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uint32_t ret;
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uint32_t ret;
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uint32_t rollingcounter,temp;
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uint32_t rollingcounter,temp;
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uint32_t tTcr = 0;
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if((reboot_times>>16) != 0x55AA)
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{
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reboot_times = 0x55AA0000;
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}
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else
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{
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reboot_times++;
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}
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ExtraBootInitFlag = 0;
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ExtraBootInitDelay = 0;
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IrqDrv_DisableGlobalInterrupt();
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IrqDrv_DisableGlobalInterrupt();
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/* Initialize all MCU drivers: flash drv included */
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/* Initialize all MCU drivers: flash drv included */
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@ -781,29 +826,7 @@ int main(void)
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ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTD, &clockConfig);
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ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTD, &clockConfig);
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ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTE, &clockConfig);
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ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTE, &clockConfig);
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/* Setup the Pll div2 clock */
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clockConfig.gating = true;
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clockConfig.source = CLOCKDRV_PLL;
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clockConfig.div = 1;
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ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PLL_DIV2, &clockConfig);
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/* Setup the SPI clock */
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clockConfig.gating = true;
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clockConfig.source = CLOCKDRV_PLL_DIV2;
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ret = ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_SPI2, &clockConfig);
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tTcr = SpiReg_GetTcr((const SpiRegType *)&mcu.spiDrv2.reg);
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SpiDrv_SetPrescaler(&tTcr,0x03);
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//SEGGER_RTT_printf(0,"ret = %d\n",ret);
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//SEGGER_RTT_printf(0,"-----SBC_SPI_INIT-----\n");
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SBC_SPI_INIT();
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SBC_Init();
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//SBC_Mode_Normal();
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//SBC_Mode_Normal();
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/* get CAN controller default configuration */
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/* get CAN controller default configuration */
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@ -836,23 +859,47 @@ int main(void)
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IrqDrv_EnableGlobalInterrupt();
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IrqDrv_EnableGlobalInterrupt();
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SEGGER_RTT_printf(0,"gCpuClockFrequency = %d\n",gCpuClockFrequency);
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//SEGGER_RTT_printf(0,"gCpuClockFrequency = %d\n",gCpuClockFrequency);
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SEGGER_RTT_printf(0,"reboot_times = %d\n",(reboot_times&0xff));
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uint32_t reset_src = mcu.resetDrv.rcmReg->RST_FLAG;
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SEGGER_RTT_printf(0,"reset_src = %08x\n",reset_src);
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if ((reboot_times&0xff) > 5)
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{
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Bootloader_EventEmergeBootRequest(true);
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}
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while(1)
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while(1)
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{
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{
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if(gSystick1msEvent > 0u)
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if(gSystick1msEvent > 0u)
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{
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{
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gSystick1msEvent = 0;
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gSystick1msEvent = 0;
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gSystick1msCnt++;
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gSystick1msCnt++;
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if (ExtraBootInitFlag == 0)
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{
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if (ExtraBootInitDelay < BOOTLOADER_CFG_BOOT_DURATION_MS)
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{
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ExtraBootInitDelay++;
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}
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else
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{
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ExtraBootInitDelay = 0;
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ExtraBootInitFlag = 1;
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ExtraBootInit();
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}
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}
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if (gSystick1msCnt % 10 == 0)
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if (gSystick1msCnt % 10 == 0)
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{
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{
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SBC_WD_Trigger();
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if (ExtraBootInitFlag == 1)
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{
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SBC_WD_Trigger();
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}
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}
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}
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if (PinsDrv_ReadPin(&mcu.ptc, 2) == 0)
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if (PinsDrv_ReadPin(&mcu.ptc, 2) == 0)
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{
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{
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Bootloader_EventEmergeBootRequest(true);
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Bootloader_EventEmergeBootRequest(true);
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}
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}
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if (gSystick1msCnt % 500 == 0)
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if (gSystick1msCnt % 1000 == 0)
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{
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{
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ret = SBC_Read_Command(SBC_WD_CTRL);
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ret = SBC_Read_Command(SBC_WD_CTRL);
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SEGGER_RTT_printf(0,"%04d : SBC_WD_CTRL = %x\n",rollingcounter++,ret);
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SEGGER_RTT_printf(0,"%04d : SBC_WD_CTRL = %x\n",rollingcounter++,ret);
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@ -637,6 +637,7 @@ void IsoTp_HandleIncomingCanMsg(IsoTpType *obj, uint32_t id, const uint8_t *data
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/* If wrong SN */
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/* If wrong SN */
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if(ISOTP_RET_WRONG_SN == ret)
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if(ISOTP_RET_WRONG_SN == ret)
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{
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{
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TxTestMsg(&msg.byte);
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obj->receiveProtocolResult = ISOTP_PROTOCOL_RESULT_WRONG_SN;
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obj->receiveProtocolResult = ISOTP_PROTOCOL_RESULT_WRONG_SN;
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obj->receiveStatus = ISOTP_RECEIVE_STATUS_IDLE;
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obj->receiveStatus = ISOTP_RECEIVE_STATUS_IDLE;
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break;
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break;
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#define BYTES_OF(x) (sizeof(x) / sizeof(uint8_t))
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#define BYTES_OF(x) (sizeof(x) / sizeof(uint8_t))
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#define UDS_RSP_LEN_MAX (512)
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#define UDS_RSP_LEN_MAX (64)
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/* DID type */
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/* DID type */
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#define UDS_VAR_TYPE_NONVOL_STORAGE (1 << 0) /* set if non-volatile data */
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#define UDS_VAR_TYPE_NONVOL_STORAGE (1 << 0) /* set if non-volatile data */
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@ -136,7 +136,7 @@ void UdsService36_TransferData(UdsType *obj, const uint8_t msgBuf[], uint16_t ms
|
|||||||
|
|
||||||
rspBuffer[0] = UDS_GET_POSITIVE_RSP(0x36);
|
rspBuffer[0] = UDS_GET_POSITIVE_RSP(0x36);
|
||||||
rspBuffer[1] = s_curRcvSequence;
|
rspBuffer[1] = s_curRcvSequence;
|
||||||
Uds_PositiveResponse(obj, rspBuffer, 2);
|
//Uds_PositiveResponse(obj, rspBuffer, 2);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
case UDS_TRANSFER_DIR_UPLOAD:
|
case UDS_TRANSFER_DIR_UPLOAD:
|
||||||
|
Loading…
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Reference in New Issue
Block a user