MCU name: RL78/F13(ROM:128KB)
Chip name: R5F10BGG

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Module	Macro	Sub	Setting	Status
Clock Generator				Used
	CGC			Used
			PIOR00 / TI00	P17
			PIOR01 / TI01	P30
			PIOR02 / TI02	P16
			PIOR03 / TI03	P125
			PIOR04 / TI04	P13
			PIOR05 / TI05	P15
			PIOR06 / TI06	P14
			PIOR07 / TI07	P120
			PIOR10 / TO00	P17
			PIOR11 / TO01	P30
			PIOR12 / TO02	P16
			PIOR13 / TO03	P125
			PIOR14 / TO04	P13
			PIOR15 / TO05	P15
			PIOR16 / TO06	P14
			PIOR17 / TO07	P120
			PIOR40 / RXD0/SI00/SDA00	P16
			PIOR40 / TXD0/SO00	P15
			PIOR40 / _SCK00/SCL00	P17
			PIOR40 / _SSI00	P30
			PIOR41 / SO01	P120
			PIOR41 / SI01	P13
			PIOR41 / _SCK01	P14
			PIOR41 / _SSI01	P125
			PIOR41 / SCL01	P14
			PIOR41 / SDA01	P13
			PIOR42 / RXD1	P11
			PIOR42 / TXD1	P12
			PIOR42 / SO10	P12
			PIOR42 / SI10	P11
			PIOR42 / _SCK10	P10
			PIOR42 / SCL10	P10
			PIOR42 / SDA10	P11
			PIOR43 / SO11	P72
			PIOR43 / SI11	P70
			PIOR43 / _SCK11	P71
			PIOR43 / _SSI11	P73
			PIOR43 / SCL11	P71
			PIOR43 / SDA11	P70
			PIOR44 / LTxD0	P13
			PIOR44 / LRxD0	P14
			PIOR46 / CTxD0	P10
			PIOR46 / CRxD0	P11
			PIOR50 / KR0	P70
			PIOR50 / KR1	P71
			PIOR50 / KR2	P72
			PIOR50 / KR3	P73
			PIOR50 / KR4	-
			PIOR50 / KR5	-
			PIOR50 / KR6	-
			PIOR50 / KR7	-
			PIOR52 / INTP2	P31
			PIOR53 / INTP3	P17
			PIOR70 / TRDCLK0/TRDIOA0	P13
			PIOR71 / TRDIOB0	P125
			PIOR73 / TRDIOD0	P120
			Operation mode setting	High speed main mode 4.0 (V) ¡Ü VDD ¡Ü 5.5 (V)
			Main system clock (fMAIN) setting	High-speed system clock (fMX)
			fIH operation	Used
			fIH frequency	32(MHz)
			fMX operation	Used
			High-speed system clock setting	X1 oscillation (fX)
			fMX frequency	8(MHz)
			Stable time	32768 (2^18/fX)(¦Ìs)
			fPLL operation	Used
			fPLL frequency	32(MHz)
			Lockup wait counter	64 (2^9/fMAIN)(¦Ìs)
			PLL output for main system clock (fMP) setting	32 (fPLL)(MHz)
			fSUB operation	Unused
			Internal low-speed oscillation clock (fIL) setting	15(kHz)
			Low speed on-chip oscillator clock (fSL) setting	15 (fIL)(kHz)
			WDT operation clock (fWDT) setting	15(kHz)
			RTC operation clock	65.57 (fMX/122)(kHz)
			Timer RD operation clock	32000 (fCLK)(kHz)
			CPU and peripheral clock (fCLK)	32000 (fMP)(kHz)
			On-chip debug operation setting	Unused
			Security ID setting	Used
			Security ID	0x00000000000000000000
			Output the function for confirming reset source	Used
			RESOUT pin setting	P130 used as port pin
			Illegal memory access detection function setting	Unused
			RAM guard function setting	Unused
			Port register guard function setting	Unused
			Interrupt register guard function setting	Unused
			Chip state control register guard function setting	Unused
			Detection of 1 bit error detection interrupt (INTRAM)	Unused
			CPU stack pointer monitor function setting	Unused
			Clock monitor function setting	Unused
			Data flash access control setting	Disables data flash access
			Setting of data flash library	Unused
Port				Used
	PORT			Used
		P00
			Mode	Out
			output value	0
		P12
			Mode	In
			Pull-up	Unused
		P13
			Mode	Out
			N-ch	Unused
			output value	0
		P14
			Mode	Out
			N-ch	Unused
			output value	0
		P15
			Mode	Out
			N-ch	Unused
			output value	0
		P17
			Mode	Out
			N-ch	Unused
			output value	0
		P30
			Mode	In
			Pull-up	Unused
			Schmitt1 buffer	Used
		P60
			Mode	In
			Pull-up	Unused
			Schmitt1 buffer	Used
		P61
			Mode	In
			Pull-up	Unused
			Schmitt1 buffer	Used
		P62
			Mode	In
			Pull-up	Unused
			Schmitt1 buffer	Used
		P63
			Mode	In
			Pull-up	Unused
			Schmitt1 buffer	Used
		P72
			Mode	Out
			N-ch	Unused
			output value	0
		P73
			Mode	Out
			output value	0
		P130
			Mode	Out
			output value	0
		P140
			Mode	Out
			output value	0
Interrupt				Used
	INTP			Used
		INTP0
			Valid edge	Rising
			Priority	Low
		INTP1
			Valid edge	Rising
			Priority	Low
		INTP2
			Valid edge	Rising
			Priority	Low
		INTP4
			Valid edge	Rising
			Priority	Low
			Requests to the interrupt control circuit are enabled	Used
		INTP6
			Valid edge	Rising
			Priority	Low
			Requests to the interrupt control circuit are enabled	Used
		INTP7
			Valid edge	Rising
			Priority	Low
		INTP8
			Valid edge	Falling
			Priority	Low
	KEY			Unused
Serial				Unused
A/D Converter				Used
	ADC			Used
			A/D convertor operation setting	Used
			Comparator operation setting	Operation
			Resolution setting	10 bits
			VREF(+) setting	VDD
			VREF(-) setting	VSS
			Trigger mode setting	Hardware trigger wait mode
			Hardware trigger wait mode	INTTM01
			Operation mode setting	One-shot select mode
			ANI0 - ANI12 analog input selection	ANI0 - ANI10
			ANI24 - ANI25 analog input selection	ANI26, ANI27, ANI28, ANI29, ANI30
			A/D channel selection	ANI2
			Conversion time mode	Normal 1
			Conversion time	27 (864/fCLK)(¦Ìs)
			Conversion result upper/lower bound value setting	Generates an interrupt request (INTAD) when ADLL ¡Ü ADCRH ¡Ü ADUL
			Upper bound (ADUL) value	255
			Lower bound (ADLL) value	0
			Use A/D interrupt (INTAD)	Used
			Priority	Low
Timer				Used
	TAU0			Used
		Channel0
			Channel 0	Interval timer
			Interval value (16 bits)	1000¦Ìs, (Actual value: 1000)
			Generates INTTM00 when counting is started	Unused
			End of timer channel 0 count, generate an interrupt (INTTM00)	Used
			Priority (INTTM00)	Low
		Channel1
			Channel 1	Interval timer
			Operation mode setting	16 bits
			Interval value (16 bits)	100¦Ìs, (Actual value: 100)
			Generates INTTM01 when counting is started	Unused
			End of timer channel 1 count, generate an interrupt (INTTM01)	Used
			Priority (INTTM01)	Low
	TAU1			Unused
	TMRJ0			Unused
	TMRD0			Unused
	TMRD1			Unused
Watchdog Timer				Unused
Real-time Clock				Unused
Data Transfer Controller				Unused
Clock Output/Buzzer Output				Unused
Voltage Detector				Used
	LVD			Used
			Low voltage detector operation setting	Used
			Operation mode setting	Reset mode
			Reset generation level (VLVD)	4.32(V)