125 lines
5.1 KiB
C
125 lines
5.1 KiB
C
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/***********************************************************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
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* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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* applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
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* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
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* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
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* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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*
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* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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* File Name : r_cg_cgc.c
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* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021]
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* Device(s) : R5F10BGG
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* Tool-Chain : CCRL
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* Description : This file implements device driver for CGC module.
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* Creation Date: 2024/7/7
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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Includes
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***********************************************************************************************************************/
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#include "r_cg_macrodriver.h"
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#include "r_cg_cgc.h"
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/* Start user code for include. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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#include "r_cg_userdefine.h"
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/***********************************************************************************************************************
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Pragma directive
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***********************************************************************************************************************/
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/* Start user code for pragma. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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/***********************************************************************************************************************
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Global variables and functions
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***********************************************************************************************************************/
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/* Start user code for global. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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/***********************************************************************************************************************
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* Function Name: R_CGC_Create
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* Description : This function initializes the clock generator.
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* Arguments : None
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* Return Value : None
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***********************************************************************************************************************/
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void R_CGC_Create(void)
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{
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volatile uint32_t w_count;
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uint8_t temp_stab_set;
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uint8_t temp_stab_wait;
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/* Set fSL */
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SELLOSC = 1U;
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/* Set fMX */
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CMC = _40_CGC_HISYS_OSC | _00_CGC_SUB_PORT | _00_CGC_SYSOSC_UNDER10M | _00_CGC_SUBMODE_DEFAULT;
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OSTS = _07_CGC_OSCSTAB_SEL18;
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MSTOP = 0U;
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temp_stab_set = _FF_CGC_OSCSTAB_STA18;
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do
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{
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temp_stab_wait = OSTC;
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temp_stab_wait &= temp_stab_set;
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}
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while (temp_stab_wait != temp_stab_set);
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/* Set fMAIN */
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MCM0 = 1U;
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while (MCS == 0U)
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{
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;
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}
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/* Set fPLL */
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PLLCTL = _80_CGC_LOCKUP_WAIT_9 | _00_CGC_PLL_BELOW_32MHZ | _10_CGC_PLL_DIVISION_4 | _02_CGC_PLL_MULTIPLY_X16;
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/* Change the waiting time according to the system */
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for (w_count = 0U; w_count <= CGC_PLLWAITTIME; w_count++)
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{
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NOP();
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}
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PLLON = 1U;
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while ((PLLSTS & 0x80U) == 0U)
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{
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;
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}
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MDIV = _00_CGC_FMP_DIV_DEFAULT;
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/* Set fMP to PLL clock select mode */
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SELPLL = 1U;
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while ((PLLSTS & 0x88U) != 0x88U)
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{
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;
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}
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/* Set fSUB */
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XTSTOP = 1U;
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/* Set fCLK */
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CSS = 0U;
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/* Set fIH */
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HIOSTOP = 0U;
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/* Set RTC clock source */
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RTCCL = _00_CGC_RTC_FMX;
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RTCCL |= _42_CGC_RTC_DIV122;
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/* Set Timer RD clock source to fCLK, fMP */
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TRD_CKSEL = 0U;
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}
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/* Start user code for adding. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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