LL01/code_app_out/Source/module/pwm_manage/pwm_manage.c

/**
* @file:	 pwm_manage.c
* @brief:
* @author:	mingyea
* @version: V1.0.0
* @date:	 2016-03-22
* @history:
*	   1.
*  author:
*  version:
*  date:
*/



#include "pwm_manage.h"
#include "tim.h"
#include "gpio.h"

void pwm_manage_channel_init(u8 base_id, u8 channel_id);
void pwm_manage_channel_deinit(u8 base_id, u8 channel_id);

#if 0
//此数组可配置--表示把哪个通道，用做pwm，1使能 0不使能
const u8 g_pwm_array_channel_en_tab[PWM_PYH_TOTAL_CHANNEL] =
{
	{PHY_PWM_CHANNEL_ATM_CH1_EN},  //ATM CH1
	{PHY_PWM_CHANNEL_ATM_CH2_EN},  //ATM_CH2
	{PHY_PWM_CHANNEL_ATM_CH3_EN},	//ATM_CH3
	{PHY_PWM_CHANNEL_ATM_CH4_EN},	//ATM_CH4
	{PHY_PWM_CHANNEL_GPTM0_CH1_EN},	//GPTM0_CH1
	{PHY_PWM_CHANNEL_GPTM0_CH2_EN},	//GPTM0_CH2
	{PHY_PWM_CHANNEL_GPTM0_CH3_EN},	//GPTM0_CH3
	{PHY_PWM_CHANNEL_GPTM0_CH4_EN},	//GPTM0_CH4
	{PHY_PWM_CHANNEL_GPTM1_CH1_EN},	//GPTM1_CH1
	{PHY_PWM_CHANNEL_GPTM1_CH2_EN},	//GPTM1_CH2
	{PHY_PWM_CHANNEL_GPTM1_CH3_EN},	//GPTM1_CH3
	{PHY_PWM_CHANNEL_GPTM1_CH4_EN},	//GPTM1_CH4
};
#endif

//此数组不改动
const pwm_cfg_tab_s g_pwm_array_channel_tab[PWM_PYH_TOTAL_CHANNEL] =
{
	{PWM_BASE_ID_ATM,1},  //ATM CH1
	{PWM_BASE_ID_ATM,2},  //ATM_CH2
	{PWM_BASE_ID_ATM,3},	//ATM_CH3
	{PWM_BASE_ID_ATM,4},	//ATM_CH4
	{PWM_BASE_ID_GPTM0,1},	//GPTM0_CH1
	{PWM_BASE_ID_GPTM0,2},	//GPTM0_CH2
	{PWM_BASE_ID_GPTM0,3},	//GPTM0_CH3
	{PWM_BASE_ID_GPTM0,4},	//GPTM0_CH4
	{PWM_BASE_ID_GPTM1,1},	//GPTM1_CH1
	{PWM_BASE_ID_GPTM1,2},	//GPTM1_CH2
	{PWM_BASE_ID_GPTM1,3},	//GPTM1_CH3
	{PWM_BASE_ID_GPTM1,4},	//GPTM1_CH4
	{PWM_BASE_ID_GPTM2,1},	//GPTM2_CH1
	{PWM_BASE_ID_GPTM2,2},	//GPTM2_CH2
	{PWM_BASE_ID_GPTM2,3},	//GPTM2_CH3
	{PWM_BASE_ID_GPTM2,4},	//GPTM2_CH4
	{PWM_BASE_ID_LPT32,1},	//LPT32_CH1
	{PWM_BASE_ID_LPT32,2},	//LPT32_CH2
	{PWM_BASE_ID_LPT32,3},	//LPT32_CH3
	{PWM_BASE_ID_LPT32,4},	//LPT32_CH4
};

u8 g_lpt32_ch_flag[4] ={0u};

/**
* @brief 初始化
* @retval none
*/
void pwm_manage_atm_init(void)
{
	#if (PHY_PWM_CHANNEL_ATM_CH1_EN !=0u)
	FL_ATIM_OC_Init(ATIM, FL_ATIM_CHANNEL_1, (FL_ATIM_OC_InitTypeDef*)&g_atmer0_ch1_InitStructer);
	FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_1);
	#endif

	#if (PHY_PWM_CHANNEL_ATM_CH2_EN !=0u)
	FL_ATIM_OC_Init(ATIM, FL_ATIM_CHANNEL_2, (FL_ATIM_OC_InitTypeDef*)&g_atmer0_ch2_InitStructer);
	FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_2);
	#endif

	#if (PHY_PWM_CHANNEL_ATM_CH3_EN !=0u)
	FL_ATIM_OC_Init(ATIM, FL_ATIM_CHANNEL_3, (FL_ATIM_OC_InitTypeDef*)&g_atmer0_ch3_InitStructer);
	FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_3);
	#endif

	#if (PHY_PWM_CHANNEL_ATM_CH4_EN !=0u)
	FL_ATIM_OC_Init(ATIM, FL_ATIM_CHANNEL_4, (FL_ATIM_OC_InitTypeDef*)&g_atmer0_ch4_InitStructer);
	FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_4);
	#endif

	#if (PHY_PWM_CHANNEL_ATM_CH1_EN !=0u) || (PHY_PWM_CHANNEL_ATM_CH2_EN !=0u) || (PHY_PWM_CHANNEL_ATM_CH3_EN !=0u) || (PHY_PWM_CHANNEL_ATM_CH4_EN !=0u)
	FL_ATIM_BDTR_Init(ATIM, (FL_ATIM_BDTR_InitTypeDef*)&g_atimer0_bdtr_config);
	#endif
}

/**
* @brief 初始化
* @retval none
*/
void pwm_manage_gptm0_init(void)
{
	#if (PHY_PWM_CHANNEL_GPTM0_CH1_EN !=0u)
	FL_GPTIM_OC_Init(GPTIM0, FL_GPTIM_CHANNEL_1, (FL_GPTIM_OC_InitTypeDef*)&g_gptim_ch1_cfg);
	FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_1);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM0_CH2_EN !=0u)
	FL_GPTIM_OC_Init(GPTIM0, FL_GPTIM_CHANNEL_2, (FL_GPTIM_OC_InitTypeDef*)&g_gptim_ch2_cfg);
	FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_2);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM0_CH3_EN !=0u)
	FL_GPTIM_OC_Init(GPTIM0, FL_GPTIM_CHANNEL_3, (FL_GPTIM_OC_InitTypeDef*)&g_gptim_ch3_cfg);
	FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_3);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM0_CH4_EN !=0u)
	FL_GPTIM_OC_Init(GPTIM0, FL_GPTIM_CHANNEL_4, (FL_GPTIM_OC_InitTypeDef*)&g_gptim_ch4_cfg);
	FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_4);
	#endif
}


/**
* @brief 初始化
* @retval none
*/
void pwm_manage_gptm1_init(void)
{
	#if (PHY_PWM_CHANNEL_GPTM1_CH1_EN !=0u)
	FL_GPTIM_OC_Init(GPTIM1, FL_GPTIM_CHANNEL_1, (FL_GPTIM_OC_InitTypeDef*)&g_gptim1_ch1_cfg);
	FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_1);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM1_CH2_EN !=0u)
	FL_GPTIM_OC_Init(GPTIM1, FL_GPTIM_CHANNEL_2, (FL_GPTIM_OC_InitTypeDef*)&g_gptim1_ch2_cfg);
	FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_2);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM1_CH3_EN !=0u)
	FL_GPTIM_OC_Init(GPTIM1, FL_GPTIM_CHANNEL_3, (FL_GPTIM_OC_InitTypeDef*)&g_gptim1_ch3_cfg);
	FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_3);
	#endif
	#if (PHY_PWM_CHANNEL_GPTM1_CH4_EN !=0u)
	FL_GPTIM_OC_Init(GPTIM1, FL_GPTIM_CHANNEL_4, (FL_GPTIM_OC_InitTypeDef*)&g_gptim1_ch4_cfg);
	FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_4);
	#endif
}

/**
* @brief 初始化
* @retval none
*/
void pwm_manage_gptm2_init(void)
{
	#if (PHY_PWM_CHANNEL_GPTM2_CH1_EN !=0u)
	FL_GPTIM_OC_Init(GPTIM2, FL_GPTIM_CHANNEL_1, (FL_GPTIM_OC_InitTypeDef*)&g_gptim2_ch1_cfg);
	FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_1);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM2_CH2_EN !=0u)
	FL_GPTIM_OC_Init(GPTIM2, FL_GPTIM_CHANNEL_2, (FL_GPTIM_OC_InitTypeDef*)&g_gptim2_ch2_cfg);
	FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_2);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM2_CH3_EN !=0u)
	FL_GPTIM_OC_Init(GPTIM2, FL_GPTIM_CHANNEL_3, (FL_GPTIM_OC_InitTypeDef*)&g_gptim2_ch3_cfg);
	FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_3);
	#endif
	#if (PHY_PWM_CHANNEL_GPTM2_CH4_EN !=0u)
	FL_GPTIM_OC_Init(GPTIM2, FL_GPTIM_CHANNEL_4, (FL_GPTIM_OC_InitTypeDef*)&g_gptim2_ch4_cfg);
	FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_4);
	#endif
}


/**
* @brief 初始化
* @retval none
*/
void pwm_manage_lpt32_init(void)
{
	#if (PHY_PWM_CHANNEL_LPT32_CH1_EN !=0u)
	//FL_GPTIM_OC_Init(GPTIM2, FL_GPTIM_CHANNEL_1, (FL_GPTIM_OC_InitTypeDef*)&g_gptim2_ch1_cfg);
	//FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_1);
	#endif

	#if (PHY_PWM_CHANNEL_LPT32_CH2_EN !=0u)
	//FL_GPTIM_OC_Init(GPTIM2, FL_GPTIM_CHANNEL_2, (FL_GPTIM_OC_InitTypeDef*)&g_gptim2_ch2_cfg);
	//FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_2);
	#endif

	#if (PHY_PWM_CHANNEL_LPT32_CH3_EN !=0u)
	//FL_GPTIM_OC_Init(GPTIM2, FL_GPTIM_CHANNEL_3, (FL_GPTIM_OC_InitTypeDef*)&g_gptim2_ch3_cfg);
	//FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_3);
	#endif
	#if (PHY_PWM_CHANNEL_LPT32_CH3_EN !=0u)
	//FL_GPTIM_OC_Init(GPTIM2, FL_GPTIM_CHANNEL_4, (FL_GPTIM_OC_InitTypeDef*)&g_gptim2_ch4_cfg);
	//FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_4);
	#endif
}

/**
* @brief 初始化
* @retval none
*/
void pwm_manage_init(void)
{
	#if 0
	u8 i;
	for(i = 0u; i < PWM_PYH_TOTAL_CHANNEL; i++)
	{
		if(g_pwm_array_channel_en_tab[i]!=0u)
		{
			pwm_manage_channel_init(g_pwm_array_channel_tab[i].base,g_pwm_array_channel_tab[i].channel);
		}
	}

	#if (PHY_PWM_CHANNEL_ATM_CH1_EN !=0u) || (PHY_PWM_CHANNEL_ATM_CH2_EN !=0u) || (PHY_PWM_CHANNEL_ATM_CH3_EN !=0u) || (PHY_PWM_CHANNEL_ATM_CH4_EN !=0u)
	FL_ATIM_BDTR_Init(ATIM, (FL_ATIM_BDTR_InitTypeDef*)&g_atimer0_bdtr_config);
	#endif
	#endif

	//测试
	#if 0
	#ifdef PWM_LOGIC_CHANNEL_LED_DEBUG
	pwm_set_duty(g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_ILL].base,g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_ILL].channel,500u);
	pwm_set_duty(g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_IND].base,g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_IND].channel,500u);
	pwm_set_duty(g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_RED_LF].base,g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_RED_LF].channel,500u);
	pwm_set_duty(g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_RED_RF].base,g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_RED_RF].channel,500u);
	pwm_set_duty(g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_RED_LR].base,g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_RED_LR].channel,500u);
	pwm_set_duty(g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_RED_RR].base,g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_RED_RR].channel,500u);
	pwm_set_duty(g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_BLUE_ALL].base,g_pwm_array_channel_tab[PWM_LOGIC_CHANNEL_LED_BLUE_ALL].channel,500u);
	#endif
	//#else
	pwm_set_duty(PWM_BASE_ID_ATM,1,250u);
	pwm_set_duty(PWM_BASE_ID_ATM,2,250u);
	pwm_set_duty(PWM_BASE_ID_ATM,3,250u);
	pwm_set_duty(PWM_BASE_ID_ATM,4,250u);
	pwm_set_duty(PWM_BASE_ID_GPTM0,1,250u);
	pwm_set_duty(PWM_BASE_ID_GPTM0,2,250u);
	pwm_set_duty(PWM_BASE_ID_GPTM1,2,250u);
	pwm_set_duty(PWM_BASE_ID_GPTM1,3,250u);
	pwm_set_duty(PWM_BASE_ID_GPTM1,4,250u);
	pwm_set_duty(PWM_BASE_ID_GPTM2,1,250u);
	pwm_set_duty(PWM_BASE_ID_LPT32,1,0u);
	pwm_set_duty(PWM_BASE_ID_LPT32,2,250u);

	#endif
	//
}


void pwm_manage_deinit(void)
{
	FL_LPTIM32_OC_InitTypeDef timOCInit;

#if 0
	u8 i;
	for(i = 0u; i < PWM_PYH_TOTAL_CHANNEL; i++)
	{
		if(g_pwm_array_channel_en_tab[i]!=0u)
		{
			pwm_manage_channel_deinit(g_pwm_array_channel_tab[i].base,g_pwm_array_channel_tab[i].channel);
		}
	}
#else

	#if (PHY_PWM_CHANNEL_ATM_CH1_EN !=0u)
	FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_1);
	FL_ATIM_WriteCompareCH1(ATIM,0u);
	#endif

	#if (PHY_PWM_CHANNEL_ATM_CH2_EN !=0u)
	FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_2);
	FL_ATIM_WriteCompareCH2(ATIM,0u);
	#endif

	#if (PHY_PWM_CHANNEL_ATM_CH3_EN !=0u)
	FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_3);
	FL_ATIM_WriteCompareCH3(ATIM,0u);
	#endif

	#if (PHY_PWM_CHANNEL_ATM_CH4_EN !=0u)
	FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_4);
	FL_ATIM_WriteCompareCH4(ATIM,0u);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM0_CH1_EN !=0u)
	FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_1);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM0_CH2_EN !=0u)
	FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_2);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM0_CH3_EN !=0u)
	FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_3);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM0_CH4_EN !=0u)
	FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_4);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM1_CH1_EN !=0u)
	FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_1);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM1_CH2_EN !=0u)
	FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_2);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM1_CH3_EN !=0u)
	FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_3);
	#endif
	#if (PHY_PWM_CHANNEL_GPTM1_CH4_EN !=0u)
	FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_4);
	#endif
	#if (PHY_PWM_CHANNEL_GPTM2_CH1_EN !=0u)
	FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_1);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM2_CH2_EN !=0u)
	FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_2);
	#endif

	#if (PHY_PWM_CHANNEL_GPTM2_CH3_EN !=0u)
	FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_3);
	#endif
	#if (PHY_PWM_CHANNEL_GPTM2_CH4_EN !=0u)
	FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_4);
	#endif

	#if (PHY_PWM_CHANNEL_LPT32_CH1_EN !=0u)
	timOCInit.OCPolarity   = g_lpt32_ch1_cfg.OCPolarity;
	timOCInit.compareValue = 0u;
	FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_1, &timOCInit);
	#endif

	#if (PHY_PWM_CHANNEL_LPT32_CH2_EN !=0u)
	timOCInit.OCPolarity   = g_lpt32_ch2_cfg.OCPolarity;
	timOCInit.compareValue = 0u;
	FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_2, &timOCInit);
	#endif

	#if (PHY_PWM_CHANNEL_LPT32_CH3_EN !=0u)
	timOCInit.OCPolarity   = g_lpt32_ch3_cfg.OCPolarity;
	timOCInit.compareValue = 0u;
	FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_3, &timOCInit);
	#endif

	#if (PHY_PWM_CHANNEL_LPT32_CH4_EN !=0u)
	timOCInit.OCPolarity   = g_lpt32_ch4_cfg.OCPolarity;
	timOCInit.compareValue = 0u;
	FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_4, &timOCInit);
	#endif


#endif

}


void pwm_manage_channel_init(u8 base_id, u8 channel_id)
{
	//atm
	if(base_id == PWM_BASE_ID_ATM)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_ATM_CH1_EN !=0u)
				FL_ATIM_OC_Init(ATIM, FL_ATIM_CHANNEL_1, (FL_ATIM_OC_InitTypeDef*)&g_atmer0_ch1_InitStructer);
				FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_1);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_ATM_CH2_EN !=0u)
				FL_ATIM_OC_Init(ATIM, FL_ATIM_CHANNEL_2, (FL_ATIM_OC_InitTypeDef*)&g_atmer0_ch2_InitStructer);
				FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_2);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_ATM_CH3_EN !=0u)
				FL_ATIM_OC_Init(ATIM, FL_ATIM_CHANNEL_3, (FL_ATIM_OC_InitTypeDef*)&g_atmer0_ch3_InitStructer);
				FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_3);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_ATM_CH4_EN !=0u)
				FL_ATIM_OC_Init(ATIM, FL_ATIM_CHANNEL_4, (FL_ATIM_OC_InitTypeDef*)&g_atmer0_ch4_InitStructer);
				FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_4);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	//gptim0
	else if(base_id == PWM_BASE_ID_GPTM0)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH1_EN !=0u)
				FL_GPTIM_OC_Init(GPTIM0, FL_GPTIM_CHANNEL_1, (FL_GPTIM_OC_InitTypeDef*)&g_gptim_ch1_cfg);
				FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_1);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH2_EN !=0u)
				FL_GPTIM_OC_Init(GPTIM0, FL_GPTIM_CHANNEL_2, (FL_GPTIM_OC_InitTypeDef*)&g_gptim_ch2_cfg);
				FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_2);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH3_EN !=0u)
				FL_GPTIM_OC_Init(GPTIM0, FL_GPTIM_CHANNEL_3, (FL_GPTIM_OC_InitTypeDef*)&g_gptim_ch3_cfg);
				FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_3);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH4_EN !=0u)
				FL_GPTIM_OC_Init(GPTIM0, FL_GPTIM_CHANNEL_4, (FL_GPTIM_OC_InitTypeDef*)&g_gptim_ch4_cfg);
				FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_4);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	//gptim1
	else if(base_id == PWM_BASE_ID_GPTM1)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH1_EN !=0u)
				FL_GPTIM_OC_Init(GPTIM1, FL_GPTIM_CHANNEL_1, (FL_GPTIM_OC_InitTypeDef*)&g_gptim1_ch1_cfg);
				FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_1);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH2_EN !=0u)
				FL_GPTIM_OC_Init(GPTIM1, FL_GPTIM_CHANNEL_2, (FL_GPTIM_OC_InitTypeDef*)&g_gptim1_ch2_cfg);
				FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_2);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH3_EN !=0u)
				FL_GPTIM_OC_Init(GPTIM1, FL_GPTIM_CHANNEL_3, (FL_GPTIM_OC_InitTypeDef*)&g_gptim1_ch3_cfg);
				FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_3);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH4_EN !=0u)
				FL_GPTIM_OC_Init(GPTIM1, FL_GPTIM_CHANNEL_4, (FL_GPTIM_OC_InitTypeDef*)&g_gptim1_ch4_cfg);
				FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_4);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	//gptim2
	else if(base_id == PWM_BASE_ID_GPTM2)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH1_EN !=0u)
				FL_GPTIM_OC_Init(GPTIM2, FL_GPTIM_CHANNEL_1, (FL_GPTIM_OC_InitTypeDef*)&g_gptim2_ch1_cfg);
				FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_1);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH2_EN !=0u)
				FL_GPTIM_OC_Init(GPTIM2, FL_GPTIM_CHANNEL_2, (FL_GPTIM_OC_InitTypeDef*)&g_gptim2_ch2_cfg);
				FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_2);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH3_EN !=0u)
				FL_GPTIM_OC_Init(GPTIM2, FL_GPTIM_CHANNEL_3, (FL_GPTIM_OC_InitTypeDef*)&g_gptim2_ch3_cfg);
				FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_3);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH4_EN !=0u)
				FL_GPTIM_OC_Init(GPTIM2, FL_GPTIM_CHANNEL_4, (FL_GPTIM_OC_InitTypeDef*)&g_gptim2_ch4_cfg);
				FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_4);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	//lpt32
	else if(base_id == PWM_BASE_ID_LPT32)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_LPT32_CH1_EN !=0u)
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_LPT32_CH2_EN !=0u)
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_LPT32_CH3_EN !=0u)
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_LPT32_CH4_EN !=0u)
				#endif
			break;
			default:
				//code
			break;
		}
	}
	else
	{
		//
	}
}


void pwm_manage_channel_deinit(u8 base_id, u8 channel_id)
{
	FL_LPTIM32_OC_InitTypeDef timOCInit;
	//atm
	if(base_id == PWM_BASE_ID_ATM)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_ATM_CH1_EN !=0u)
				FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_1);
				FL_ATIM_WriteCompareCH1(ATIM,0u);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_ATM_CH2_EN !=0u)
				FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_2);
				FL_ATIM_WriteCompareCH2(ATIM,0u);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_ATM_CH3_EN !=0u)
				FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_3);
				FL_ATIM_WriteCompareCH3(ATIM,0u);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_ATM_CH4_EN !=0u)
				FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_4);
				FL_ATIM_WriteCompareCH4(ATIM,0u);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	//gptim0
	else if(base_id == PWM_BASE_ID_GPTM0)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH1_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_1);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH2_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_2);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH3_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_3);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH4_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_4);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	//gptim1
	else if(base_id == PWM_BASE_ID_GPTM1)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH1_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_1);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH2_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_2);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH3_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_3);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH4_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_4);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	//gptim2
	else if(base_id == PWM_BASE_ID_GPTM2)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH1_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_1);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH2_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_2);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH3_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_3);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH4_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_4);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	//lpt32
	else if(base_id == PWM_BASE_ID_LPT32)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_LPT32_CH1_EN !=0u)
				timOCInit.OCPolarity   = g_lpt32_ch1_cfg.OCPolarity;
				timOCInit.compareValue = 0u;
				FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_1, &timOCInit);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_LPT32_CH2_EN !=0u)
				timOCInit.OCPolarity   = g_lpt32_ch2_cfg.OCPolarity;
				timOCInit.compareValue = 0u;
				FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_2, &timOCInit);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_LPT32_CH3_EN !=0u)
				timOCInit.OCPolarity   = g_lpt32_ch3_cfg.OCPolarity;
				timOCInit.compareValue = 0u;
				FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_3, &timOCInit);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_LPT32_CH4_EN !=0u)
				timOCInit.OCPolarity   = g_lpt32_ch4_cfg.OCPolarity;
				timOCInit.compareValue = 0u;
				FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_4, &timOCInit);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	else
	{
		//
	}
}

void pwm_set_duty(u8 base_id, u8 channel_id,u16 duty)
{
	FL_LPTIM32_OC_InitTypeDef timOCInit;
	u16 l_duty;
	//atm
	if(base_id == PWM_BASE_ID_ATM)
	{
		l_duty = SET_ATM1_PWM_DUTY_PERCENT(duty);
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_ATM_CH1_EN !=0u)
				FL_ATIM_OC_EnableChannel(ATIM,FL_ATIM_CHANNEL_1);
				FL_ATIM_WriteCompareCH1(ATIM,l_duty);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_ATM_CH2_EN !=0u)
				FL_ATIM_OC_EnableChannel(ATIM,FL_ATIM_CHANNEL_2);
				FL_ATIM_WriteCompareCH2(ATIM,l_duty);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_ATM_CH3_EN !=0u)
				FL_ATIM_OC_EnableChannel(ATIM,FL_ATIM_CHANNEL_3);
				FL_ATIM_WriteCompareCH3(ATIM,l_duty);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_ATM_CH4_EN !=0u)
				FL_ATIM_OC_EnableChannel(ATIM,FL_ATIM_CHANNEL_4);
				FL_ATIM_WriteCompareCH4(ATIM,l_duty);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	//gptim
	else if(base_id == PWM_BASE_ID_GPTM0)
	{
		l_duty = SET_GPTIM0_PWM_DUTY_PERCENT(duty);
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH1_EN !=0u)
				FL_GPTIM_WriteCompareCH1(GPTIM0,l_duty);
				FL_GPTIM_OC_EnableChannel(GPTIM0, FL_GPTIM_CHANNEL_1);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH2_EN !=0u)
				FL_GPTIM_WriteCompareCH2(GPTIM0,l_duty);
				FL_GPTIM_OC_EnableChannel(GPTIM0, FL_GPTIM_CHANNEL_2);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH3_EN !=0u)
				FL_GPTIM_WriteCompareCH3(GPTIM0,l_duty);
				FL_GPTIM_OC_EnableChannel(GPTIM0, FL_GPTIM_CHANNEL_3);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH4_EN !=0u)
				FL_GPTIM_WriteCompareCH4(GPTIM0,l_duty);
				FL_GPTIM_OC_EnableChannel(GPTIM0, FL_GPTIM_CHANNEL_4);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	else if(base_id == PWM_BASE_ID_GPTM1)
	{
		l_duty = SET_GPTIM1_PWM_DUTY_PERCENT(duty);
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH1_EN !=0u)
				FL_GPTIM_WriteCompareCH1(GPTIM1,l_duty);
				FL_GPTIM_OC_EnableChannel(GPTIM1, FL_GPTIM_CHANNEL_1);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH2_EN !=0u)
				FL_GPTIM_WriteCompareCH2(GPTIM1,l_duty);
				FL_GPTIM_OC_EnableChannel(GPTIM1, FL_GPTIM_CHANNEL_2);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH3_EN !=0u)
				FL_GPTIM_WriteCompareCH3(GPTIM1,l_duty);
				FL_GPTIM_OC_EnableChannel(GPTIM1, FL_GPTIM_CHANNEL_3);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH4_EN !=0u)
				FL_GPTIM_WriteCompareCH4(GPTIM1,l_duty);
				FL_GPTIM_OC_EnableChannel(GPTIM1, FL_GPTIM_CHANNEL_4);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	else if(base_id == PWM_BASE_ID_GPTM2)
	{
		l_duty = SET_GPTIM2_PWM_DUTY_PERCENT(duty);
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH1_EN !=0u)
				FL_GPTIM_WriteCompareCH1(GPTIM2,l_duty);
				FL_GPTIM_OC_EnableChannel(GPTIM2, FL_GPTIM_CHANNEL_1);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH2_EN !=0u)
				FL_GPTIM_WriteCompareCH2(GPTIM2,l_duty);
				FL_GPTIM_OC_EnableChannel(GPTIM2, FL_GPTIM_CHANNEL_2);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH3_EN !=0u)
				FL_GPTIM_WriteCompareCH3(GPTIM2,l_duty);
				FL_GPTIM_OC_EnableChannel(GPTIM2, FL_GPTIM_CHANNEL_3);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH4_EN !=0u)
				FL_GPTIM_WriteCompareCH4(GPTIM2,l_duty);
				FL_GPTIM_OC_EnableChannel(GPTIM2, FL_GPTIM_CHANNEL_4);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	//lpt32
	else if(base_id == PWM_BASE_ID_LPT32)
	{
		l_duty = SET_LPT32_PWM_DUTY_PERCENT(duty);
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_LPT32_CH1_EN !=0u)
				if(l_duty==0u)
				{
					lpt32_ch1_set_gpio();
					g_lpt32_ch_flag[0]=0u;
				}
				else
				{
					if(g_lpt32_ch_flag[0]!=1u)
					{
						lpt32_ch1_set_pwm();
						g_lpt32_ch_flag[0]=1u;
					}
					timOCInit.OCPolarity   = g_lpt32_ch1_cfg.OCPolarity;
					timOCInit.compareValue = l_duty;
					FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_1, &timOCInit);
				}
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_LPT32_CH2_EN !=0u)
				if(l_duty==0u)
				{
					lpt32_ch1_set_gpio();
					g_lpt32_ch_flag[1]=0u;
				}
				else
				{
					if(g_lpt32_ch_flag[1]!=1u)
					{
						lpt32_ch1_set_pwm();
						g_lpt32_ch_flag[1]=1u;
					}
					timOCInit.OCPolarity   = g_lpt32_ch2_cfg.OCPolarity;
					timOCInit.compareValue = l_duty;
					FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_2, &timOCInit);
				}
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_LPT32_CH3_EN !=0u)
				timOCInit.OCPolarity   = g_lpt32_ch3_cfg.OCPolarity;
				timOCInit.compareValue = l_duty;
				FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_3, &timOCInit);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_LPT32_CH4_EN !=0u)
				timOCInit.OCPolarity   = g_lpt32_ch4_cfg.OCPolarity;
				timOCInit.compareValue = l_duty;
				FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_4, &timOCInit);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	else
	{
		//
	}
	//FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_2);
}

void pwm_disable(u8 base_id, u8 channel_id)
{
	FL_LPTIM32_OC_InitTypeDef timOCInit;
	u8 l_duty =0u;
	//atm
	if(base_id == PWM_BASE_ID_ATM)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_ATM_CH1_EN !=0u)
				FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_1);
				FL_ATIM_WriteCompareCH1(ATIM,l_duty);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_ATM_CH2_EN !=0u)
				FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_2);
				FL_ATIM_WriteCompareCH2(ATIM,l_duty);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_ATM_CH3_EN !=0u)
				FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_3);
				FL_ATIM_WriteCompareCH3(ATIM,l_duty);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_ATM_CH4_EN !=0u)
				FL_ATIM_OC_DisableChannel(ATIM,FL_ATIM_CHANNEL_4);
				FL_ATIM_WriteCompareCH4(ATIM,l_duty);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	//gptim
	else if(base_id == PWM_BASE_ID_GPTM0)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH1_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_1);
				FL_GPTIM_WriteCompareCH1(GPTIM0,l_duty);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH2_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_2);
				FL_GPTIM_WriteCompareCH2(GPTIM0,l_duty);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH3_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_3);
				FL_GPTIM_WriteCompareCH3(GPTIM0,l_duty);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_GPTM0_CH4_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM0, FL_GPTIM_CHANNEL_4);
				FL_GPTIM_WriteCompareCH4(GPTIM0,l_duty);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	else if(base_id == PWM_BASE_ID_GPTM1)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH1_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_1);
				FL_GPTIM_WriteCompareCH1(GPTIM1,l_duty);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH2_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_2);
				FL_GPTIM_WriteCompareCH2(GPTIM1,l_duty);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH3_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_3);
				FL_GPTIM_WriteCompareCH3(GPTIM1,l_duty);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_GPTM1_CH4_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM1, FL_GPTIM_CHANNEL_4);
				FL_GPTIM_WriteCompareCH4(GPTIM1,l_duty);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	else if(base_id == PWM_BASE_ID_GPTM2)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH1_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_1);
				FL_GPTIM_WriteCompareCH1(GPTIM2,l_duty);
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH2_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_2);
				FL_GPTIM_WriteCompareCH2(GPTIM2,l_duty);
				#endif
			break;
			case 3u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH3_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_3);
				FL_GPTIM_WriteCompareCH3(GPTIM2,l_duty);
				#endif
			break;
			case 4u:
				#if (PHY_PWM_CHANNEL_GPTM2_CH4_EN !=0u)
				FL_GPTIM_OC_DisableChannel(GPTIM2, FL_GPTIM_CHANNEL_4);
				FL_GPTIM_WriteCompareCH4(GPTIM2,l_duty);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	//lpt32
	else if(base_id == PWM_BASE_ID_LPT32)
	{
		switch(channel_id)
		{
			case 1u:
				#if (PHY_PWM_CHANNEL_LPT32_CH1_EN !=0u)
				#if 0
				timOCInit.OCPolarity   = g_lpt32_ch1_cfg.OCPolarity;
				timOCInit.compareValue = 0u;
				FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_1, &timOCInit);
				#else
				g_lpt32_ch_flag[0]=0u;
				lpt32_ch1_set_gpio();
				#endif
				#endif
			break;
			case 2u:
				#if (PHY_PWM_CHANNEL_LPT32_CH2_EN !=0u)
				#if 0
				timOCInit.OCPolarity   = g_lpt32_ch2_cfg.OCPolarity;
				timOCInit.compareValue = 0u;
				FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_2, &timOCInit);
				#else
				g_lpt32_ch_flag[1]=0u;
				lpt32_ch2_set_gpio();
				#endif
				#endif
			break;
			case 3u:
				g_lpt32_ch_flag[2]=0u;
				#if (PHY_PWM_CHANNEL_LPT32_CH3_EN !=0u)
				timOCInit.OCPolarity   = g_lpt32_ch3_cfg.OCPolarity;
				timOCInit.compareValue = 0u;
				FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_3, &timOCInit);
				#endif
			break;
			case 4u:
				g_lpt32_ch_flag[3]=0u;
				#if (PHY_PWM_CHANNEL_LPT32_CH4_EN !=0u)
				timOCInit.OCPolarity   = g_lpt32_ch4_cfg.OCPolarity;
				timOCInit.compareValue = 0u;
				FL_LPTIM32_OC_Init(LPTIM32, FL_LPTIM32_CHANNEL_4, &timOCInit);
				#endif
			break;
			default:
				//code
			break;
		}
	}
	else
	{
		//
	}
}

void pwm_enable(u8 base_id, u8 channel_id)
{

}