diff --git a/CAN_Bootloader/lib/usb2canfd.aardio b/CAN_Bootloader/lib/usb2canfd.aardio index 039f656..075a8c0 100644 --- a/CAN_Bootloader/lib/usb2canfd.aardio +++ b/CAN_Bootloader/lib/usb2canfd.aardio @@ -294,7 +294,7 @@ namespace usb2canfd{ canconfig.CAN_SJW = 2; ret = DllHandle.CAN_Init(AvailableHW[index].hLINHW,channel,canconfig); //console.log("init ret = " + ret); - this.SetFilter(index); + //this.SetFilter(index); } canfd_connected = canfd; diff --git a/CAN_Bootloader/main.aardio b/CAN_Bootloader/main.aardio index d908dca..fff2e74 100644 --- a/CAN_Bootloader/main.aardio +++ b/CAN_Bootloader/main.aardio @@ -6,29 +6,27 @@ btnConnect={cls="button";text="连接";left=204;top=64;right=289;bottom=90;z=4}; btnFlash={cls="button";text="开始刷写";left=36;top=329;right=135;bottom=357;z=9}; btnFresh={cls="button";text="刷新";left=204;top=28;right=288;bottom=54;z=2}; btnOpen={cls="button";text="打开文件";left=36;top=296;right=135;bottom=324;z=8}; -btnOpenFlashdrv={cls="button";text="打开FlashDriver";left=148;top=296;right=247;bottom=324;z=24}; +btnOpenFlashdrv={cls="button";text="进入BOOT";left=148;top=296;right=247;bottom=324;z=22}; btnReadF180={cls="button";text="读取boot版本";left=36;top=429;right=135;bottom=457;z=19}; btnReadF186={cls="button";text="读取当前会话";left=36;top=363;right=135;bottom=391;z=13}; btnReadF187={cls="button";text="读取型号";left=148;top=429;right=247;bottom=457;z=20}; -btnReadF191={cls="button";text="读取编译日期";left=148;top=362;right=247;bottom=390;z=25}; +btnReadF191={cls="button";text="读取编译日期";left=148;top=362;right=247;bottom=390;z=23}; btnReadHw={cls="button";text="读取硬件版本号";left=148;top=395;right=247;bottom=423;z=12}; btnReadSw={cls="button";text="读取软件版本号";left=36;top=396;right=135;bottom=424;z=10}; btnTest={cls="button";text="停止";left=148;top=330;right=247;bottom=358;z=11}; cbbChannel={cls="combobox";left=58;top=64;right=191;bottom=90;edge=1;items={};mode="dropdown";z=3}; cbbDev={cls="combobox";left=58;top=27;right=191;bottom=53;edge=1;items={};mode="dropdown";z=1}; -checkbox={cls="checkbox";text="CANFD设备";left=151;top=101;right=248;bottom=120;checked=1;z=21}; +checkbox={cls="checkbox";text="CANFD设备";left=151;top=101;right=248;bottom=120;z=21}; edFile={cls="richedit";left=8;top=131;right=288;bottom=187;border=1;disabled=1;edge=1;multiline=1;wrap=1;z=14}; -edFile2={cls="richedit";left=8;top=202;right=288;bottom=258;border=1;disabled=1;edge=1;multiline=1;wrap=1;z=22}; edit={cls="edit";left=294;top=19;right=596;bottom=401;autovscroll=false;edge=1;multiline=1;vscroll=1;z=5}; progress={cls="progress";left=296;top=436;right=596;bottom=464;edge=1;max=100;min=0;z=15}; -radiobutton={cls="radiobutton";text="左侧";left=45;top=268;right=121;bottom=288;checked=1;group=1;z=26}; -radiobutton2={cls="radiobutton";text="右侧";left=163;top=268;right=242;bottom=287;z=27}; +radiobutton={cls="radiobutton";text="左侧";left=45;top=268;right=121;bottom=288;checked=1;group=1;z=24}; +radiobutton2={cls="radiobutton";text="右侧";left=163;top=268;right=242;bottom=287;z=25}; static={cls="static";text="设备";left=1;top=28;right=61;bottom=52;align="center";center=1;transparent=1;z=6}; static2={cls="static";text="通道";left=1;top=66;right=61;bottom=90;align="center";center=1;transparent=1;z=7}; static3={cls="static";text="刷写进度";left=296;top=409;right=349;bottom=429;transparent=1;z=16}; static4={cls="static";text="烧录APP";left=13;top=108;right=85;bottom=132;center=1;transparent=1;z=17}; -static5={cls="static";text="V0.2_20241219";left=451;top=1;right=595;bottom=17;align="right";center=1;transparent=1;z=18}; -static6={cls="static";text="FlashDriver";left=13;top=184;right=101;bottom=207;transparent=1;z=23} +static5={cls="static";text="V0.2_20241219";left=451;top=1;right=595;bottom=17;align="right";center=1;transparent=1;z=18} ) /*}}*/ @@ -156,8 +154,8 @@ var CanThread = function(){ DiagReadDID = function(did){ ::PostThreadMessage(thrdId,110,did,0)//自定义消息 } -var Diag10Req = function(num){ - ::PostThreadMessage(thrdId,111,num,0)//自定义消息 +var Diag10Req = function(phyaddr,num){ + ::PostThreadMessage(thrdId,111,phyaddr,num)//自定义消息 } var DiagBootReq = function(){ ::PostThreadMessage(thrdId,102,0,0)//自定义消息 @@ -188,10 +186,7 @@ mainForm.btnFlash.oncommand = function(id,event){ Display("请打开烧写文件"); return; } - if(io.exist(mainForm.edFile2.text) == null){ - Display("请打开flashdriver文件"); - return; - } + if(flag_connected == 0){ Display("请连接设备"); return; @@ -236,7 +231,8 @@ mainForm.btnReadF187.oncommand = function(id,event){ } mainForm.btnOpenFlashdrv.oncommand = function(id,event){ - ::PostThreadMessage(thrdId,104,1,0)//自定义消息-打开flashdriver + //::PostThreadMessage(thrdId,104,1,0)//自定义消息-打开flashdriver + Diag10Req(1,0x02);//进入扩展会话 } diff --git a/CAN_Bootloader/user/CanThread.aardio b/CAN_Bootloader/user/CanThread.aardio index 205f083..0766807 100644 --- a/CAN_Bootloader/user/CanThread.aardio +++ b/CAN_Bootloader/user/CanThread.aardio @@ -41,23 +41,13 @@ FuncLoopMsg = function(msg){ FuncStopBoot(); } case 104 {//打开s19文件 - if(msg.wParam == 1){ - FuncDisplay("打开FlashDriver"); - var ret = FuncOpenS19File(msg.wParam); - if(ret != null){ - thread.command.$ShowFlashDrvPath(ret); - var crc32 = FuncGetFlashCRC(1); - FuncDisplay("CRC = " ++ string.format("%X",crc32)); - } - } - else { - FuncDisplay("打开烧写文件"); - var ret = FuncOpenS19File(msg.wParam); - if(ret != null){ - thread.command.$ShowPath(ret); - var crc32 = FuncGetFlashCRC(2); - FuncDisplay("CRC = " ++ string.format("%X",crc32)); - } + + FuncDisplay("打开烧写文件"); + var ret = FuncOpenS19File(1); + if(ret != null){ + thread.command.$ShowPath(ret); + var crc32 = FuncGetFlashCRC(1); + FuncDisplay("CRC = " ++ string.format("%X",crc32)); } diff --git a/CAN_Bootloader/user/Diag34code.aardio b/CAN_Bootloader/user/Diag34code.aardio index 34e36b3..26d1fc9 100644 --- a/CAN_Bootloader/user/Diag34code.aardio +++ b/CAN_Bootloader/user/Diag34code.aardio @@ -2,6 +2,7 @@ //发送 FuncReq34 = function(addr,len){ + FuncDisplay("请求下载"++ tostring(addr,16) ++ "," ++ tostring(len,16)) var data = {0x44,addr>>24,addr>>16,addr>>8,addr,len>>24,len>>16,len>>8,len}; var txdata = {0x10,2+#data,0x34,0x00,data[1],data[2],data[3],data[4]}; CANHw.SendMsg(DiagReqID,txdata); diff --git a/CAN_Bootloader/user/DiagBootcode.aardio b/CAN_Bootloader/user/DiagBootcode.aardio index 42a4cdd..1f8aa2a 100644 --- a/CAN_Bootloader/user/DiagBootcode.aardio +++ b/CAN_Bootloader/user/DiagBootcode.aardio @@ -120,6 +120,7 @@ FuncSendBlockApp = function(){ } else { if(FuncWait(0x34) == 0){ + sleep(200); FuncSendBlockApp_sendflag = 0; sendblockstate += 1; } @@ -211,7 +212,7 @@ FuncBootSeq = function(){ else { var ret = FuncWait(0x22); if(g22data["F187"]!= null){ - if(g22data["F187"] == "RP-77B"){ + if(g22data["F187"] == "WK-K86"){ nextstate(0); } else { @@ -320,6 +321,7 @@ FuncBootSeq = function(){ var ret = FuncWait(0x27); nextstate(ret); } + } case 9 { if(sendstate == 0){ @@ -334,6 +336,7 @@ FuncBootSeq = function(){ } } case 10 { + /* if(sendstate == 0){ FuncReq31EraseFlash(0x20005BF0,0x800); FuncClearState(); @@ -343,9 +346,12 @@ FuncBootSeq = function(){ var ret = FuncWait(0x31); nextstate(ret); } + */ + nextstate(0); } case 11 { + /* if(sendstate == 0){//写入installation_date FuncReq3103(0xFD01); FuncClearState(); @@ -354,8 +360,11 @@ FuncBootSeq = function(){ var ret = FuncWait(0x31); nextstate(ret); } + */ + nextstate(0); } case 12 { + /* if(sendstate == 0){//发送数据 FuncSendBlockInit(1); FuncDisplay("开始发送FlashDrv数据"); @@ -365,8 +374,11 @@ FuncBootSeq = function(){ var ret = FuncSendBlockApp(); nextstate(ret); } + */ + nextstate(0); } case 13 { + /* if(sendstate == 0){//CheckLogicBlock //var crc = FuncGetFlashCRC(0); //FuncReq31CheckLogicBlock(crc); @@ -377,18 +389,11 @@ FuncBootSeq = function(){ var ret = FuncWait(0x31); nextstate(ret); } + */ + nextstate(0); } + case 14 { - if(sendstate == 0){// - FuncReq3103(0xFD02); - FuncClearState(); - } - else { - var ret = FuncWait(0x31); - nextstate(ret); - } - } - case 15 { if(sendstate == 0){//CheckLogicBlock FuncReq31EraseFlash(0x00010000,0x28000); FuncClearState(); @@ -398,10 +403,32 @@ FuncBootSeq = function(){ nextstate(ret); } } - + case 15 { + /* + if(sendstate == 0){// + FuncReq3103(0xFD02); + FuncClearState(); + } + else { + var ret = FuncWait(0x31); + nextstate(ret); + } + */ + if(sendstate == 0){//等待复位完成 + delaycount = 0; + FuncClearState(); + } + else { + delaycount += 1; + if(delaycount > 20){ + nextstate(0);//延时0.1S + } + + } + } case 16 { if(sendstate == 0){//发送数据 - FuncSendBlockInit(2); + FuncSendBlockInit(1); FuncDisplay("开始发送App数据"); FuncClearState(); } diff --git a/cva_asw_m0118/.vscode/settings.json b/cva_asw_m0118/.vscode/settings.json index dfbe4f4..f60238b 100644 --- a/cva_asw_m0118/.vscode/settings.json +++ b/cva_asw_m0118/.vscode/settings.json @@ -20,6 +20,8 @@ "files.associations": { "canuser.h": "c", "apptask.h": "c", - "mcu.h": "c" + "mcu.h": "c", + "key.h": "c", + "hwctrl.h": "c" } } \ No newline at end of file diff --git a/cva_asw_m0118/cva_asw_m0118.ewp b/cva_asw_m0118/cva_asw_m0118.ewp index 8fe78e3..211e4d6 100644 --- a/cva_asw_m0118/cva_asw_m0118.ewp +++ b/cva_asw_m0118/cva_asw_m0118.ewp @@ -357,7 +357,6 @@ $PROJ_DIR$\SDK\middleware\uds\user $PROJ_DIR$\SDK\lib\shared\common\stimer $PROJ_DIR$\src\private_driver\drivers\cpu\startup - $PROJ_DIR$\src\TLE9461 $PROJ_DIR$\src $PROJ_DIR$\src\RTT @@ -691,7 +690,7 @@ - 192 + 56 inputOutputBased @@ -1770,30 +1769,6 @@ $PROJ_DIR$\src\RTT\SEGGER_RTT_Syscalls_GCC.c - - TLE9461 - - $PROJ_DIR$\src\TLE9461\SBC_TLE94x1.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1.c - - - $PROJ_DIR$\src\TLE9461\TLE94x1.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1_DEFINES.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1_ISR.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1_SPI.c - - - $PROJ_DIR$\src\TLE9461\TLE94x1_SPI.h - - user @@ -1808,6 +1783,9 @@ $PROJ_DIR$\src\hwctrl.c + + $PROJ_DIR$\src\key.c + diff --git a/cva_asw_m0118/cva_asw_m0118.ewt b/cva_asw_m0118/cva_asw_m0118.ewt index 88fb20b..487839c 100644 --- a/cva_asw_m0118/cva_asw_m0118.ewt +++ b/cva_asw_m0118/cva_asw_m0118.ewt @@ -2100,30 +2100,6 @@ $PROJ_DIR$\src\RTT\SEGGER_RTT_Syscalls_GCC.c - - TLE9461 - - $PROJ_DIR$\src\TLE9461\SBC_TLE94x1.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1.c - - - $PROJ_DIR$\src\TLE9461\TLE94x1.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1_DEFINES.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1_ISR.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1_SPI.c - - - $PROJ_DIR$\src\TLE9461\TLE94x1_SPI.h - - user @@ -2138,6 +2114,9 @@ $PROJ_DIR$\src\hwctrl.c + + $PROJ_DIR$\src\key.c + diff --git a/cva_asw_m0118/settings/cva_asw_m0118.Debug.cspy.bat b/cva_asw_m0118/settings/cva_asw_m0118.Debug.cspy.bat index b33c581..f46c571 100644 --- a/cva_asw_m0118/settings/cva_asw_m0118.Debug.cspy.bat +++ b/cva_asw_m0118/settings/cva_asw_m0118.Debug.cspy.bat @@ -25,7 +25,7 @@ if not "%~1" == "" goto debugFile @echo on -"E:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "F:\FCB_project\RP-77\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.general.xcl" --backend -f "F:\FCB_project\RP-77\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.driver.xcl" +"D:\software\IAR\common\bin\cspybat" -f "E:\work\wk\K86\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.general.xcl" --backend -f "E:\work\wk\K86\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.driver.xcl" @echo off goto end @@ -34,7 +34,7 @@ goto end @echo on -"E:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "F:\FCB_project\RP-77\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.general.xcl" "--debug_file=%~1" --backend -f "F:\FCB_project\RP-77\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.driver.xcl" +"D:\software\IAR\common\bin\cspybat" -f "E:\work\wk\K86\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.general.xcl" "--debug_file=%~1" --backend -f "E:\work\wk\K86\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.driver.xcl" @echo off :end \ No newline at end of file diff --git a/cva_asw_m0118/settings/cva_asw_m0118.Debug.cspy.ps1 b/cva_asw_m0118/settings/cva_asw_m0118.Debug.cspy.ps1 index e50a82c..7a37323 100644 --- a/cva_asw_m0118/settings/cva_asw_m0118.Debug.cspy.ps1 +++ b/cva_asw_m0118/settings/cva_asw_m0118.Debug.cspy.ps1 @@ -23,9 +23,9 @@ if ($debugfile -eq "") { -& "E:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "F:\FCB_project\RP-77\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.general.xcl" --backend -f "F:\FCB_project\RP-77\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.driver.xcl" +& "D:\software\IAR\common\bin\cspybat" -f "E:\work\wk\K86\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.general.xcl" --backend -f "E:\work\wk\K86\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.driver.xcl" } else { -& "E:\Program Files\IAR Systems\Embedded Workbench 9.2\common\bin\cspybat" -f "F:\FCB_project\RP-77\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.general.xcl" --debug_file=$debugfile --backend -f "F:\FCB_project\RP-77\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.driver.xcl" +& "D:\software\IAR\common\bin\cspybat" -f "E:\work\wk\K86\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.general.xcl" --debug_file=$debugfile --backend -f "E:\work\wk\K86\CVM0118BOOT\cva_asw_m0118\settings\cva_asw_m0118.Debug.driver.xcl" } diff --git a/cva_asw_m0118/settings/cva_asw_m0118.Debug.driver.xcl b/cva_asw_m0118/settings/cva_asw_m0118.Debug.driver.xcl index e3d9d6b..d87fe38 100644 --- a/cva_asw_m0118/settings/cva_asw_m0118.Debug.driver.xcl +++ b/cva_asw_m0118/settings/cva_asw_m0118.Debug.driver.xcl @@ -6,7 +6,7 @@ "-p" -"E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0118.ddf" +"D:\software\IAR\arm\config\debugger\CVAChip\CVM0118.ddf" "--semihosting" diff --git a/cva_asw_m0118/settings/cva_asw_m0118.Debug.general.xcl b/cva_asw_m0118/settings/cva_asw_m0118.Debug.general.xcl index a484125..102836a 100644 --- a/cva_asw_m0118/settings/cva_asw_m0118.Debug.general.xcl +++ b/cva_asw_m0118/settings/cva_asw_m0118.Debug.general.xcl @@ -1,10 +1,10 @@ -"E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armPROC.dll" +"D:\software\IAR\arm\bin\armPROC.dll" -"E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armJLINK.dll" +"D:\software\IAR\arm\bin\armJLINK.dll" -"F:\FCB_project\RP-77\CVM0118BOOT\cva_asw_m0118\Debug_FLASH\Exe\cva_asw_m0118.out" +"E:\work\wk\K86\CVM0118BOOT\cva_asw_m0118\Debug_FLASH\Exe\cva_asw_m0118.out" ---plugin="E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\armbat.dll" +--plugin="D:\software\IAR\arm\bin\armbat.dll" diff --git a/cva_asw_m0118/settings/cva_asw_m0118.dnx b/cva_asw_m0118/settings/cva_asw_m0118.dnx index b622afd..38989d9 100644 --- a/cva_asw_m0118/settings/cva_asw_m0118.dnx +++ b/cva_asw_m0118/settings/cva_asw_m0118.dnx @@ -13,7 +13,7 @@ 0 - E:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\config\debugger\CVAChip\CVM0118.ddf + D:\software\IAR\arm\config\debugger\CVAChip\CVM0118.ddf 1 @@ -47,13 +47,13 @@ 0 - _ 0 - _ 0 12 0 0x10000 0x0 0x0 + _ 0 + _ 0 0 diff --git a/cva_asw_m0118/settings/cva_asw_m0118.wsdt b/cva_asw_m0118/settings/cva_asw_m0118.wsdt index ffa611e..33708c8 100644 --- a/cva_asw_m0118/settings/cva_asw_m0118.wsdt +++ b/cva_asw_m0118/settings/cva_asw_m0118.wsdt @@ -74,7 +74,7 @@ _I0 - 1486 + 1674 20 2 @@ -91,7 +91,7 @@ 14 - 32 + 27 1 @@ -101,16 +101,16 @@ 1 1 1 - 2D000000090010860000050000000C8100002600000056860000010000000E810000020000000B810000030000000581000001000000118600000500000046810000010000000A84000001000000 + 44000000090010860000050000000C8100003C00000056860000010000000E810000020000000B810000030000001186000005000000058100000200000046810000010000000A84000001000000 - 3B002DDE00001FDE000020DE000021DE000026DE000028DE000023DE000022DE000024DE000027DE000025DE0000209200002892000029920000379200003892000034920000339200001E9200001D9200002CDE00000C84000033840000788400001184000008800000098000000A8000000B8000000C800000158000000A810000FFFFFFFF01E80000778400000784000086840000808C000044D500000D8400000F8400000884000054840000328100001C81000009840000538400003C8400003D840000408400004C8400003E8400004B8400004D8400003F8400003A8400003B8400005A8400005B840000 - 1E0004840000B403000004810000820300003184000054000000208100002A0000000F8100002200000000900000BF0300000C8100001F00000006840000B60300000981000084030000038400004C00000025920000590000000E840000B803000030840000BA03000044920000730300001F810000290000000E810000210000001F920000700300000B810000850300002D92000072030000D184000008000000058400004E000000028400004B0000000581000083030000108400005200000032840000550000000A840000500000000D8100008703000035E10000AC03000002E10000A20300002C92000071030000 + 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0A0000000A0000006E0000006E000000 - 000000001A030000000600002B030000 + 00000000D3030000AB060000E4030000 4096 0 0 @@ -136,8 +136,8 @@ 4294967295 - 00000000FE0100000006000031030000 - 00000000E7010000000600001A030000 + 00000000B7020000AB060000EA030000 + 00000000A0020000AB060000D3030000 4096 0 0 @@ -150,7 +150,7 @@ 34051 000000001700000022010000C8000000 - 04000000FF010000FC05000000030000 + 04000000B8020000A7060000B9030000 32768 0 0 @@ -168,12 +168,12 @@ _I0 - 338 + 382 40 - 1107 + 1251 20 - 2 + 4 $WS_DIR$\BuildLog.log 0 0 @@ -181,7 +181,7 @@ 34055 000000001700000022010000C8000000 - 04000000FF010000FC05000000030000 + 04000000B8020000A7060000B9030000 4096 0 0 @@ -194,7 +194,7 @@ 34056 000000001700000022010000C8000000 - 04000000FF010000FC05000000030000 + 04000000B8020000A7060000B9030000 4096 0 0 @@ -205,9 +205,9 @@ 0 - 533 - 76 - 914 + 591 + 84 + 1014 2 0 @@ -216,7 +216,7 @@ 34057 000000001700000022010000C8000000 - 04000000FF010000FC05000000030000 + 04000000B8020000A7060000B9030000 4096 0 0 @@ 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diff --git a/cva_asw_m0118/src/TLE9461/SBC_TLE94x1.h b/cva_asw_m0118/src/TLE9461/SBC_TLE94x1.h deleted file mode 100644 index 146c2cc..0000000 --- a/cva_asw_m0118/src/TLE9461/SBC_TLE94x1.h +++ /dev/null @@ -1,101 +0,0 @@ -/** - * @cond - *********************************************************************************************************************** - * - * Copyright (c) 2018, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the - * following disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **********************************************************************************************************************/ -#ifndef SBC_TLE94X1_H -#define SBC_TLE94X1_H - -/* XML Version 0.0.6 */ -#define SBC_XML_VERSION (00006) - -#define CTRL_BUS_CTRL_0 (0x3) /*decimal 3*/ - -#define CTRL_BUS_CTRL_3 (0x0) /*decimal 0*/ - -#define CTRL_GPIO_CTRL (0x4) /*decimal 4*/ - -#define CTRL_HW_CTRL_0 (0x40) /*decimal 64*/ - -#define CTRL_HW_CTRL_1 (0x0) /*decimal 0*/ - -#define CTRL_HW_CTRL_2 (0x40) /*decimal 64*/ - -#define CTRL_HW_CTRL_3 (0x1) /*decimal 1*/ - -#define CTRL_M_S_CTRL (0x13) /*decimal 19*/ - -#define CTRL_PWM_CTRL (0x0) /*decimal 0*/ - -#define CTRL_PWM_FREQ_CTRL (0x0) /*decimal 0*/ - -#define CTRL_SWK_BTL0_CTRL (0x50) /*decimal 80*/ - -#define CTRL_SWK_CAN_FD_CTRL (0x0) /*decimal 0*/ - -#define CTRL_SWK_CDR_CTRL2 (0x1) /*decimal 1*/ - -#define CTRL_SWK_CDR_LIMIT_HIGH_CTRL (0x54) /*decimal 84*/ - -#define CTRL_SWK_CDR_LIMIT_LOW_CTRL (0x4C) /*decimal 76*/ - -#define CTRL_SWK_DATA_H_CTRL 0x00000000 - -#define CTRL_SWK_DATA_L_CTRL 0x00000000 - -#define CTRL_SWK_DLC_CTRL (0x0) /*decimal 0*/ - -#define CTRL_SWK_ID0_CTRL (0x0) /*decimal 0*/ - -#define CTRL_SWK_IDx_CTRL 0x00000000 - -#define CTRL_SWK_MASK_IDx_CTRL 0x00000000 - -#define CTRL_TIMER_CTRL (0x0) /*decimal 0*/ - -#define CTRL_WD_CTRL (0x15) /*decimal 21*/ - -#define CTRL_WK_CTRL_0 (0x0) /*decimal 0*/ - -#define CTRL_WK_CTRL_1 (0x0) /*decimal 0*/ - -#define CTRL_WK_PUPD_CTRL (0x0) /*decimal 0*/ - -#define LED_Math_extendedID (0x1) /*decimal 1*/ - -#define LED_Math_extendedIDMsk (0x1) /*decimal 1*/ - -#define MATH_Baudrate (0x2) /*decimal 2*/ - -#define MATH_CDR_FrequencyMHz (0x28) /*decimal 40*/ - -#define MATH_DoubleCDRFreq (0x0) /*decimal 0*/ - -#define MATH_EN_PN (0x1) /*decimal 1*/ - -#define MATH_PWM_DC (0.0) - -#endif /* SBC_TLE94X1_H */ diff --git a/cva_asw_m0118/src/TLE9461/TLE9461.icwp b/cva_asw_m0118/src/TLE9461/TLE9461.icwp deleted file mode 100644 index 5a043c4..0000000 --- a/cva_asw_m0118/src/TLE9461/TLE9461.icwp +++ /dev/null @@ -1,233 +0,0 @@ - - - 9e8e9087eecb39921ec31dfccce96b2a2efec664bafe2827aea4ddb51cb86761 - TLE94x1_Lib.xml - V0.0.6 - - - CTRL.HW_CTRL_2[4] - 0 - 0 - - - CTRL.HW_CTRL_1[4] - 0 - 0 - - - CTRL.WK_PUPD_CTRL[7:6] - 0 - 0 - - - CTRL.PWM_FREQ_CTRL[1:0] - 0 - 0 - - - MATH.PWM_DC - 0 - 0.0 - - - CTRL.WK_CTRL_1[7] - 0 - 0 - - - CTRL.HW_CTRL_0[0] - 0 - 0 - - - CTRL.HW_CTRL_0[5] - 0 - 0 - - - CTRL.BUS_CTRL_3[4] - 0 - 0 - - - CTRL.WK_PUPD_CTRL[1:0] - 0 - 0 - - - CTRL.WK_CTRL_0[6] - 0 - 0 - - - CTRL.TIMER_CTRL[3:0] - 0 - 0 - - - CTRL.TIMER_CTRL[6:4] - 0 - 0 - - - CTRL.HW_CTRL_1[5] - 0 - 0 - - - CTRL.HW_CTRL_3[2] - 0 - 0 - - - CTRL.WD_CTRL[5] - 0 - 0 - - - CTRL.HW_CTRL_0[2] - 0 - 0 - - - CTRL.HW_CTRL_2[7:5] - 2 - 2 - - - CTRL.HW_CTRL_2[3:2] - 0 - 0 - - - CTRL.SWK_CAN_FD_CTRL[3:1] - 2 - 0 - - - MATH.Baudrate - 2 - 2 - - - CTRL.SWK_ID0_CTRL[0] - 0 - 0 - - - CTRL.SWK_MASK_IDx_CTRL - 0x00000000 - 0 - - - CTRL.SWK_DLC_CTRL[3:0] - 0 - 0 - - - CTRL.SWK_DATA_H_CTRL - 0x00000000 - 0x00000000 - - - CTRL.SWK_DATA_L_CTRL - 0x00000000 - 0x00000000 - - - CTRL.HW_CTRL_1[3] - 0 - 0 - - - CTRL.HW_CTRL_2[0] - 0 - 0 - - - CTRL.M_S_CTRL[4:3] - 2 - 2 - - - MATH.EN_PN - 1 - 1 - - - CTRL.HW_CTRL_3[1:0] - 1 - 1 - - - CTRL.HW_CTRL_0[6] - 1 - 1 - - - CTRL.SWK_CAN_FD_CTRL[0] - 0 - 0 - - - MATH.DoubleCDRFreq - 0 - 0 - - - CTRL.SWK_IDx_CTRL - 0x00000000 - 0 - - - CTRL.GPIO_CTRL[2:0] - 4 - 4 - - - CTRL.WK_CTRL_1[0] - 0 - 0 - - - CTRL.WK_CTRL_1[5] - 0 - 0 - - - CTRL.WK_CTRL_0[2];CTRL.WD_CTRL[6] - 1 - 1 - - - CTRL.WD_CTRL[4] - 1 - 1 - - - CTRL.WD_CTRL[2:0] - 5 - 5 - - - CTRL.M_S_CTRL[1:0] - 3 - 3 - - - CTRL.HW_CTRL_1[7] - 0 - 0 - - - CTRL.M_S_CTRL[2] - 0 - 0 - - - CTRL.BUS_CTRL_0[2:0] - 3 - 3 - - - \ No newline at end of file diff --git a/cva_asw_m0118/src/TLE9461/TLE94x1.c b/cva_asw_m0118/src/TLE9461/TLE94x1.c deleted file mode 100644 index 73428d2..0000000 --- a/cva_asw_m0118/src/TLE9461/TLE94x1.c +++ /dev/null @@ -1,591 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2019, Infineon Technologies AG - * - * - * Distributed under the Boost Software License, Version 1.0. - * - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - *********************************************************************************************************************/ - - -/****************************************************************************************************//** - * @file TLE94x1.c - * - * @brief Implementation of main library functions - * - * @version V1.0.1 - * @date 05. October 2020 - * @author Markus Noll / markus.noll@infineon.com - * @author Yannek Micha Rixen / Yannek.Rixen@infineon.com - ********************************************************************************************************/ - - - -/* ================================================================================ */ -/* ============================ HEADER FILES ================================ */ -/* ================================================================================ */ - -#include "TLE94x1.h" -#include "SBC_TLE94x1.h" -#include - - -/* ================================================================================ */ -/* ============================== Variables ================================= */ -/* ================================================================================ */ - - -/* -------------------------------- ISR Handling --------------------------------- */ - -static SBC_Func_Callback SBC_ISR_Callbacks[30]; -static uint32_t SBC_ISR_Vectors[30]; -static uint8_t SBC_ISR_ReadOutRegs[30]; -static uint8_t SBC_ISR_ReadOutVals[30]; -static uint8_t SBC_RegisteredCallbacks = 0; -static uint8_t SBC_RegisteredRedoutRegs = 0; - - - -/* ================================================================================ */ -/* =========================== Library Functions ============================ */ -/* ================================================================================ */ - - -/* -------------------------------- Main Functions ------------------------------- */ - - -SBC_ErrorCode SBC_WD_Trigger(void) { - /* Read WD config out of SBC and write back to trigger WD */ - uint8_t WD_Data = (uint8_t)SBC_Read_Command(SBC_WD_CTRL); - return SBC_Write_Reg(SBC_WD_CTRL, WD_Data, NULL); -} - - -uint16_t SBC_Read_Command(uint8_t SBC_Reg) { - /* Read and return data - Bit[15:8] = Status Information Field - Bit [7:0] Register data */ - return SBC_SPI_TRANSFER16(SBC_Read_Mask & SBC_Reg, 0x00U); -} - - -uint8_t SBC_Read_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos) { - uint8_t data = ((uint8_t)SBC_Read_Command(SBC_Reg)) & 0xFFU; - return (data & SBC_FieldMsk) >> SBC_FieldPos; -} - - -SBC_ErrorCode SBC_Write_Reg(uint8_t SBC_Reg, uint8_t SBC_Val, uint16_t * returnval) { - SBC_ErrorCode errCode; - uint16_t returndata = SBC_SPI_TRANSFER16(SBC_Write_Bit | SBC_Reg, SBC_Val); - if(returnval != NULL) { - *returnval = returndata; - } - - errCode.SBC_Register = SBC_Reg; - errCode.flippedBitsMask = ((uint8_t)SBC_Read_Command(SBC_Reg)) ^ SBC_Val; - errCode.expectedValue = SBC_Val; - return errCode; -} - - -SBC_ErrorCode SBC_Write_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos, uint8_t SBC_FieldVal, uint16_t * returnval) { - SBC_ErrorCode errCode; - - /* Read data out of register to be manipulated */ - uint16_t returndata = SBC_Read_Command(SBC_Reg); - if(returnval != NULL) { - *returnval = returndata; - } - uint8_t data = (uint8_t)returndata; - - /* Set the used bit field to all 0 */ - data &= ~(SBC_FieldMsk); - - /* Configure new data to bit field */ - data |= (SBC_FieldVal << SBC_FieldPos); - - (void)SBC_SPI_TRANSFER16(SBC_Write_Bit | SBC_Reg, data); - - errCode.SBC_Register = SBC_Reg; - errCode.expectedValue = (SBC_FieldVal << SBC_FieldPos); - uint8_t actualValue = ((uint8_t)SBC_Read_Command(SBC_Reg)) & SBC_FieldMsk; - errCode.flippedBitsMask = errCode.expectedValue ^ actualValue; - return errCode; -} - - -SBC_ErrorCode SBC_Init(void) { - SBC_ErrorCode errCode; - uint8_t WD_Checksum = CTRL_WD_CTRL; - uint8_t WD_CTRL = CTRL_WD_CTRL; - uint8_t SWK_ID3_CTRL, SWK_ID2_CTRL, SWK_ID1_CTRL, SWK_ID0_CTRL; - uint8_t SWK_MASK_ID3_CTRL, SWK_MASK_ID2_CTRL, SWK_MASK_ID1_CTRL, SWK_MASK_ID0_CTRL; - uint8_t SWK_CAN_FD_CTRL = CTRL_SWK_CAN_FD_CTRL; - - /* Calculate checksum */ - WD_Checksum = WD_Checksum ^ WD_Checksum >> 4; - WD_Checksum = WD_Checksum ^ WD_Checksum >> 2; - WD_Checksum = WD_Checksum ^ WD_Checksum >> 1; - - if((WD_Checksum & 1) > 0) { - /* Set parity bit */ - WD_CTRL = CTRL_WD_CTRL | 0x80U; - } - - /* Check if ID is configured to be extended */ - if((CTRL_SWK_ID0_CTRL & SBC_SWK_ID0_CTRL_IDE_Msk) == SBC_IDE_EXTENDED) { - /* extended ID */ - uint32_t SWK_ID_CTRL = CTRL_SWK_IDx_CTRL << 3; - uint32_t SWK_MASK_ID_CTRL = CTRL_SWK_MASK_IDx_CTRL << 3; - - SWK_ID3_CTRL = (uint8_t)(SWK_ID_CTRL >> 24); - SWK_ID2_CTRL = (uint8_t)(SWK_ID_CTRL >> 16); - SWK_ID1_CTRL = (uint8_t)(SWK_ID_CTRL >> 8); - SWK_ID0_CTRL = (((uint8_t)(SWK_ID_CTRL >> 1)) & SBC_SWK_ID0_CTRL_ID4_0_Msk) | SBC_IDE_EXTENDED; - SWK_MASK_ID3_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 24); - SWK_MASK_ID2_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 16); - SWK_MASK_ID1_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 8); - SWK_MASK_ID0_CTRL = (((uint8_t)(SWK_MASK_ID_CTRL >> 1)) & SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk); - } else { - /* Standard length ID */ - uint16_t SWK_ID_CTRL = CTRL_SWK_IDx_CTRL; - uint32_t SWK_MASK_ID_CTRL = CTRL_SWK_MASK_IDx_CTRL; - - SWK_ID3_CTRL = (uint8_t)(SWK_ID_CTRL >> 3); - SWK_ID2_CTRL = (uint8_t)(SWK_ID_CTRL << 5); - SWK_ID1_CTRL = 0x00U; - SWK_ID0_CTRL = 0x00U; - SWK_MASK_ID3_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 3); - SWK_MASK_ID2_CTRL = (uint8_t)(SWK_MASK_ID_CTRL << 5); - SWK_MASK_ID1_CTRL = 0x00U; - SWK_MASK_ID0_CTRL = 0x00U; - } - - /* DIS_ERR_CNT is set only when FD Tolerance is set. */ - if((CTRL_SWK_CAN_FD_CTRL & SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk) == SBC_CAN_FD_EN_ENABLED) { - SWK_CAN_FD_CTRL &= SBC_DIS_ERR_CNT_DISABLED << SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos; - } - - /* Describes initialization sequence */ - uint8_t initSequence[39][2] = { - {SBC_WD_CTRL, WD_CTRL}, - {SBC_M_S_CTRL, CTRL_M_S_CTRL}, - {SBC_HW_CTRL_0, CTRL_HW_CTRL_0}, - {SBC_HW_CTRL_3, CTRL_HW_CTRL_3}, - {SBC_BUS_CTRL_3, CTRL_BUS_CTRL_3}, - {SBC_WK_CTRL_0, CTRL_WK_CTRL_0}, - {SBC_WK_CTRL_1, CTRL_WK_CTRL_1}, - {SBC_WK_PUPD_CTRL, CTRL_WK_PUPD_CTRL}, - {SBC_TIMER_CTRL, CTRL_TIMER_CTRL}, - {SBC_PWM_FREQ_CTRL, CTRL_PWM_FREQ_CTRL}, /* The desired duty cycle should be set first before GPIO is enabled as PWM HS or PWM LS. */ - {SBC_PWM_CTRL, CTRL_PWM_CTRL}, - {SBC_GPIO_CTRL, CTRL_GPIO_CTRL}, - {SBC_HW_CTRL_1, CTRL_HW_CTRL_1}, /* May lock configuration (CFG_LOCK_0) */ - {SBC_HW_CTRL_2, CTRL_HW_CTRL_2}, /* May lock configuration (CFG_LOCK_1) */ - {SBC_BUS_CTRL_0, CTRL_BUS_CTRL_0}, - - /* -------------------------- SELECTIVE WAKE REGISTERS --------------------------- */ - - /* Configuring CDR */ - {SBC_SWK_CDR_CTRL2, CTRL_SWK_CDR_CTRL2}, - {SBC_SWK_BTL0_CTRL, CTRL_SWK_BTL0_CTRL}, - {SBC_SWK_CDR_LIMIT_HIGH_CTRL, CTRL_SWK_CDR_LIMIT_HIGH_CTRL}, - {SBC_SWK_CDR_LIMIT_LOW_CTRL, CTRL_SWK_CDR_LIMIT_LOW_CTRL}, - {SBC_SWK_CDR_CTRL1, (SBC_SEL_FILT_TC16 << SBC_SWK_CDR_CTRL1_SEL_FILT_Pos) | (SBC_CDR_EN_ENABLED << SBC_SWK_CDR_CTRL1_CDR_EN_Pos)}, - - - /* Set ID */ - {SBC_SWK_ID3_CTRL, SWK_ID3_CTRL}, - {SBC_SWK_ID2_CTRL, SWK_ID2_CTRL}, - {SBC_SWK_ID1_CTRL, SWK_ID1_CTRL}, - {SBC_SWK_ID0_CTRL, SWK_ID0_CTRL}, - - /* Set Mask */ - {SBC_SWK_MASK_ID3_CTRL, SWK_MASK_ID3_CTRL}, - {SBC_SWK_MASK_ID2_CTRL, SWK_MASK_ID2_CTRL}, - {SBC_SWK_MASK_ID1_CTRL, SWK_MASK_ID1_CTRL}, - {SBC_SWK_MASK_ID0_CTRL, SWK_MASK_ID0_CTRL}, - - /* Set Data */ - {SBC_SWK_DATA7_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 24)}, - {SBC_SWK_DATA6_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 16)}, - {SBC_SWK_DATA5_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 8)}, - {SBC_SWK_DATA4_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 0)}, - {SBC_SWK_DATA3_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 24)}, - {SBC_SWK_DATA2_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 16)}, - {SBC_SWK_DATA1_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 8)}, - {SBC_SWK_DATA0_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 0)}, - - /* Set DLC */ - {SBC_SWK_DLC_CTRL, CTRL_SWK_DLC_CTRL}, - - {SBC_SWK_CAN_FD_CTRL, SWK_CAN_FD_CTRL}, - - /* End Configuration */ - {0x00U, 0x00U} - }; - - /* Call SPI Init */ - if(SBC_SPI_INIT() != 0) { - errCode.SBC_Register = 0x00; - errCode.flippedBitsMask = 0xFF; - errCode.expectedValue = 0x00; - return errCode; - }; - - uint8_t i = 0; - - /* Write all initialization items to Lite SBC */ - while(initSequence[i][0] != 0x00U || initSequence[i][1] != 0x00U) { - errCode = SBC_Write_Reg(initSequence[i][0], initSequence[i][1], NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - i++; - } - - errCode.SBC_Register = 0x00; - errCode.flippedBitsMask = 0x00; - errCode.expectedValue = 0x00; - return errCode; -} - - - -/* -------------------------------- ISR Functions -------------------------------- */ - - -void SBC_Register_Callback(uint32_t ISR_Vector, void (*Callback_Handler)(uint8_t callbackHandler)) { - /* Save callback */ - SBC_ISR_Callbacks[SBC_RegisteredCallbacks] = Callback_Handler; - - /* Save callback vector */ - SBC_ISR_Vectors[SBC_RegisteredCallbacks] = ISR_Vector; - - /* Check if the register will be readout already to avoid double-readout later */ - uint8_t RegFound = 0; - for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) { - if (SBC_ISR_ReadOutRegs[i] == (ISR_Vector >> 24)) { - RegFound = 1; - } - } - - /* If readout status-reg was not found, register in the readout list */ - if (RegFound == 0) { - SBC_ISR_ReadOutRegs[SBC_RegisteredRedoutRegs] = (uint8_t)(ISR_Vector >> 24); - SBC_RegisteredRedoutRegs++; - } - - SBC_RegisteredCallbacks++; -} - - -SBC_ErrorCode SBC_ISR(void) { - SBC_ErrorCode errCode; - - /* Readout all registered status-registers */ - for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) { - SBC_ISR_ReadOutVals[i] = (uint8_t) SBC_Read_Command(SBC_ISR_ReadOutRegs[i]); - } - - /* Handle all interrupts */ - for (uint8_t i = 0; i < SBC_RegisteredCallbacks; i++) { - /* Decode ISR Vector */ - uint8_t Compare = (uint8_t)SBC_ISR_Vectors[i]; - uint8_t FieldPos = (uint8_t)(SBC_ISR_Vectors[i] >> 8); - uint8_t FieldMsk = (uint8_t)(SBC_ISR_Vectors[i] >> 16); - uint8_t RegAddr = (uint8_t)(SBC_ISR_Vectors[i] >> 24); - - /* Readback of associated status-bit */ - uint8_t ReadBack = 0; - for (uint8_t j = 0; j < SBC_RegisteredRedoutRegs; j++) { - if (SBC_ISR_ReadOutRegs[j] == RegAddr) { - ReadBack = SBC_ISR_ReadOutVals[j]; - break; - } - } - - /* If compare-values matched -> proceed callback and clear field */ - if (((ReadBack & FieldMsk) >> FieldPos) == Compare) { - SBC_ISR_Callbacks[i](ReadBack); - } - } - - /* Clear all ISR related registers */ - for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) { - errCode = SBC_Write_Reg(SBC_ISR_ReadOutRegs[i], 0x00U, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - } - - errCode.SBC_Register = 0x00U; - errCode.flippedBitsMask = 0x00U; - errCode.expectedValue = 0x00U; - return errCode; -} - - - -/* -------------------------------- API Calls ----------------------------------- */ - -SBC_ErrorCode SBC_Mode_Normal(void) { - return SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_NORMAL, NULL); -} - - -SBC_ErrorCode SBC_Mode_Stop(void) { - return SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_STOP, NULL); -} - - -SBC_ErrorCode SBC_Mode_Sleep(void) { - uint8_t registerReadOut; - - SBC_ErrorCode errCode; - - /* If CAN PN is configured */ - if(MATH_EN_PN != 0) { - - /* Reading value of SWK_STAT. */ - registerReadOut = (uint8_t)SBC_Read_Command(SBC_SWK_STAT); - - /* CAN Protocol Handler in sync? The selective wake routine should be aborted if sync is not set. Note: for SYNC to be set the transceiver must have been in Normal Mode and a valid CAN communication must have been sent on the bus by any node. */ - if((registerReadOut & SBC_SWK_STAT_SYNC_Msk) >> SBC_SWK_STAT_SYNC_Pos != SBC_SYNC_VALID_FRAME_RECEIVED) { - errCode.SBC_Register = SBC_SWK_STAT; - errCode.flippedBitsMask = SBC_SWK_STAT_SYNC_Msk; - errCode.expectedValue = SBC_SYNC_VALID_FRAME_RECEIVED << SBC_SWK_STAT_SYNC_Pos; - return errCode; - } - - /* Set SWK Configuration valid */ - errCode = SBC_Write_RegField(SBC_SWK_CTRL, SBC_SWK_CTRL_CFG_VAL_Msk, SBC_SWK_CTRL_CFG_VAL_Pos, SBC_CFG_VAL_VALID, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - - /* Clear SYSERR bit */ - errCode = SBC_Write_RegField(SBC_BUS_STAT, SBC_BUS_STAT_SYSERR_Msk, SBC_BUS_STAT_SYSERR_Pos, 0x00, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - /* Set CAN Mode to off and once again to desired configuration */ - errCode = SBC_Write_Reg(SBC_BUS_CTRL_0, 0x03, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - errCode = SBC_Write_Reg(SBC_BUS_CTRL_0, CTRL_BUS_CTRL_0, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - /* Check SWK_STAT for SYNC == 1 && SWK_SET == 1 && WUF == 0 && WUP == 0. Ignore CANSIL */ - registerReadOut = (uint8_t)SBC_Read_Command(SBC_SWK_STAT); - if( ((SBC_SWK_STAT_SYNC_Msk & registerReadOut) == SBC_SWK_STAT_SYNC_Msk) - && ((SBC_SWK_STAT_SWK_SET_Msk & registerReadOut) == SBC_SWK_STAT_SWK_SET_Msk) - && ((SBC_SWK_STAT_WUP_Msk & registerReadOut) != SBC_SWK_STAT_WUP_Msk) - && ((SBC_SWK_STAT_WUF_Msk & registerReadOut) != SBC_SWK_STAT_WUF_Msk)) { - /* Empty */ - } else { - errCode.SBC_Register = SBC_SWK_STAT; - errCode.expectedValue = 0b01000100U; - errCode.flippedBitsMask = errCode.expectedValue ^ registerReadOut; - return errCode; - } - - - - } - - - - /* Clear Wake Status Registers, so that SBC can sleep. */ - errCode = SBC_Write_Reg(SBC_WK_STAT_0, 0x00, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - errCode = SBC_Write_Reg(SBC_WK_STAT_1, 0x00, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - /* Select sleep mode */ - (void)SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_SLEEP, NULL); - registerReadOut = (uint8_t)SBC_Read_Command(SBC_M_S_CTRL); - - /* This piece of code is ideally never reached as the microcontroller should be already turned off then */ - if(registerReadOut != 0) { - errCode.SBC_Register = SBC_M_S_CTRL; - errCode.flippedBitsMask = registerReadOut; - errCode.expectedValue = 0x00U; - return errCode; - } - - errCode.SBC_Register = 0x00U; - errCode.flippedBitsMask = 0x00U; - errCode.expectedValue = 0x00U; - return errCode; -} - - -SBC_ErrorCode SBC_Set_DutyCycle_PWM (uint8_t PWM_DC) { - return SBC_Write_Reg(SBC_PWM_CTRL, PWM_DC, NULL); -} - - -SBC_ErrorCode SBC_Set_Timer_On (uint8_t OnTime) { - return SBC_Write_RegField(SBC_TIMER_CTRL, SBC_TIMER_CTRL_TIMER_ON_Msk, SBC_TIMER_CTRL_TIMER_ON_Pos, OnTime, NULL); -} - - -SBC_ErrorCode SBC_Set_Timer_Period (uint8_t Period) { - return SBC_Write_RegField(SBC_TIMER_CTRL, SBC_TIMER_CTRL_TIMER_PER_Msk, SBC_TIMER_CTRL_TIMER_PER_Pos, Period, NULL); -} - - -SBC_ErrorCode SBC_FO_Test_On(void) { - return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_FO_ON_Msk, SBC_HW_CTRL_0_FO_ON_Pos, SBC_FO_ON_ACTIVE, NULL); -} - - -SBC_ErrorCode SBC_FO_Test_Off(void) { - return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_FO_ON_Msk, SBC_HW_CTRL_0_FO_ON_Pos, SBC_FO_ON_NOT_ACTIVE, NULL); -} - - -SBC_ErrorCode SBC_CP_On(void) { - return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_CP_EN_Msk, SBC_HW_CTRL_0_CP_EN_Pos, SBC_CP_EN_ON, NULL); -} - - -SBC_ErrorCode SBC_CP_Off(void) { - return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_CP_EN_Msk, SBC_HW_CTRL_0_CP_EN_Pos, SBC_CP_EN_OFF, NULL); -} - - -SBC_ErrorCode SBC_WK_MEAS_On(void) { - return SBC_Write_RegField(SBC_WK_CTRL_1, SBC_WK_CTRL_1_WK_MEAS_Msk, SBC_WK_CTRL_1_WK_MEAS_Pos, SBC_WK_MEAS_WK_AS_VOLTAGESENSING, NULL); -} - - -SBC_ErrorCode SBC_WK_MEAS_Off(void) { - return SBC_Write_RegField(SBC_WK_CTRL_1, SBC_WK_CTRL_1_WK_MEAS_Msk, SBC_WK_CTRL_1_WK_MEAS_Pos, SBC_WK_MEAS_WK_AS_WAKEUP, NULL); -} - - -SBC_ErrorCode SBC_TIMER_WK_EN_On(void) { - return SBC_Write_RegField(SBC_WK_CTRL_0, SBC_WK_CTRL_0_TIMER_WK_EN_Msk, SBC_WK_CTRL_0_TIMER_WK_EN_Pos, WK_CTRL_0_TIMER_WK_EN_WAKESOURCE, NULL); -} - - -SBC_ErrorCode SBC_TIMER_WK_EN_Off(void) { - return SBC_Write_RegField(SBC_WK_CTRL_0, SBC_WK_CTRL_0_TIMER_WK_EN_Msk, SBC_WK_CTRL_0_TIMER_WK_EN_Pos, WK_CTRL_0_TIMER_WK_EN_WAKEUP_DISABLED, NULL); -} - - -uint16_t SBC_SYS_STAT_Read(void) { - uint16_t systemStatus = 0; - uint16_t returndata = SBC_Read_Command(SBC_SYS_STATUS_CTRL_0); - systemStatus = returndata & 0x00FFU; - systemStatus |= SBC_Read_Command(SBC_SYS_STATUS_CTRL_1) << 8; - return systemStatus; -} - - -SBC_ErrorCode SBC_SYS_STAT_Write(uint16_t SystemStatus) { - SBC_ErrorCode errCode; - - /* Write lower bits */ - errCode = SBC_Write_Reg(SBC_SYS_STATUS_CTRL_0, (uint8_t)SystemStatus, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - /* Write higher bits */ - return SBC_Write_Reg(SBC_SYS_STATUS_CTRL_1, (uint8_t)(SystemStatus >> 8), NULL); -} - - -SBC_ErrorCode SBC_Lock_Configuration(void) { - SBC_ErrorCode errCode; - - /* Lock CP_EN and GPIO cannot be modified */ - errCode = SBC_Write_RegField(SBC_HW_CTRL_1, SBC_HW_CTRL_1_CFG_LOCK_0_Msk, SBC_HW_CTRL_1_CFG_LOCK_0_Pos, SBC_CFG_LOCK_0_LOCKED, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - /* Lock Bits with bit type ‘rwl’ (except CP_EN and GPIO) until next device power-up. */ - errCode = SBC_Write_RegField(SBC_HW_CTRL_2, SBC_HW_CTRL_2_CFG_LOCK_1_Msk, SBC_HW_CTRL_2_CFG_LOCK_1_Pos, SBC_CFG_LOCK_1_LOCKED, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - errCode.SBC_Register = 0x00; - errCode.flippedBitsMask = 0x00; - errCode.expectedValue = 0x00; - return errCode; -} - - -SBC_ErrorCode SBC_Unlock_Configuration(void) { - SBC_ErrorCode errCode; - - /* Unlock CP_EN and GPIO configuration. */ - errCode = SBC_Write_RegField(SBC_HW_CTRL_1, SBC_HW_CTRL_1_CFG_LOCK_0_Msk, SBC_HW_CTRL_1_CFG_LOCK_0_Pos, SBC_CFG_LOCK_0_NOTLOCKED, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - /* Unlock Bits with bit type ‘rwl’ (except CP_EN and GPIO). */ - errCode = SBC_Write_RegField(SBC_HW_CTRL_2, SBC_HW_CTRL_2_CFG_LOCK_1_Msk, SBC_HW_CTRL_2_CFG_LOCK_1_Pos, SBC_CFG_LOCK_1_NOTLOCKED, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - errCode.SBC_Register = 0x00; - errCode.flippedBitsMask = 0x00; - errCode.expectedValue = 0x00; - return errCode; -} - -SBC_ErrorCode SBC_Clear_Wake_Status(void) { - SBC_ErrorCode errCode = SBC_Write_Reg(SBC_WK_STAT_0, 0x00, NULL); - if(errCode.flippedBitsMask != 0) { - return errCode; - } - errCode = SBC_Write_Reg(SBC_WK_STAT_1, 0x00, NULL); - if(errCode.flippedBitsMask != 0) { - return errCode; - } - errCode.SBC_Register = 0x00; - errCode.flippedBitsMask = 0x00; - errCode.expectedValue = 0x00; - return errCode; -} diff --git a/cva_asw_m0118/src/TLE9461/TLE94x1.h b/cva_asw_m0118/src/TLE9461/TLE94x1.h deleted file mode 100644 index a434389..0000000 --- a/cva_asw_m0118/src/TLE9461/TLE94x1.h +++ /dev/null @@ -1,393 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2019, Infineon Technologies AG - * - * - * Distributed under the Boost Software License, Version 1.0. - * - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - *********************************************************************************************************************/ - - -/****************************************************************************************************//** - * @file TLE94x1.h - * - * @brief Main header declaration file for TLE94x1 SBC family device - * - * @version V1.0.0 - * @date 15. April 2019 - * @author Markus Noll / markus.noll@infineon.com - * @author Yannek Micha Rixen / Yannek.Rixen@infineon.com - *******************************************************************************************************/ - - - - -#ifndef TLE94x1_H -#define TLE94x1_H - - - - - - -/* ================================================================================ */ -/* ============================ HEADER FILES ================================ */ -/* ================================================================================ */ - - - -#include "TLE94x1_DEFINES.h" -#include "TLE94x1_ISR.h" -#include "TLE94x1_SPI.h" -#include - - - - -/* ================================================================================ */ -/* ================================ MACROS ================================== */ -/* ================================================================================ */ - - -/** - * @def SBC_Write_Bit - * - * @brief This bit has to be set in order to write to a register. - */ -#define SBC_Write_Bit (0x80U) - -/** - * @def SBC_Read_Mask - * - * @brief A mask to prevent the user from accidentally writing to a register. - */ -#define SBC_Read_Mask (0x7FU) - - - - -/* ================================================================================ */ -/* =========================== Library Functions ============================ */ -/* ================================================================================ */ - -struct __SBC_ErrorCode; - -/** - * @brief A structure for simple error readout. - * - * flippedBitsMask is greater than 0 if the value read from the register at SBC_Register differs from expectedValue. - */ -typedef struct __SBC_ErrorCode { - uint8_t SBC_Register; //!< The register where an error occurred. - uint8_t flippedBitsMask; //!< Masks the bits that differ from the expected value. Is 0 if readout is as expected. - uint8_t expectedValue; //!< Expected readout of the register. -} SBC_ErrorCode; - -/** - * @brief Typedef for interrupt callbacks. - */ -typedef void (*SBC_Func_Callback)(uint8_t callbackHandler); - - - - - - -/* -------------------------------- Main Functions ------------------------------- */ - - -/** - * @brief This method will trigger the watchdog. - * - * The function must be called periodically according to the configured watchdog-time. - */ -SBC_ErrorCode SBC_WD_Trigger(void); - - -/** - * @brief This method will proceed a readout of a register. - * - * @param SBC_Reg Address of the register to be read out. See TLE94x1_DEFINES.h for definitions - * @retval A 16 bit value will be returned. - * Bit[15:8] is the Status-Information-Field, Bit [7:0] is the read register-value. - * For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet. - */ -uint16_t SBC_Read_Command(uint8_t SBC_Reg); - - -/** - * @brief This method will proceed a readout of a dedicated bitfield within a register - * - * @param SBC_Reg Address of the register to be readout. See TLE94x1_DEFINES.h for definitions - * @param SBC_FieldMsk Bit mask of the field to be readout. See TLE94x1_DEFINES.h for definitions - * @param SBC_FieldPos Bit position of the field to be readout. See TLE94x1_DEFINES.h for definitions - * - * - * @retval A 8 bit value will be returned and includes the data of the bitfield to be read out * - */ -uint8_t SBC_Read_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos); - - - -/** - * @brief Writes a whole byte to a register and verifies it. - * - * @param SBC_Reg Address of the register to be manipulated. See TLE94x1_DEFINES.h for definitions - * @param SBC_Val Byte to write to SBC_Reg - * @param *returnval A 16 bit value will be returned. - * Bit[15:8] is the Status-Information-Field, Bit [7:0] is the value of the manipulated register before write - * For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet. - * - * @retval See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Write_Reg(uint8_t SBC_Reg, uint8_t SBC_Val, uint16_t * returnval); - - -/** - * @brief This method can be used for manipulating a single bit-field in a control-register. - * - * It will readout the old value of the registers, manipulate the desired bit-field and keep - * the other bit-configuration as it was. - * For usage examples have a look at the implementations of different API calls below. - * - * @param SBC_Reg Address of the register to be manipulated. See TLE94x1_DEFINES.h for definitions - * @param SBC_FieldMsk Bit mask of the field to manipulate. See TLE94x1_DEFINES.h for definitions - * @param SBC_FieldPos Bit position of the field to manipulate. See TLE94x1_DEFINES.h for definitions - * @param SBC_FieldVal New value which will be written to the bit-field. See TLE94x1_DEFINES.h for enumerations - * @param *returnval A 16 bit value will be returned. - * Bit[15:8] is the Status-Information-Field, Bit [7:0] is the value of the manipulated register before write - * For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet. - * - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - * - */ -SBC_ErrorCode SBC_Write_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos, uint8_t SBC_FieldVal, uint16_t * returnval); - - -/** - * @brief This method must be called one time at startup of the microcontroller. - * - * This method will initialize all registers of the SBC with the configuration-data of SBC_TLE94x1.h. - * After this, the SBC can be used as normal. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Init(void); - -/* -------------------------------- ISR Functions -------------------------------- */ - - -/** - * @brief This function can register a self-defined function to a specific interrupt-event of the SBC. - * - * Everytime the SBC_ISR() method is called and the associated status-bit is set, it will consider to - * proceed a callback to this function later. - * See all the possible ISR_Vectors in the TLE94x1_ISR.h - * - * - * @param ISR_Vector Definition of the interrupt event. See all possible events in TLE94x1_ISR.h - * - * @param *Callback_Handler Pointer to the function which will be called back. - * The function must accept a uint8_t as first argument. - */ -void SBC_Register_Callback(uint32_t ISR_Vector, void (*Callback_Handler)(uint8_t callbackHandler)); - - -/** - * @brief Interrupt Service Routine for handling interrupts. - * - * This method must be called automatically everytime a rising-edge on the INTN pin is recognized. - * In case, the INTN pin is not connected, this method can also be called periodically by the user during runtime. - * The ISR will proceed a readout of all registered interrupts. If a status-bit of a registered interrupt is set, - * it will initiate a callback to the registered function and give the registered function the status-register value - * as a parameter. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_ISR(void); - - - -/* -------------------------------- API Calls ----------------------------------- */ - -/** - * @brief Enters SBC normal mode - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Mode_Normal(void); - - -/** - * @brief Enters SBC stop mode - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Mode_Stop(void); - - -/** - * @brief Clears all wake status registers and enter SBC sleep mode. Depending on configuration also the selective-wake feature will be initialized - * before entering sleep mode. In case, the SWK option is enabled and the internal CAN protocol handler is not in sync when calling this function, - * the sleep mode will be not entered. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Mode_Sleep(void); - - -/** - * @brief Sets the duty-cycle of the internal PWM generator - * - * @param PWM_DC Set the duty-cycle with values of 0-255 for 0% to 100% - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Set_DutyCycle_PWM(uint8_t PWM_DC); - - -/** - * @brief Sets the OnTime of the internal timer. - * - * @param OnTime On time which will be configured to the timer. See TLE94x1_DEFINES.h for enumerations. - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Set_Timer_On(uint8_t OnTime); - -/** - * @brief Sets the Period time of the internal timer - * - * @param Period Period time which will be configured to the timer. See TLE94x1_DEFINES.h for enumerations. - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Set_Timer_Period(uint8_t Period); - - -/** - * @brief FO output activated by software for testing. Only working if FO/GPIO is configured as FO - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_FO_Test_On(void); - - -/** - * @brief FO output deactivated by software for testing. Only working if FO/GPIO is configured as FO - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_FO_Test_Off(void); - - -/** - * @brief Charge-Pump (VCP-Pin) is enabled. See chapter 5.3 in datasheet. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_CP_On(void); - - -/** - * @brief Charge-Pump (VCP-Pin) is disabled. See chapter 5.3 in datasheet. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_CP_Off(void); - - -/** - * @brief Enable Voltage Sensing. No wake-up events are generated. See chapter 9.2.4 in datasheet. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_WK_MEAS_On(void); - - -/** - * @brief Disable Voltage Sensing and enable wake-up functionality. See chapter 9.2.4 in datasheet. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_WK_MEAS_Off(void); - - -/** - * @brief WK is enabled as wake source. See chapter 5.2. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_TIMER_WK_EN_On(void); - - -/** - * @brief WK wake-up disabled. See chapter 5.2. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_TIMER_WK_EN_Off(void); - - -/** - * @brief Reads System Status Control, both lower and higher bits. See page 138 in datasheet. - * - * @retval Upper 8 bit are read from register SBC_SYS_STATUS_CTRL_1 and the lower 8 bit from SBC_SYS_STATUS_CTRL_0 - */ -uint16_t SBC_SYS_STAT_Read(void); - - -/** - * @brief Writes System Status Control, both lower and higher bits. See page 138 in datasheet. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_SYS_STAT_Write(uint16_t SystemStatus); - - -/** - * @brief Locks CP_EN, GPIO configuration and 'rwl'-bits. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Lock_Configuration(void); - - -/** - * @brief Unlocks CP_EN, GPIO configuration and 'rwl'-bits. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Unlock_Configuration(void); - - -/** - * @brief Clears both Wake Status registers. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Clear_Wake_Status(void); - -#endif /*TLE94x1_H*/ diff --git a/cva_asw_m0118/src/TLE9461/TLE94x1_DEFINES.h b/cva_asw_m0118/src/TLE9461/TLE94x1_DEFINES.h deleted file mode 100644 index 57d8ab2..0000000 --- a/cva_asw_m0118/src/TLE9461/TLE94x1_DEFINES.h +++ /dev/null @@ -1,3248 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2019, Infineon Technologies AG - * - * - * Distributed under the Boost Software License, Version 1.0. - * - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - *********************************************************************************************************************/ - - -/****************************************************************************************************//** - * @file TLE94x1_DEFINES.h - * - * @brief Main header declaration file for TLE94x1 SBC family device - * - * @version V1.0.0 - * @date 15. April 2019 - * @author Markus Noll / markus.noll@infineon.com - * @author Yannek Micha Rixen / Yannek.Rixen@infineon.com - *******************************************************************************************************/ - - - -#ifndef TLE94x1_DEFINES_H -#define TLE94x1_DEFINES_H - - - - - - -/* ================================================================================ */ -/* ================ General Control Registers ================ */ -/* ================================================================================ */ - - - -/** - * @def SBC_M_S_CTRL - * - * @brief Control register address. - */ -#define SBC_M_S_CTRL (0b00000001U) - -/** - * @def SBC_HW_CTRL_0 - * - * @brief Control register address. - */ -#define SBC_HW_CTRL_0 (0b00000010U) - -/** - * @def SBC_WD_CTRL - * - * @brief Control register address. - */ -#define SBC_WD_CTRL (0b00000011U) - -/** - * @def SBC_BUS_CTRL_0 - * - * @brief Control register address. - */ -#define SBC_BUS_CTRL_0 (0b00000100U) - -/** - * @def SBC_WK_CTRL_0 - * - * @brief Control register address. - */ -#define SBC_WK_CTRL_0 (0b00000110U) - -/** - * @def SBC_WK_CTRL_1 - * - * @brief Control register address. - */ -#define SBC_WK_CTRL_1 (0b00000111U) - -/** - * @def SBC_WK_PUPD_CTRL - * - * @brief Control register address. - */ -#define SBC_WK_PUPD_CTRL (0b00001000U) - -/** - * @def SBC_BUS_CTRL_3 - * - * @brief Control register address. - */ -#define SBC_BUS_CTRL_3 (0b00001011U) - -/** - * @def SBC_TIMER_CTRL - * - * @brief Control register address. - */ -#define SBC_TIMER_CTRL (0b00001100U) - -/** - * @def SBC_HW_CTRL_1 - * - * @brief Control register address. - */ -#define SBC_HW_CTRL_1 (0b00001110U) - -/** - * @def SBC_HW_CTRL_2 - * - * @brief Control register address. - */ -#define SBC_HW_CTRL_2 (0b00001111U) - -/** - * @def SBC_GPIO_CTRL - * - * @brief Control register address. - */ -#define SBC_GPIO_CTRL (0b00010111U) - -/** - * @def SBC_PWM_CTRL - * - * @brief Control register address. - */ -#define SBC_PWM_CTRL (0b00011000U) - -/** - * @def SBC_PWM_FREQ_CTRL - * - * @brief Control register address. - */ -#define SBC_PWM_FREQ_CTRL (0b00011100U) - -/** - * @def SBC_HW_CTRL_3 - * - * @brief Control register address. - */ -#define SBC_HW_CTRL_3 (0b00011101U) - -/** - * @def SBC_SYS_STATUS_CTRL_0 - * - * @brief Control register address. - */ -#define SBC_SYS_STATUS_CTRL_0 (0b00011110U) - -/** - * @def SBC_SYS_STATUS_CTRL_1 - * - * @brief Control register address. - */ -#define SBC_SYS_STATUS_CTRL_1 (0b00011111U) - - - - - - -/* ================================================================================ */ -/* ================ Selective Wake Control Registers ================ */ -/* ================================================================================ */ - - - -/** - * @def SBC_SWK_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_CTRL (0b00100000U) - -/** - * @def SBC_SWK_BTL0_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_BTL0_CTRL (0b00100001U) - -/** - * @def SBC_SWK_BTL1_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_BTL1_CTRL (0b00100010U) - -/** - * @def SBC_SWK_ID3_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_ID3_CTRL (0b00100011U) - -/** - * @def SBC_SWK_ID2_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_ID2_CTRL (0b00100100U) - -/** - * @def SBC_SWK_ID1_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_ID1_CTRL (0b00100101U) - -/** - * @def SBC_SWK_ID0_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_ID0_CTRL (0b00100110U) - -/** - * @def SBC_SWK_MASK_ID3_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_MASK_ID3_CTRL (0b00100111U) - -/** - * @def SBC_SWK_MASK_ID2_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_MASK_ID2_CTRL (0b00101000U) - -/** - * @def SBC_SWK_MASK_ID1_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_MASK_ID1_CTRL (0b00101001U) - -/** - * @def SBC_SWK_MASK_ID0_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_MASK_ID0_CTRL (0b00101010U) - -/** - * @def SBC_SWK_DLC_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DLC_CTRL (0b00101011U) - -/** - * @def SBC_SWK_DATA7_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA7_CTRL (0b00101100U) - -/** - * @def SBC_SWK_DATA6_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA6_CTRL (0b00101101U) - -/** - * @def SBC_SWK_DATA5_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA5_CTRL (0b00101110U) - -/** - * @def SBC_SWK_DATA4_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA4_CTRL (0b00101111U) - -/** - * @def SBC_SWK_DATA3_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA3_CTRL (0b00110000U) - -/** - * @def SBC_SWK_DATA2_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA2_CTRL (0b00110001U) - -/** - * @def SBC_SWK_DATA1_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA1_CTRL (0b00110010U) - -/** - * @def SBC_SWK_DATA0_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA0_CTRL (0b00110011U) - -/** - * @def SBC_SWK_CAN_FD_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_CAN_FD_CTRL (0b00110100U) - -/** - * @def SBC_SWK_OSC_TRIM_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_OSC_TRIM_CTRL (0b00111000U) - -/** - * @def SBC_SWK_OPT_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_OPT_CTRL (0b00111001U) - -/** - * @def SBC_SWK_OSC_CAL_H_STAT - * - * @brief Selective wake register address. - */ -#define SBC_SWK_OSC_CAL_H_STAT (0b00111010U) - -/** - * @def SBC_SWK_OSC_CAL_L_STAT - * - * @brief Selective wake register address. - */ -#define SBC_SWK_OSC_CAL_L_STAT (0b00111011U) - -/** - * @def SBC_SWK_CDR_CTRL1 - * - * @brief Selective wake register address. - */ -#define SBC_SWK_CDR_CTRL1 (0b00111100U) - -/** - * @def SBC_SWK_CDR_CTRL2 - * - * @brief Selective wake register address. - */ -#define SBC_SWK_CDR_CTRL2 (0b00111101U) - -/** - * @def SBC_SWK_CDR_LIMIT_HIGH_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_CDR_LIMIT_HIGH_CTRL (0b00111110U) - -/** - * @def SBC_SWK_CDR_LIMIT_LOW_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_CDR_LIMIT_LOW_CTRL (0b00111111U) - - - - - - -/* ================================================================================ */ -/* ================ General Status Registers ================ */ -/* ================================================================================ */ - - - - -/** - * @def SBC_SUP_STAT_1 - * - * @brief Status register address. - */ -#define SBC_SUP_STAT_1 (0b01000000U) - -/** - * @def SBC_SUP_STAT_0 - * - * @brief Status register address. - */ -#define SBC_SUP_STAT_0 (0b01000001U) - -/** - * @def SBC_THERM_STAT - * - * @brief Status register address. - */ -#define SBC_THERM_STAT (0b01000010U) - -/** - * @def SBC_DEV_STAT - * - * @brief Status register address. - */ -#define SBC_DEV_STAT (0b01000011U) - -/** - * @def SBC_BUS_STAT - * - * @brief Status register address. - */ -#define SBC_BUS_STAT (0b01000100U) - -/** - * @def SBC_WK_STAT_0 - * - * @brief Status register address. - */ -#define SBC_WK_STAT_0 (0b01000110U) - -/** - * @def SBC_WK_STAT_1 - * - * @brief Status register address. - */ -#define SBC_WK_STAT_1 (0b01000111U) - -/** - * @def SBC_WK_LVL_STAT - * - * @brief Status register address. - */ -#define SBC_WK_LVL_STAT (0b01001000U) - -/** - * @def SBC_GPIO_OC_STAT - * - * @brief Status register address. - */ -#define SBC_GPIO_OC_STAT (0b01010100U) - -/** - * @def SBC_GPIO_OL_STAT - * - * @brief Status register address. - */ -#define SBC_GPIO_OL_STAT (0b01010101U) - - - - - - -/* ================================================================================ */ -/* ================ Selective Wake Status Registers ================ */ -/* ================================================================================ */ - - - - -/** - * @def SBC_SWK_STAT - * - * @brief Selective wake status register address. - */ -#define SBC_SWK_STAT (0b01110000U) - -/** - * @def SBC_SWK_ECNT_STAT - * - * @brief Selective wake status register address. - */ -#define SBC_SWK_ECNT_STAT (0b01110001U) - -/** - * @def SBC_SWK_CDR_STAT1 - * - * @brief Selective wake status register address. - */ -#define SBC_SWK_CDR_STAT1 (0b01110010U) - -/** - * @def SBC_SWK_CDR_STAT2 - * - * @brief Selective wake status register address. - */ -#define SBC_SWK_CDR_STAT2 (0b01110011U) - -/** - * @def SBC_FAM_PROD_STAT - * - * @brief Selective wake status register address. - */ -#define SBC_FAM_PROD_STAT (0b01111110U) - - - - - - -/* ================================================================================ */ -/* ============ General Control Registers Position & Mask ================ */ -/* ================================================================================ */ - - - -/* -------------------------------- M_S_CTRL ------------------------------------ */ - -/** - * @def SBC_M_S_CTRL_MODE_Pos - * - * @brief Control register bit position. - */ -#define SBC_M_S_CTRL_MODE_Pos (6U) -/** - * @def SBC_M_S_CTRL_MODE_Msk - * - * @brief Control register bit mask. - */ -#define SBC_M_S_CTRL_MODE_Msk (0b11000000U) -/** - * @def SBC_M_S_CTRL_VCC2_ON_Pos - * - * @brief Control register bit position. - */ -#define SBC_M_S_CTRL_VCC2_ON_Pos (3U) -/** - * @def SBC_M_S_CTRL_VCC2_ON_Msk - * - * @brief Control register bit mask. - */ -#define SBC_M_S_CTRL_VCC2_ON_Msk (0b00011000U) -/** - * @def SBC_M_S_CTRL_VCC1_OV_RST_Pos - * - * @brief Control register bit position. - */ -#define SBC_M_S_CTRL_VCC1_OV_RST_Pos (2U) -/** - * @def SBC_M_S_CTRL_VCC1_OV_RST_Msk - * - * @brief Control register bit mask. - */ -#define SBC_M_S_CTRL_VCC1_OV_RST_Msk (0b00000100U) -/** - * @def SBC_M_S_CTRL_VCC1_RT_Pos - * - * @brief Control register bit position. - */ -#define SBC_M_S_CTRL_VCC1_RT_Pos (0U) -/** - * @def SBC_M_S_CTRL_VCC1_RT_Msk - * - * @brief Control register bit mask. - */ -#define SBC_M_S_CTRL_VCC1_RT_Msk (0b00000011U) - - -/* -------------------------------- HW_CTRL_0 ----------------------------------- */ - - -/** - * @def SBC_HW_CTRL_0_SOFT_RESET_RST_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_0_SOFT_RESET_RST_Pos (6U) - -/** - * @def SBC_HW_CTRL_0_SOFT_RESET_RST_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_0_SOFT_RESET_RST_Msk (0b01000000U) - -/** - * @def SBC_HW_CTRL_0_FO_ON_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_0_FO_ON_Pos (5U) - -/** - * @def SBC_HW_CTRL_0_FO_ON_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_0_FO_ON_Msk (0b00100000U) - -/** - * @def SBC_HW_CTRL_0_CP_EN_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_0_CP_EN_Pos (2U) - -/** - * @def SBC_HW_CTRL_0_CP_EN_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_0_CP_EN_Msk (0b00000100U) - -/** - * @def SBC_HW_CTRL_0_CFG1_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_0_CFG1_Pos (0U) - -/** - * @def SBC_HW_CTRL_0_CFG1_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_0_CFG1_Msk (0b00000001U) - - -/* -------------------------------- WD_CTRL ----------------------------------- */ - - -/** - * @def SBC_WD_CTRL_CHECKSUM_Pos - * - * @brief Control register bit position. - */ -#define SBC_WD_CTRL_CHECKSUM_Pos (7U) - -/** - * @def SBC_WD_CTRL_CHECKSUM_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WD_CTRL_CHECKSUM_Msk (0b10000000U) - -/** - * @def SBC_WD_CTRL_WD_STM_EN_0_Pos - * - * @brief Control register bit position. - */ -#define SBC_WD_CTRL_WD_STM_EN_0_Pos (6U) - -/** - * @def SBC_WD_CTRL_WD_STM_EN_0_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WD_CTRL_WD_STM_EN_0_Msk (0b01000000U) - -/** - * @def SBC_WD_CTRL_WD_WIN_Pos - * - * @brief Control register bit position. - */ -#define SBC_WD_CTRL_WD_WIN_Pos (5U) - -/** - * @def SBC_WD_CTRL_WD_WIN_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WD_CTRL_WD_WIN_Msk (0b00100000U) - -/** - * @def SBC_WD_CTRL_WD_EN_WK_BUS_Pos - * - * @brief Control register bit position. - */ -#define SBC_WD_CTRL_WD_EN_WK_BUS_Pos (4U) - -/** - * @def SBC_WD_CTRL_WD_EN_WK_BUS_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WD_CTRL_WD_EN_WK_BUS_Msk (0b00010000U) - -/** - * @def SBC_WD_CTRL_WD_TIMER_Pos - * - * @brief Control register bit position. - */ -#define SBC_WD_CTRL_WD_TIMER_Pos (0U) - -/** - * @def SBC_WD_CTRL_WD_TIMER_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WD_CTRL_WD_TIMER_Msk (0b00000111U) - - -/* -------------------------------- BUS_CTRL_0 ---------------------------------- */ - -/** - * @def SBC_BUS_CTRL_0_CAN_Pos - * - * @brief Control register bit position. - */ -#define SBC_BUS_CTRL_0_CAN_Pos (0U) - -/** - * @def SBC_BUS_CTRL_0_CAN_Msk - * - * @brief Control register bit mask. - */ -#define SBC_BUS_CTRL_0_CAN_Msk (0b00000111U) - - -/* -------------------------------- WK_CTRL_0 ----------------------------------- */ - -/** - * @def SBC_WK_CTRL_0_TIMER_WK_EN_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_CTRL_0_TIMER_WK_EN_Pos (6U) - -/** - * @def SBC_WK_CTRL_0_TIMER_WK_EN_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_CTRL_0_TIMER_WK_EN_Msk (0b01000000U) - -/** - * @def SBC_WK_CTRL_0_WD_STM_EN_1_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_CTRL_0_WD_STM_EN_1_Pos (2U) - -/** - * @def SBC_WK_CTRL_0_WD_STM_EN_1_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_CTRL_0_WD_STM_EN_1_Msk (0b00000100U) - - -/* -------------------------------- WK_CTRL_1 ----------------------------------- */ - - -/** - * @def SBC_WK_CTRL_1_INT_GLOBAL_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_CTRL_1_INT_GLOBAL_Pos (7U) - -/** - * @def SBC_WK_CTRL_1_INT_GLOBAL_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_CTRL_1_INT_GLOBAL_Msk (0b10000000U) - -/** - * @def SBC_WK_CTRL_1_WK_MEAS_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_CTRL_1_WK_MEAS_Pos (5U) - -/** - * @def SBC_WK_CTRL_1_WK_MEAS_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_CTRL_1_WK_MEAS_Msk (0b00100000U) - -/** - * @def SBC_WK_CTRL_1_WK_EN_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_CTRL_1_WK_EN_Pos (0U) - -/** - * @def SBC_WK_CTRL_1_WK_EN_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_CTRL_1_WK_EN_Msk (0b00000001U) - - -/* -------------------------------- WK_PUPD_CTRL -------------------------------- */ - - -/** - * @def SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Pos (6U) - -/** - * @def SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Msk (0b11000000U) - -/** - * @def SBC_WK_PUPD_CTRL_WK_PUPD_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_PUPD_CTRL_WK_PUPD_Pos (0U) - -/** - * @def SBC_WK_PUPD_CTRL_WK_PUPD_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_PUPD_CTRL_WK_PUPD_Msk (0b00000011U) - - -/* ------------------------------- BUS_CTRL_3 ---------------------------------- */ - -/** - * @def SBC_BUS_CTRL_3_CAN_FLASH_Pos - * - * @brief Control register bit position. - */ -#define SBC_BUS_CTRL_3_CAN_FLASH_Pos (4U) - -/** - * @def SBC_BUS_CTRL_3_CAN_FLASH_Msk - * - * @brief Control register bit mask. - */ -#define SBC_BUS_CTRL_3_CAN_FLASH_Msk (0b00010000U) - - -/* ------------------------------- TIMER_CTRL ---------------------------------- */ - - -/** - * @def SBC_TIMER_CTRL_TIMER_ON_Pos - * - * @brief Control register bit position. - */ -#define SBC_TIMER_CTRL_TIMER_ON_Pos (4U) - -/** - * @def SBC_TIMER_CTRL_TIMER_ON_Msk - * - * @brief Control register bit mask. - */ -#define SBC_TIMER_CTRL_TIMER_ON_Msk (0b01110000U) - -/** - * @def SBC_TIMER_CTRL_TIMER_PER_Pos - * - * @brief Control register bit position. - */ -#define SBC_TIMER_CTRL_TIMER_PER_Pos (0U) - -/** - * @def SBC_TIMER_CTRL_TIMER_PER_Msk - * - * @brief Control register bit mask. - */ -#define SBC_TIMER_CTRL_TIMER_PER_Msk (0b00001111U) - - -/* -------------------------------- HW_CTRL_1 ----------------------------------- */ - - -/** - * @def SBC_HW_CTRL_1_RSTN_HYS_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_1_RSTN_HYS_Pos (7U) - -/** - * @def SBC_HW_CTRL_1_RSTN_HYS_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_1_RSTN_HYS_Msk (0b10000000U) - -/** - * @def SBC_HW_CTRL_1_TSD2_DEL_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_1_TSD2_DEL_Pos (5U) - -/** - * @def SBC_HW_CTRL_1_TSD2_DEL_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_1_TSD2_DEL_Msk (0b00100000U) - -/** - * @def SBC_HW_CTRL_1_RSTN_DEL_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_1_RSTN_DEL_Pos (4U) - -/** - * @def SBC_HW_CTRL_1_RSTN_DEL_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_1_RSTN_DEL_Msk (0b00010000U) - -/** - * @def SBC_HW_CTRL_1_CFG_LOCK_0_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_1_CFG_LOCK_0_Pos (3U) - -/** - * @def SBC_HW_CTRL_1_CFG_LOCK_0_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_1_CFG_LOCK_0_Msk (0b00001000U) - - -/* -------------------------------- HW_CTRL_2 ----------------------------------- */ - - -/** - * @def SBC_HW_CTRL_2_2MHZ_FREQ_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_2_2MHZ_FREQ_Pos (5U) - -/** - * @def SBC_HW_CTRL_2_2MHZ_FREQ_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_2_2MHZ_FREQ_Msk (0b11100000U) - -/** - * @def SBC_HW_CTRL_2_I_PEAK_TH_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_2_I_PEAK_TH_Pos (4U) - -/** - * @def SBC_HW_CTRL_2_I_PEAK_TH_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_2_I_PEAK_TH_Msk (0b00010000U) - -/** - * @def SBC_HW_CTRL_2_SS_MOD_FR_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_2_SS_MOD_FR_Pos (2U) - -/** - * @def SBC_HW_CTRL_2_SS_MOD_FR_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_2_SS_MOD_FR_Msk (0b00001100U) - -/** - * @def SBC_HW_CTRL_2_CFG_LOCK_1_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_2_CFG_LOCK_1_Pos (0U) - -/** - * @def SBC_HW_CTRL_2_CFG_LOCK_1_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_2_CFG_LOCK_1_Msk (0b00000001U) - - -/* -------------------------------- GPIO_CTRL ----------------------------------- */ - -/** - * @def SBC_GPIO_CTRL_GPIO_Pos - * - * @brief Control register bit position. - */ -#define SBC_GPIO_CTRL_GPIO_Pos (0U) - -/** - * @def SBC_GPIO_CTRL_GPIO_Msk - * - * @brief Control register bit mask. - */ -#define SBC_GPIO_CTRL_GPIO_Msk (0b00000111U) - - -/* -------------------------------- PWM_CTRL -------------------------------------- */ - -/** - * @def SBC_PWM_DC_PWM_DC_Pos - * - * @brief Control register bit position. - */ -#define SBC_PWM_CTRL_PWM_DC_Pos (0U) - -/** - * @def SBC_PWM_DC_PWM_DC_Msk - * - * @brief Control register bit mask. - */ -#define SBC_PWM_CTRL_PWM_DC_Msk (0b11111111U) - - -/* -------------------------------- PWM_FREQ_CTRL -------------------------------------- */ - -/** - * @def SBC_PWM_FREQ_CTRL_PWM_FREQ_Pos - * - * @brief Control register bit position. - */ -#define SBC_PWM_FREQ_CTRL_PWM_FREQ_Pos (0U) - - -/** - * @def SBC_PWM_FREQ_CTRL_PWM_FREQ_Msk - * - * @brief Control register bit mask. - */ -#define SBC_PWM_FREQ_CTRL_PWM_FREQ_Msk (0b00000011U) - - -/* -------------------------------- HW_CTRL_3 ----------------------------------- */ - - -/** - * @def SBC_HW_CTRL_3_TSD_THR_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_3_TSD_THR_Pos (2U) - -/** - * @def SBC_HW_CTRL_3_TSD_THR_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_3_TSD_THR_Msk (0b00000100U) - -/** - * @def SBC_HW_CTRL_3_ICC1_LIM_ADJ_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_3_ICC1_LIM_ADJ_Pos (0U) - -/** - * @def SBC_HW_CTRL_3_ICC1_LIM_ADJ_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_3_ICC1_LIM_ADJ_Msk (0b00000011U) - - -/* -------------------------------- SYS_STATUS_CTRL_0 --------------------------- */ - -/** - * @def SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Pos - * - * @brief Control register bit position. - */ -#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Pos (0U) - -/** - * @def SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Msk - * - * @brief Control register bit mask. - */ -#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Msk (0b11111111U) - - -/* -------------------------------- SYS_STATUS_CTRL_1 --------------------------- */ - - -/** - * @def SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Pos - * - * @brief Control register bit position. - */ -#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Pos (0U) - -/** - * @def SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Msk - * - * @brief Control register bit mask. - */ -#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Msk (0b11111111U) - - - - - - -/* ================================================================================ */ -/* ======== Selective Wake Control Registers Position & Mask ============= */ -/* ================================================================================ */ - - - -/* -------------------------------- SWK_CTRL ------------------------------------ */ - - -/** - * @def SBC_SWK_CTRL_OSC_CAL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CTRL_OSC_CAL_Pos (7U) - -/** - * @def SBC_SWK_CTRL_OSC_CAL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CTRL_OSC_CAL_Msk (0b10000000U) - -/** - * @def SBC_SWK_CTRL_TRIM_EN_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CTRL_TRIM_EN_Pos (5U) - -/** - * @def SBC_SWK_CTRL_TRIM_EN_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CTRL_TRIM_EN_Msk (0b01100000U) - -/** - * @def SBC_SWK_CTRL_CANTO_MASK_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CTRL_CANTO_MASK_Pos (4U) - -/** - * @def SBC_SWK_CTRL_CANTO_MASK_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CTRL_CANTO_MASK_Msk (0b00010000U) - -/** - * @def SBC_SWK_CTRL_CFG_VAL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CTRL_CFG_VAL_Pos (0U) - -/** - * @def SBC_SWK_CTRL_CFG_VAL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CTRL_CFG_VAL_Msk (0b00000001U) - - -/* -------------------------------- SWK_BTL0_CTRL ------------------------------- */ - - -/** - * @def SBC_SWK_BTL0_CTRL_TBIT_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_BTL0_CTRL_TBIT_Pos (0U) - -/** - * @def SBC_SWK_BTL0_CTRL_TBIT_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_BTL0_CTRL_TBIT_Msk (0b11111111U) - - -/* -------------------------------- SWK_BTL1_CTRL ------------------------------- */ - - -/** - * @def SBC_SWK_BTL1_CTRL_SP_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_BTL1_CTRL_SP_Pos (0U) - -/** - * @def SBC_SWK_BTL1_CTRL_SP_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_BTL1_CTRL_SP_Msk (0b00111111U) - - -/* -------------------------------- SWK_ID3_CTRL -------------------------------- */ - - -/** - * @def SBC_SWK_ID3_CTRL_ID28_21_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_ID3_CTRL_ID28_21_Pos (0U) - -/** - * @def SBC_SWK_ID3_CTRL_ID28_21_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_ID3_CTRL_ID28_21_Msk (0b11111111U) - - -/* -------------------------------- SWK_ID2_CTRL -------------------------------- */ - - -/** - * @def SBC_SWK_ID2_CTRL_ID20_13_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_ID2_CTRL_ID20_13_Pos (0U) - -/** - * @def SBC_SWK_ID2_CTRL_ID20_13_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_ID2_CTRL_ID20_13_Msk (0b11111111U) - - -/* -------------------------------- SWK_ID1_CTRL -------------------------------- */ - - -/** - * @def SBC_SWK_ID1_CTRL_ID12_5_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_ID1_CTRL_ID12_5_Pos (0U) - -/** - * @def SBC_SWK_ID1_CTRL_ID12_5_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_ID1_CTRL_ID12_5_Msk (0b11111111U) - - -/* -------------------------------- SWK_ID0_CTRL -------------------------------- */ - - -/** - * @def SBC_SWK_ID0_CTRL_ID4_0_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_ID0_CTRL_ID4_0_Pos (2U) - -/** - * @def SBC_SWK_ID0_CTRL_ID4_0_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_ID0_CTRL_ID4_0_Msk (0b01111100U) - -/** - * @def SBC_SWK_ID0_CTRL_RTR_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_ID0_CTRL_RTR_Pos (1U) - -/** - * @def SBC_SWK_ID0_CTRL_RTR_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_ID0_CTRL_RTR_Msk (0b00000010U) - -/** - * @def SBC_SWK_ID0_CTRL_IDE_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_ID0_CTRL_IDE_Pos (0U) - -/** - * @def SBC_SWK_ID0_CTRL_IDE_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_ID0_CTRL_IDE_Msk (0b00000001U) - - -/* -------------------------------- SWK_MASK_ID3_CTRL --------------------------- */ - - -/** - * @def SBC_SWK_MASK_ID3_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_MASK_ID3_CTRL_Pos (0U) - -/** - * @def SBC_SWK_MASK_ID3_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_MASK_ID3_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_MASK_ID2_CTRL --------------------------- */ - - -/** - * @def SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Pos (0U) - -/** - * @def SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Msk (0b11111111U) - - -/* -------------------------------- SWK_MASK_ID1_CTRL --------------------------- */ - - -/** - * @def SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Pos (0U) - -/** - * @def SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Msk (0b11111111U) - - -/* -------------------------------- SWK_MASK_ID0_CTRL --------------------------- */ - - -/** - * @def SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Pos (2U) - -/** - * @def SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk (0b01111100U) - - -/* -------------------------------- SWK_DLC_CTRL -------------------------------- */ - - -/** - * @def SBC_SWK_DLC_CTRL_DLC_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DLC_CTRL_DLC_Pos (0U) - -/** - * @def SBC_SWK_DLC_CTRL_DLC_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DLC_CTRL_DLC_Msk (0b00001111U) - - -/* -------------------------------- SWK_DATA7_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA7_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA7_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA7_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA7_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA6_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA6_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA6_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA6_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA6_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA5_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA5_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA5_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA5_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA5_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA4_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA4_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA4_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA4_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA4_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA3_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA3_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA3_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA3_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA3_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA2_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA2_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA2_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA2_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA2_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA1_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA1_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA1_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA1_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA1_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA0_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA0_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA0_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA0_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA0_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_CAN_FD_CTRL ----------------------------- */ - - -/** - * @def SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos (5U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Msk (0b00100000U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Pos (4U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Msk (0b00010000U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_FD_FILTER_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CAN_FD_CTRL_FD_FILTER_Pos (1U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_FD_FILTER_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CAN_FD_CTRL_FD_FILTER_Msk (0b00001110U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Pos (0U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk (0b00000001U) - - -/* -------------------------------- SWK_OSC_TRIM_CTRL --------------------------- */ - - -/** - * @def SBC_SWK_OSC_TRIM_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_OSC_TRIM_CTRL_Pos (0U) - -/** - * @def SBC_SWK_OSC_TRIM_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_OSC_TRIM_CTRL_Msk (0b01111111U) - - -/* -------------------------------- SWK_OPT_CTRL -------------------------------- */ - - -/** - * @def SBC_SWK_OPT_CTRL_RX_WK_SEL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_OPT_CTRL_RX_WK_SEL_Pos (7U) - -/** - * @def SBC_SWK_OPT_CTRL_RX_WK_SEL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_OPT_CTRL_RX_WK_SEL_Msk (0b10000000U) - - -/* -------------------------------- SWK_OSC_CAL_H_STAT -------------------------- */ - - -/** - * @def SBC_SWK_OSC_CAL_H_STAT_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_OSC_CAL_H_STAT_Pos (0U) - -/** - * @def SBC_SWK_OSC_CAL_H_STAT_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_OSC_CAL_H_STAT_Msk (0b11111111U) - - -/* -------------------------------- SWK_OPT_CAL_L_STAT -------------------------- */ - - -/** - * @def SBC_SWK_OPT_CAL_L_STAT_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_OPT_CAL_L_STAT_Pos (0U) - -/** - * @def SBC_SWK_OPT_CAL_L_STAT_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_OPT_CAL_L_STAT_Msk (0b11111111U) - - -/* -------------------------------- SWK_CDR_CTRL1 ------------------------------- */ - - -/** - * @def SBC_SWK_CDR_CTRL1_SEL_FILT_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CDR_CTRL1_SEL_FILT_Pos (2U) - -/** - * @def SBC_SWK_CDR_CTRL1_SEL_FILT_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CDR_CTRL1_SEL_FILT_Msk (0b00001100U) - -/** - * @def SBC_SWK_CDR_CTRL1_CDR_EN_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CDR_CTRL1_CDR_EN_Pos (0U) - -/** - * @def SBC_SWK_CDR_CTRL1_CDR_EN_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CDR_CTRL1_CDR_EN_Msk (0b00000001U) - - -/* -------------------------------- SWK_CDR_CTRL2 ------------------------------- */ - - -/** - * @def SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Pos (0U) - -/** - * @def SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Msk (0b00000011U) - - -/* -------------------------------- SWK_CDR_LIMIT_HIGH_CTRL --------------------- */ - - -/** - * @def SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Pos (0U) - -/** - * @def SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Msk (0b11111111U) - - -/* -------------------------------- SWK_CDR_LIMIT_LOW_CTRL ---------------------- */ - - -/** - * @def SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Pos (0U) - -/** - * @def SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Msk (0b11111111U) - - - - - - -/* ================================================================================ */ -/* ============= General Status Registers Position & Mask ================ */ -/* ================================================================================ */ - - - -/* -------------------------------- SUP_STAT_1 ---------------------------------- */ - - -/** - * @def SBC_SUP_STAT_1_VS_UV_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_1_VS_UV_Pos (6U) - -/** - * @def SBC_SUP_STAT_1_VS_UV_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_1_VS_UV_Msk (0b01000000U) - -/** - * @def SBC_SUP_STAT_1_VS_OV_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_1_VS_OV_Pos (5U) - -/** - * @def SBC_SUP_STAT_1_VS_OV_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_1_VS_OV_Msk (0b00100000U) - -/** - * @def SBC_SUP_STAT_1_VCC1_OV_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_1_VCC1_OV_Pos (1U) - -/** - * @def SBC_SUP_STAT_1_VCC1_OV_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_1_VCC1_OV_Msk (0b00000010U) - -/** - * @def SBC_SUP_STAT_1_VCC1_WARN_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_1_VCC1_WARN_Pos (0U) - -/** - * @def SBC_SUP_STAT_1_VCC1_WARN_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_1_VCC1_WARN_Msk (0b00000001U) - - -/* -------------------------------- SUP_STAT_0 ---------------------------------- */ - - -/** - * @def SBC_SUP_STAT_0_POR_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_0_POR_Pos (7U) - -/** - * @def SBC_SUP_STAT_0_POR_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_0_POR_Msk (0b10000000U) - -/** - * @def SBC_SUP_STAT_0_VCC2_OT_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_0_VCC2_OT_Pos (4U) - -/** - * @def SBC_SUP_STAT_0_VCC2_OT_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_0_VCC2_OT_Msk (0b00010000U) - -/** - * @def SBC_SUP_STAT_0_VCC2_UV_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_0_VCC2_UV_Pos (3U) - -/** - * @def SBC_SUP_STAT_0_VCC2_UV_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_0_VCC2_UV_Msk (0b00001000U) - -/** - * @def SBC_SUP_STAT_0_VCC1_SC_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_0_VCC1_SC_Pos (2U) - -/** - * @def SBC_SUP_STAT_0_VCC1_SC_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_0_VCC1_SC_Msk (0b00000100U) - -/** - * @def SBC_SUP_STAT_0_VCC1_UV_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_0_VCC1_UV_Pos (0U) - -/** - * @def SBC_SUP_STAT_0_VCC1_UV_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_0_VCC1_UV_Msk (0b00000001U) - - -/* -------------------------------- THERM_STAT ---------------------------------- */ - - -/** - * @def SBC_THERM_STAT_TSD2_SAFE_Pos - * - * @brief General status register bit position. - */ -#define SBC_THERM_STAT_TSD2_SAFE_Pos (3U) - -/** - * @def SBC_THERM_STAT_TSD2_SAFE_Msk - * - * @brief General status register bit mask. - */ -#define SBC_THERM_STAT_TSD2_SAFE_Msk (0b00001000U) - -/** - * @def SBC_THERM_STAT_TSD2_Pos - * - * @brief General status register bit position. - */ -#define SBC_THERM_STAT_TSD2_Pos (2U) - -/** - * @def SBC_THERM_STAT_TSD2_Msk - * - * @brief General status register bit mask. - */ -#define SBC_THERM_STAT_TSD2_Msk (0b00000100U) - -/** - * @def SBC_THERM_STAT_TSD1_Pos - * - * @brief General status register bit position. - */ -#define SBC_THERM_STAT_TSD1_Pos (1U) - -/** - * @def SBC_THERM_STAT_TSD1_Msk - * - * @brief General status register bit mask. - */ -#define SBC_THERM_STAT_TSD1_Msk (0b00000010U) - -/** - * @def SBC_THERM_STAT_TPW_Pos - * - * @brief General status register bit position. - */ -#define SBC_THERM_STAT_TPW_Pos (0U) - -/** - * @def SBC_THERM_STAT_TPW_Msk - * - * @brief General status register bit mask. - */ -#define SBC_THERM_STAT_TPW_Msk (0b00000001U) - - -/* -------------------------------- DEV_STAT ------------------------------------ */ - - -/** - * @def SBC_DEV_STAT_DEV_STAT_Pos - * - * @brief General status register bit position. - */ -#define SBC_DEV_STAT_DEV_STAT_Pos (6U) - -/** - * @def SBC_DEV_STAT_DEV_STAT_Msk - * - * @brief General status register bit mask. - */ -#define SBC_DEV_STAT_DEV_STAT_Msk (0b11000000U) - -/** - * @def SBC_DEV_STAT_WD_FAIL_Pos - * - * @brief General status register bit position. - */ -#define SBC_DEV_STAT_WD_FAIL_Pos (2U) - -/** - * @def SBC_DEV_STAT_WD_FAIL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_DEV_STAT_WD_FAIL_Msk (0b00001100U) - -/** - * @def SBC_DEV_STAT_SPI_FAIL_Pos - * - * @brief General status register bit position. - */ -#define SBC_DEV_STAT_SPI_FAIL_Pos (1U) - -/** - * @def SBC_DEV_STAT_SPI_FAIL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_DEV_STAT_SPI_FAIL_Msk (0b00000010U) - -/** - * @def SBC_DEV_STAT_FAILURE_Pos - * - * @brief General status register bit position. - */ -#define SBC_DEV_STAT_FAILURE_Pos (0U) - -/** - * @def SBC_DEV_STAT_FAILURE_Msk - * - * @brief General status register bit mask. - */ -#define SBC_DEV_STAT_FAILURE_Msk (0b00000001U) - - -/* -------------------------------- BUS_STAT ------------------------------------ */ - - -/** - * @def SBC_BUS_STAT_CANTO_Pos - * - * @brief General status register bit position. - */ -#define SBC_BUS_STAT_CANTO_Pos (4U) - -/** - * @def SBC_BUS_STAT_CANTO_Msk - * - * @brief General status register bit mask. - */ -#define SBC_BUS_STAT_CANTO_Msk (0b00010000U) - -/** - * @def SBC_BUS_STAT_SYSERR_Pos - * - * @brief General status register bit position. - */ -#define SBC_BUS_STAT_SYSERR_Pos (3U) - -/** - * @def SBC_BUS_STAT_SYSERR_Msk - * - * @brief General status register bit mask. - */ -#define SBC_BUS_STAT_SYSERR_Msk (0b00001000U) - -/** - * @def SBC_BUS_STAT_CAN_FAIL_Pos - * - * @brief General status register bit position. - */ -#define SBC_BUS_STAT_CAN_FAIL_Pos (1U) - -/** - * @def SBC_BUS_STAT_CAN_FAIL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_BUS_STAT_CAN_FAIL_Msk (0b00000110U) - -/** - * @def SBC_BUS_STAT_VCAN_UV_Pos - * - * @brief General status register bit position. - */ -#define SBC_BUS_STAT_VCAN_UV_Pos (0U) - -/** - * @def SBC_BUS_STAT_VCAN_UV_Msk - * - * @brief General status register bit mask. - */ -#define SBC_BUS_STAT_VCAN_UV_Msk (0b00000001U) - - -/* -------------------------------- WK_STAT_0 ----------------------------------- */ - - -/** - * @def SBC_WK_STAT_0_CAN_WU_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_STAT_0_CAN_WU_Pos (5U) - -/** - * @def SBC_WK_STAT_0_CAN_WU_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_STAT_0_CAN_WU_Msk (0b00100000U) - -/** - * @def SBC_WK_STAT_0_TIMER_WU_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_STAT_0_TIMER_WU_Pos (4U) - -/** - * @def SBC_WK_STAT_0_TIMER_WU_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_STAT_0_TIMER_WU_Msk (0b00010000U) - -/** - * @def SBC_WK_STAT_0_WK_WU_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_STAT_0_WK_WU_Pos (0U) - -/** - * @def SBC_WK_STAT_0_WK_WU_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_STAT_0_WK_WU_Msk (0b00000001U) - - -/* -------------------------------- WK_STAT_1 ----------------------------------- */ - - -/** - * @def SBC_WK_STAT_1_GPIO_WK_WU_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_STAT_1_GPIO_WK_WU_Pos (4U) - -/** - * @def SBC_WK_STAT_1_GPIO_WK_WU_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_STAT_1_GPIO_WK_WU_Msk (0b00010000U) - - -/* -------------------------------- WK_LVL_STAT --------------------------------- */ - - -/** - * @def SBC_WK_LVL_STAT_SBC_DEV_LVL_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_LVL_STAT_SBC_DEV_LVL_Pos (7U) - -/** - * @def SBC_WK_LVL_STAT_SBC_DEV_LVL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_LVL_STAT_SBC_DEV_LVL_Msk (0b10000000U) - -/** - * @def SBC_WK_LVL_STAT_CFG0_STATE_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_LVL_STAT_CFG0_STATE_Pos (6U) - -/** - * @def SBC_WK_LVL_STAT_CFG0_STATE_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_LVL_STAT_CFG0_STATE_Msk (0b01000000U) - -/** - * @def SBC_WK_LVL_STAT_GPIO_LVL_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_LVL_STAT_GPIO_LVL_Pos (4U) - -/** - * @def SBC_WK_LVL_STAT_GPIO_LVL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_LVL_STAT_GPIO_LVL_Msk (0b00010000U) - -/** - * @def SBC_WK_LVL_STAT_WK_LVL_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_LVL_STAT_WK_LVL_Pos (0U) - -/** - * @def SBC_WK_LVL_STAT_WK_LVL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_LVL_STAT_WK_LVL_Msk (0b00000001U) - - -/* -------------------------------- GPIO_OC_STAT -------------------------------- */ - - -/** - * @def SBC_GPIO_OC_STAT_GPIO_OC_Pos - * - * @brief General status register bit position. - */ -#define SBC_GPIO_OC_STAT_GPIO_OC_Pos (6U) - -/** - * @def SBC_GPIO_OC_STAT_GPIO_OC_Msk - * - * @brief General status register bit mask. - */ -#define SBC_GPIO_OC_STAT_GPIO_OC_Msk (0b01000000U) - - -/* -------------------------------- GPIO_OL_STAT -------------------------------- */ - - -/** - * @def SBC_GPIO_OL_STAT_GPIO_OL_Pos - * - * @brief General status register bit position. - */ -#define SBC_GPIO_OL_STAT_GPIO_OL_Pos (6U) - -/** - * @def SBC_GPIO_OL_STAT_GPIO_OL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_GPIO_OL_STAT_GPIO_OL_Msk (0b01000000U) - - - - - - - -/* ================================================================================ */ -/* ========= Selective Wake Status Registers Position & Mask ============= */ -/* ================================================================================ */ - - - - -/* -------------------------------- SWK_STAT ------------------------------------ */ - - -/** - * @def SBC_SWK_STAT_SYNC_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_STAT_SYNC_Pos (6U) - -/** - * @def SBC_SWK_STAT_SYNC_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_STAT_SYNC_Msk (0b01000000U) - -/** - * @def SBC_SWK_STAT_CANSIL_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_STAT_CANSIL_Pos (3U) - -/** - * @def SBC_SWK_STAT_CANSIL_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_STAT_CANSIL_Msk (0b00001000U) - -/** - * @def SBC_SWK_STAT_SWK_SET_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_STAT_SWK_SET_Pos (2U) - -/** - * @def SBC_SWK_STAT_SWK_SET_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_STAT_SWK_SET_Msk (0b00000100U) - -/** - * @def SBC_SWK_STAT_WUP_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_STAT_WUP_Pos (1U) - -/** - * @def SBC_SWK_STAT_WUP_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_STAT_WUP_Msk (0b00000010U) - -/** - * @def SBC_SWK_STAT_WUF_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_STAT_WUF_Pos (0U) - -/** - * @def SBC_SWK_STAT_WUF_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_STAT_WUF_Msk (0b00000001U) - - - - - -/* -------------------------------- SWK_ECNT_STAT -------------------------------- */ - - -/** - * @def SBC_SWK_ECNT_STAT_ECNT_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_ECNT_STAT_ECNT_Pos (0U) - -/** - * @def SBC_SWK_ECNT_STAT_ECNT_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_ECNT_STAT_ECNT_Msk (0b00111111U) - - -/* -------------------------------- SWK_CDR_STAT1 -------------------------------- */ - - -/** - * @def SBC_SWK_CDR_STAT1_NAVG_SAT_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_CDR_STAT1_NAVG_SAT_Pos (0U) - -/** - * @def SBC_SWK_CDR_STAT1_NAVG_SAT_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_CDR_STAT1_NAVG_SAT_Msk (0b11111111U) - - -/* -------------------------------- SWK_CDR_STAT2 -------------------------------- */ - - -/** - * @def SBC_SWK_CDR_STAT2_NAVG_SAT_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_CDR_STAT2_NAVG_SAT_Pos (4U) - -/** - * @def SBC_SWK_CDR_STAT2_NAVG_SAT_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_CDR_STAT2_NAVG_SAT_Msk (0b11110000U) - - - - - - -/* ================================================================================ */ -/* ====== Family and Product Information Register Position & Mask ======== */ -/* ================================================================================ */ - - - -/* -------------------------------- FAM_PROD_STAT -------------------------------- */ - - -/** - * @def SBC_FAM_PROD_STAT_FAM_Pos - * - * @brief Family and product register bit position. - */ -#define SBC_FAM_PROD_STAT_FAM_Pos (4U) - -/** - * @def SBC_FAM_PROD_STAT_FAM_Msk - * - * @brief Family and product register bit mask. - */ -#define SBC_FAM_PROD_STAT_FAM_Msk (0b11110000U) - -/** - * @def SBC_FAM_PROD_STAT_PROD_Pos - * - * @brief Family and product register bit position. - */ -#define SBC_FAM_PROD_STAT_PROD_Pos (0U) - -/** - * @def SBC_FAM_PROD_STAT_PROD_Msk - * - * @brief Family and product register bit mask. - */ -#define SBC_FAM_PROD_STAT_PROD_Msk (0b00001111U) - - - - - - -/* ================================================================================ */ -/* =============== General Control Registers Enumerations ================ */ -/* ================================================================================ */ - - - -/* -------------------------------- M_S_CTRL ------------------------------------ */ - -typedef enum -{ - SBC_MODE_NORMAL = 0x00U, - SBC_MODE_SLEEP, - SBC_MODE_STOP, - SBC_MODE_RESET -}; - -typedef enum -{ - SBC_VCC2_OFF = 0x00U, - SBC_VCC2_ON_NORMAL, - SBC_VCC2_ON_NORMAL_STOP, - SBC_VCC2_ON_ALWAYS -}; - -typedef enum -{ - SBC_VCC1_OV_RST_NOACTION = 0x00U, - SBC_VCC1_OV_RST_RESTART_FAILSAFE -}; - -typedef enum -{ - SBC_VCC1_RT_VRT1 = 0x00U, - SBC_VCC1_RT_VRT2, - SBC_VCC1_RT_VRT3, - SBC_VCC1_RT_VRT4 -}; - - -/* -------------------------------- HW_CTRL_0 ----------------------------------- */ - -typedef enum -{ - SBC_SOFT_RESET_RST_TRIGGER_SOFTRST = 0x00U, - SBC_SOFT_RESET_RST_NOTRIGGER_SOFTRST -}; - -typedef enum -{ - SBC_FO_ON_NOT_ACTIVE = 0x00U, - SBC_FO_ON_ACTIVE -}; - -typedef enum -{ - SBC_CP_EN_OFF = 0x00U, - SBC_CP_EN_ON -}; - -typedef enum -{ - SBC_CFG1_RESTART_FAILSAFE_2WDFAIL = 0x00U, - SBC_CFG1_RESTART_FAILSAFE_1WDFAIL -}; - - -/* -------------------------------- WD_CTRL ------------------------------------- */ - -typedef enum -{ - SBC_CHECKSUM_0 = 0x00U, - SBC_CHECKSUM_1 -}; - -typedef enum -{ - SBC_WD_STM_EN_0_ACTIVE_STOPMODE = 0x00U, - SBC_WD_STM_EN_0_NOTACTIVE_STOPMODE -}; - -typedef enum -{ - SBC_WD_WIN_TIMEOUT_WD = 0x00U, - SBC_WD_WIN_WINDOW_WD -}; - -typedef enum -{ - SBC_WD_EN_WK_BUS_NOSTART_AFTER_CANWAKE = 0x00U, - SBC_WD_EN_WK_BUS_START_LONGOPENWINDOW_CANWAKE -}; - -typedef enum -{ - SBC_WD_TIMER_10MS = 0x00U, - SBC_WD_TIMER_20MS, - SBC_WD_TIMER_50MS, - SBC_WD_TIMER_100MS, - SBC_WD_TIMER_200MS, - SBC_WD_TIMER_500MS, - SBC_WD_TIMER_1000MS, - SBC_WD_TIMER_10000MS -}; - - -/* -------------------------------- BUS_CTRL_0 ---------------------------------- */ - -typedef enum -{ - SBC_BUS_CTRL_0_CAN_WAKECAPABLE_NOSWK = 0x01U, - SBC_BUS_CTRL_0_CAN_RECEIVEONLY_NOSWK, - SBC_BUS_CTRL_0_CAN_NORMAL_NOSWK, - SBC_BUS_CTRL_0_CAN_OFF, - SBC_BUS_CTRL_0_CAN_WAKECAPABLE_SWK, - SBC_BUS_CTRL_0_CAN_RECEIVEONLY_SWK, - SBC_BUS_CTRL_0_CAN_NORMAL_SWK -}; - - -/* -------------------------------- WK_CTRL_0 ----------------------------------- */ - -typedef enum -{ - WK_CTRL_0_TIMER_WK_EN_WAKEUP_DISABLED = 0x00U, - WK_CTRL_0_TIMER_WK_EN_WAKESOURCE -}; - -typedef enum -{ - SBC_WD_STM_EN_1_WATCHDOG_STOPMPDE = 0x00U, - SBC_WD_STM_EN_1_NOWATCHDOG_STOPMODE -}; - - -/* -------------------------------- WK_CTRL_1 ----------------------------------- */ - -typedef enum -{ - SBC_INT_GLOBAL_WAKESOURCES_ONLY = 0x00U, - SBC_INT_GLOBAL_ALLINFORMATIONBITS -}; - -typedef enum -{ - SBC_WK_MEAS_WK_AS_WAKEUP = 0x00U, - SBC_WK_MEAS_WK_AS_VOLTAGESENSING -}; - -typedef enum -{ - SBC_WK_EN_WAKEUP_DISABLED = 0x00U, - SBC_WK_EN_WAKEUP_ENABLED -}; - - -/* -------------------------------- WK_PUPD_CTRL -------------------------------- */ - -typedef enum -{ - SBC_GPIO_WK_PUPD_NOPULLING = 0x00U, - SBC_GPIO_WK_PUPD_PULLDOWN, - SBC_GPIO_WK_PUPD_PULLUP, - SBC_GPIO_WK_PUPD_AUTOMATIC_PULLING -}; - -typedef enum -{ - SBC_WK_PUPD_NOPULLING = 0x00U, - SBC_WK_PUPD_PULLDOWN, - SBC_WK_PUPD_PULLUP, - SBC_WK_PUPD_AUTOMATIC_PULLING -}; - - -/* -------------------------------- BUS_CTRL_3 ---------------------------------- */ - -typedef enum -{ - SBC_CAN_FLASH_DISABLED = 0x00U, - SBC_CAN_FLASH_ENABLED -}; - - -/* -------------------------------- TIMER_CTRL ---------------------------------- */ - -typedef enum -{ - SBC_TIMER_ON_TIMEROFF_HSX_LOW = 0x00U, - SBC_TIMER_ON_100US, - SBC_TIMER_ON_300US, - SBC_TIMER_ON_1MS, - SBC_TIMER_ON_10MS, - SBC_TIMER_ON_20MS, - SBC_TIMER_ON_TIMEROFF_HSX_HIGH -}; - -typedef enum -{ - SBC_TIMER_PER_10MS = 0x00U, - SBC_TIMER_PER_20MS, - SBC_TIMER_PER_50MS, - SBC_TIMER_PER_100MS, - SBC_TIMER_PER_200MS, - SBC_TIMER_PER_500MS, - SBC_TIMER_PER_1S, - SBC_TIMER_PER_2S, - SBC_TIMER_PER_5S, - SBC_TIMER_PER_10S, - SBC_TIMER_PER_20S, - SBC_TIMER_PER_50S, - SBC_TIMER_PER_100S, - SBC_TIMER_PER_200S, - SBC_TIMER_PER_500S, - SBC_TIMER_PER_1000S -}; - - -/* -------------------------------- HW_CTRL_1 ----------------------------------- */ - -typedef enum -{ - SBC_RSTN_HYS_DEFAULT = 0x00U, - SBC_RSTN_HYS_HIGHEST_VRT -}; - -typedef enum -{ - SBC_TSD2_DEL_NO_WAIT_RELEASE_EXTENSION = 0x00U, - SBC_TSD2_DEL_64S_AFTER_16_TSD2_EVENTS -}; - -typedef enum -{ - SBC_RSTN_DEL_TRD1 = 0x00U, - SBC_RSTN_DEL_TRD2 -}; - -typedef enum -{ - SBC_CFG_LOCK_0_NOTLOCKED = 0x00U, - SBC_CFG_LOCK_0_LOCKED -}; - - -/* -------------------------------- HW_CTRL_2 ----------------------------------- */ - -typedef enum -{ - SBC_2MHZ_FREQ_1_8_MHZ = 0x00U, - SBC_2MHZ_FREQ_2_0_MHZ, - SBC_2MHZ_FREQ_2_2_MHZ, - SBC_2MHZ_FREQ_2_4_MHZ -}; - -typedef enum -{ - SBC_I_PEAK_TH_LOW = 0x00U, - SBC_I_PEAK_TH_HIGH -}; - -typedef enum -{ - SBC_SS_MOD_FR_DISABLED = 0x00U, - SBC_SS_MOD_FR_15_6KHZ, - SBC_SS_MOD_FR_31_2KHZ, - SBC_SS_MOD_FR_62_5KHZ -}; - -typedef enum -{ - SBC_CFG_LOCK_1_NOTLOCKED = 0x00U, - SBC_CFG_LOCK_1_LOCKED -}; - - -/* -------------------------------- GPIO_CTRL ----------------------------------- */ - -typedef enum -{ - SBC_GPIO_FO = 0x00U, - SBC_GPIO_HSS_TIMER = 0x03U, - SBC_GPIO_OFF, - SBC_GPIO_WAKE_INPUT, - SBC_GPIO_LSS_PWM, - SBC_GPIO_HSS_PWM -}; - - -/* -------------------------------- PWM_CTRL ------------------------------------ */ - -typedef enum -{ - SBC_PWM_DC_0 = 0x00U, - SBC_PWM_DC_10 = 0x19U, - SBC_PWM_DC_20 = 0x51U, - SBC_PWM_DC_30 = 0x4DU, - SBC_PWM_DC_40 = 0x66U, - SBC_PWM_DC_50 = 0x80U, - SBC_PWM_DC_60 = 0x99U, - SBC_PWM_DC_70 = 0xB3U, - SBC_PWM_DC_80 = 0xCCU, - SBC_PWM_DC_90 = 0xE6U, - SBC_PWM_DC_100 = 0xFFU -}; - - -/* -------------------------------- PWM_FREQ_CTRL ------------------------------- */ - -typedef enum -{ - SBC_PWM_FREQ_100HZ = 0x00U, - SBC_PWM_FREQ_200HZ, - SBC_PWM_FREQ_325HZ, - SBC_PWM_FREQ_400HZ -}; - - -/* -------------------------------- HW_CTRL_3 ----------------------------------- */ - -typedef enum -{ - SBC_TSD_THR_DEFAULT = 0x00U, - SBC_TSD_THR_HIGHER -}; - -typedef enum -{ - SBC_ICC1_LIM_ADJ_750MA = 0x00U, - SBC_ICC1_LIM_ADJ_1000MA, - SBC_ICC1_LIM_ADJ_1200MA, - SBC_ICC1_LIM_ADJ_1500MA -}; - - - - - - -/* ================================================================================ */ -/* ========== Selective Wake Control Registers Enumerations ============== */ -/* ================================================================================ */ - - - -/* -------------------------------- SWK_CTRL ------------------------------------ */ - -typedef enum -{ - SBC_OSC_CAL_DISABLED = 0x00U, - SBC_OSC_CAL_ENABLED -}; - -typedef enum -{ - SBC_TRIM_EN_LOCKED = 0x00U, - SBC_TRIM_EN_UNLOCKED = 0x03U -}; - -typedef enum -{ - SBC_CANTO_MASK_NOINT = 0x00U, - SBC_CANTO_MASK_INT_ON_TO -}; - -typedef enum -{ - SBC_CFG_VAL_NOTVALID = 0x00U, - SBC_CFG_VAL_VALID -}; - - -/* -------------------------------- SWK_ID0_CTRL --------------------------------- */ - -typedef enum -{ - SBC_RTR_NORMAL_DATA_FRAME = 0x00U, - SBC_RTR_REMOTE_TRANSMIT_REQUEST -}; - -typedef enum -{ - SBC_IDE_STANDARD = 0x00U, - SBC_IDE_EXTENDED -}; - - -/* -------------------------------- SWK_DLC_CTRL --------------------------------- */ - -typedef enum -{ - SBC_DLC_0BYTES = 0x00U, - SBC_DLC_1BYTES, - SBC_DLC_2BYTES, - SBC_DLC_3BYTES, - SBC_DLC_4BYTES, - SBC_DLC_5BYTES, - SBC_DLC_6BYTES, - SBC_DLC_7BYTES, - SBC_DLC_8BYTES -}; - - -/* -------------------------------- SWK_CAN_FD_CTRL ------------------------------ */ - -typedef enum -{ - SBC_DIS_ERR_CNT_ENABLED = 0x00U, - SBC_DIS_ERR_CNT_DISABLED -}; - -typedef enum -{ - SBC_RX_FILT_BYP_NOTBYPASSED = 0x00U, - SBC_RX_FILT_BYP_BYPASSED -}; - -typedef enum -{ - SBC_FD_FILTER_50NS = 0x00U, - SBC_FD_FILTER_100NS, - SBC_FD_FILTER_150NS, - SBC_FD_FILTER_200NS, - SBC_FD_FILTER_250NS, - SBC_FD_FILTER_300NS, - SBC_FD_FILTER_350NS, - SBC_FD_FILTER_700NS -}; - -typedef enum -{ - SBC_CAN_FD_EN_DISABLED = 0x00U, - SBC_CAN_FD_EN_ENABLED -}; - - -/* -------------------------------- SWK_OPT_CTRL --------------------------------- */ - -typedef enum -{ - SBC_RX_WK_SEL_LOWPOWER = 0x00U, - SBC_RX_WK_SEL_STANDARD -}; - - -/* -------------------------------- SWK_CDR_CTRL1 -------------------------------- */ - -typedef enum -{ - SBC_SEL_FILT_TC8 = 0x00U, - SBC_SEL_FILT_TC16, - SBC_SEL_FILT_TC32, - SBC_SEL_FILT_ADAPT -}; - -typedef enum -{ - SBC_CDR_EN_DISABLED = 0x00U, - SBC_CDR_EN_ENABLED -}; - - -/* -------------------------------- SWK_CDR_CTRL2 -------------------------------- */ - -typedef enum -{ - SBC_SEL_OSC_CLK_80MHZ = 0x00U, - SBC_SEL_OSC_CLK_40MHZ, - SBC_SEL_OSC_CLK_20MHZ, - SBC_SEL_OSC_CLK_10MHZ -}; - - - - - - -/* ================================================================================ */ -/* ========== General Status Information Registers Enumerations ========== */ -/* ================================================================================ */ - - - -/* -------------------------------- SUP_STAT_1 ---------------------------------- */ - -typedef enum -{ - SBC_VS_UV_NOEVENT = 0x00U, - SBC_VS_UV_EVENT -}; - -typedef enum -{ - SBC_VS_OV_NOEVENT = 0x00U, - SBC_VS_OV_EVENT -}; - -typedef enum -{ - SBC_VCC1_OV_NOEVENT = 0x00U, - SBC_VCC1_OV_EVENT -}; - -typedef enum -{ - SBC_VCC1_UV_PREWARN_NOEVENT = 0x00U, - SBC_VCC1_UV_PREWARN_EVENT -}; - - -/* -------------------------------- SUP_STAT_0 ----------------------------------- */ - -typedef enum -{ - SBC_POR_NOEVENT = 0x00U, - SBC_POR_EVENT -}; - -typedef enum -{ - SBC_VCC2_OT_NOEVENT = 0x00U, - SBC_VCC2_OT_EVENT -}; - -typedef enum -{ - SBC_VCC2_UV_NOEVENT = 0x00U, - SBC_VCC2_UV_EVENT -}; - -typedef enum -{ - SBC_VCC1_SC_NOEVENT = 0x00U, - SBC_VCC1_SC_TO_GND_EVENT -}; - -typedef enum -{ - SBC_VCC1_UV_NOEVENT = 0x00U, - SBC_VCC1_UV_EVENT -}; - - -/* -------------------------------- THERM_STAT ----------------------------------- */ - -typedef enum -{ - SBC_TSD2_SAFE_NOSAFESTATE = 0x00U, - SBC_TSD2_SAFE_SAFESTATE_DETECTED -}; - -typedef enum -{ - SBC_TSD2_NOEVENT = 0x00U, - SBC_TSD2_EVENT -}; - -typedef enum -{ - SBC_TSD1_NOEVENT = 0x00U, - SBC_TSD1_EVENT -}; - -typedef enum -{ - SBC_TPW_NOEVENT = 0x00U, - SBC_TPW_EVENT -}; - - -/* -------------------------------- DEV_STAT ------------------------------------- */ - -typedef enum -{ - SBC_DEV_STAT_CLEARED = 0x00U, - SBC_DEV_STAT_RESTART_AFTER_FAIL, - SBC_DEV_STAT_SLEEP_MODE -}; - -typedef enum -{ - SBC_WD_FAIL_NOFAIL = 0x00U, - SBC_WD_FAIL_1FAIL, - SBC_WD_FAIL_2FAIL -}; - -typedef enum -{ - SBC_SPI_FAIL_NOEVENT = 0x00U, - SBC_SPI_FAIL_EVENT -}; - -typedef enum -{ - SBC_FAILURE_NOEVENT = 0x00U, - SBC_FAILURE_EVENT -}; - - -/* -------------------------------- BUS_STAT ------------------------------------- */ - -typedef enum -{ - SBC_CANTO_NORMAL = 0x00U, - SBC_CANTO_TIMEOUT -}; - -typedef enum -{ - SBC_SYSERR_NOEVENT = 0x00U, - SBC_SYSERR_DETECTED -}; - -typedef enum -{ - SBC_CAN_FAIL_NO_FAIL = 0x00U, - SBC_CAN_FAIL_TSD, - SBC_CAN_FAIL_TXD_DOM_TO, - SBC_CAN_FAIL_BUS_DOM_TO -}; - -typedef enum -{ - SBC_VCAN_UV_NOEVENT = 0x00U, - SBC_VCAN_UV_EVENT -}; - - -/* -------------------------------- WK_STAT_0 ------------------------------------ */ - -typedef enum -{ - SBC_CAN_WU_NOEVENT = 0x00U, - SBC_CAN_WU_EVENT -}; - -typedef enum -{ - SBC_TIMER_WU_NOEVENT = 0x00U, - SBC_TIMER_WU_EVENT -}; - -typedef enum -{ - SBC_WK_WU_NOEVENT = 0x00U, - SBC_WK_WU_EVENT -}; - - -/* -------------------------------- WK_STAT_1 ------------------------------------ */ - -typedef enum -{ - SBC_GPIO_WK_WU_NOEVENT = 0x00U, - SBC_GPIO_WK_WU_EVENT -}; - - -/* -------------------------------- WK_LVL_STAT ---------------------------------- */ - -typedef enum -{ - SBC_DEV_LVL_NORMAL = 0x00U, - SBC_DEV_LVL_DEVELOPMENT_MODE -}; - -typedef enum -{ - SBC_CFG0_STATE_CONFIG_2_4 = 0x00U, - SBC_CFG0_STATE_CONFIG_1_3 -}; - -typedef enum -{ - SBC_GPIO_LVL_LOW = 0x00U, - SBC_GPIO_LVL_HIGH -}; - -typedef enum -{ - SBC_WK_LVL_LOW = 0x00U, - SBC_WK_LVL_HIGH -}; - - -/* -------------------------------- GPIO_OC_STAT --------------------------------- */ - -typedef enum -{ - SBC_GPIO_OC_NOEVENT = 0x00U, - SBC_GPIO_OC_EVENT -}; - - -/* -------------------------------- GPIO_OL_STAT --------------------------------- */ - -typedef enum -{ - SBC_GPIO_OL_NOEVENT = 0x00U, - SBC_GPIO_OL_EVENT -}; - - - - - - -/* ================================================================================ */ -/* ============= Selective Wake Status Registers Enumerations ============ */ -/* ================================================================================ */ - - - -/* -------------------------------- SWK_STAT ------------------------------------ */ - -typedef enum -{ - SBC_SYNC_NOT_SYNCHRONOUS = 0x00U, - SBC_SYNC_VALID_FRAME_RECEIVED -}; - -typedef enum -{ - SBC_CANSIL_NOT_EXCEEDED = 0x00U, - SBC_CANSIL_EXCEEDED -}; - -typedef enum -{ - SBC_SWK_SET_SWK_NOT_ACTIVE = 0x00U, - SBC_SWK_SET_SWK_ACTIVE -}; - -typedef enum -{ - SBC_WUP_NO_WUP = 0x00U, - SBC_WUP_DETECTED -}; - -typedef enum -{ - SBC_WUF_NO_WUF = 0x00U, - SBC_WUF_DETECTED -}; - - -/* -------------------------------- SWK_ECNT_STAT ------------------------------ */ - -typedef enum -{ - SBC_ECNT_NOEVENT = 0x00U, - SBC_ECNT_31_FRAME_ERRORS = 0x1FU, - SBC_ECNT_ERROR_OVERFLOW = 0x20U -}; - - -/* ================================================================================ */ -/* ======== Family and Product Information Registers Enumerations ======== */ -/* ================================================================================ */ - - - -/* -------------------------------- FAM_PROD_STAT ------------------------------- */ - -typedef enum -{ - SBC_FAM_DRIVER = 0x01U, - SBC_FAM_DCDC, - SBC_FAM_MIDRANGE, - SBC_FAM_MULTICAN, - SBC_FAM_LITE, - SBC_FAM_MIDRANGEPLUS = 0x07U -}; - -typedef enum -{ - SBC_PROD_TLE9461 = 0x06U, - SBC_PROD_TLE9461V33, - SBC_PROD_TLE9471 = 0x0EU, - SBC_PROD_TLE9471V33 -}; - - -#endif /* TLE94x1_DEFINES_H */ diff --git a/cva_asw_m0118/src/TLE9461/TLE94x1_ISR.h b/cva_asw_m0118/src/TLE9461/TLE94x1_ISR.h deleted file mode 100644 index b40bbbe..0000000 --- a/cva_asw_m0118/src/TLE9461/TLE94x1_ISR.h +++ /dev/null @@ -1,127 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2019, Infineon Technologies AG - * - * - * Distributed under the Boost Software License, Version 1.0. - * - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - *********************************************************************************************************************/ - - -/****************************************************************************************************//** - * @file TLE94x1_ISR.h - * - * @brief Declaration file for ISR-Vectors and ISR related functions - * - * @version V1.0.0 - * @date 15. April 2019 - * @author Markus Noll / markus.noll@infineon.com - * @author Yannek Micha Rixen / Yannek.Rixen@infineon.com - *******************************************************************************************************/ - - - - -#ifndef TLE94x1_ISR_H -#define TLE94x1_ISR_H - - - - - - - -/* ================================================================================ */ -/* ============================ HEADER FILES ================================== */ -/* ================================================================================ */ - -#include "TLE94x1_DEFINES.h" - - - - - - - - -/* ================================================================================ */ -/* ================================ MACROS ==================================== */ -/* ================================================================================ */ - - -/** - * @def SBC_ISR_VECTOR - * - * @brief Vector defining the handling of interrupts. - * - * Vectors of this type have to be registered by the SBC_Register_Callback method. - */ -#define SBC_ISR_VECTOR(REG,MASK,POS,COMPARE) ((((uint32_t)REG) << 24) | (((uint32_t)MASK) << 16) | (((uint32_t)POS) << 8) | ((uint32_t)COMPARE)) - - - - - - -/* ================================================================================ */ -/* ======================= General Interrupt Defines ========================== */ -/* ================================================================================ */ - - - -/* Interrupts based on WK_STAT_0 and WK_STAT_1 register are always available */ -#define SBC_ISR_CAN_WU SBC_ISR_VECTOR(SBC_WK_STAT_0, SBC_WK_STAT_0_CAN_WU_Msk, SBC_WK_STAT_0_CAN_WU_Pos, SBC_CAN_WU_EVENT) -#define SBC_ISR_TIMER_WU SBC_ISR_VECTOR(SBC_WK_STAT_0, SBC_WK_STAT_0_TIMER_WU_Msk, SBC_WK_STAT_0_TIMER_WU_Pos, SBC_TIMER_WU_EVENT) -#define SBC_ISR_WK_WU SBC_ISR_VECTOR(SBC_WK_STAT_0, SBC_WK_STAT_0_WK_WU_Msk, SBC_WK_STAT_0_WK_WU_Pos, SBC_WK_WU_EVENT) -#define SBC_ISR_GPIO_WK_WU SBC_ISR_VECTOR(SBC_WK_STAT_1, SBC_WK_STAT_1_GPIO_WK_WU_Msk, SBC_WK_STAT_1_GPIO_WK_WU_Pos, SBC_GPIO_WK_WU_EVENT) - - -/* Following interrupts only usable if INT_GLOBAL bit is set to '1' */ -#define SBC_ISR_VS_UV SBC_ISR_VECTOR(SBC_SUP_STAT_1, SBC_SUP_STAT_1_VS_UV_Msk, SBC_SUP_STAT_1_VS_UV_Pos, SBC_VS_UV_EVENT) -#define SBC_ISR_VS_OV SBC_ISR_VECTOR(SBC_SUP_STAT_1, SBC_SUP_STAT_1_VS_OV_Msk, SBC_SUP_STAT_1_VS_OV_Pos, SBC_VS_OV_EVENT) -#define SBC_ISR_VCC1_OV SBC_ISR_VECTOR(SBC_SUP_STAT_1, SBC_SUP_STAT_1_VCC1_OV_Msk, SBC_SUP_STAT_1_VCC1_OV_Pos, SBC_VCC1_OV_EVENT) -#define SBC_ISR_VCC1_UV_PREWARN SBC_ISR_VECTOR(SBC_SUP_STAT_1, SBC_SUP_STAT_1_VCC1_WARN_Msk, SBC_SUP_STAT_1_VCC1_WARN_Pos, SBC_VCC1_UV_PREWARN_EVENT) -#define SBC_ISR_VCC2_OT SBC_ISR_VECTOR(SBC_SUP_STAT_0, SBC_SUP_STAT_0_VCC2_OT_Msk, SBC_SUP_STAT_0_VCC2_OT_Pos, SBC_VCC2_OT_EVENT) -#define SBC_ISR_VCC2_UV SBC_ISR_VECTOR(SBC_SUP_STAT_0, SBC_SUP_STAT_0_VCC2_UV_Msk, SBC_SUP_STAT_0_VCC2_UV_Pos, SBC_VCC2_UV_EVENT) -#define SBC_ISR_VCC1_UV SBC_ISR_VECTOR(SBC_SUP_STAT_0, SBC_SUP_STAT_0_VCC1_UV_Msk, SBC_SUP_STAT_0_VCC1_UV_Pos, SBC_VCC1_UV_EVENT) -#define SBC_ISR_TSD2_SAFESTATE SBC_ISR_VECTOR(SBC_THERM_STAT, SBC_THERM_STAT_TSD2_SAFE_Msk, SBC_THERM_STAT_TSD2_SAFE_Pos, SBC_TSD2_SAFE_SAFESTATE_DETECTED) -#define SBC_ISR_TSD1 SBC_ISR_VECTOR(SBC_THERM_STAT, SBC_THERM_STAT_TSD1_Msk, SBC_THERM_STAT_TSD1_Pos, SBC_TSD1_EVENT) -#define SBC_ISR_TPW SBC_ISR_VECTOR(SBC_THERM_STAT, SBC_THERM_STAT_TPW_Msk, SBC_THERM_STAT_TPW_Pos, SBC_TPW_EVENT) -#define SBC_ISR_RESTART_AFTER_FAIL SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_DEV_STAT_Msk, SBC_DEV_STAT_DEV_STAT_Pos, SBC_DEV_STAT_RESTART_AFTER_FAIL) -#define SBC_ISR_FROM_SLEEPMODE SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_DEV_STAT_Msk, SBC_DEV_STAT_DEV_STAT_Pos, SBC_DEV_STAT_SLEEP_MODE) -#define SBC_ISR_WD_FAIL_1 SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_WD_FAIL_Msk, SBC_DEV_STAT_WD_FAIL_Pos, SBC_WD_FAIL_1FAIL) -#define SBC_ISR_WD_FAIL_2 SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_WD_FAIL_Msk, SBC_DEV_STAT_WD_FAIL_Pos, SBC_WD_FAIL_2FAIL) -#define SBC_ISR_FAILURE SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_FAILURE_Msk, SBC_DEV_STAT_FAILURE_Pos, SBC_FAILURE_EVENT) -#define SBC_ISR_CAN_TSD SBC_ISR_VECTOR(SBC_BUS_STAT, SBC_BUS_STAT_CAN_FAIL_Msk, SBC_BUS_STAT_CAN_FAIL_Pos, SBC_CAN_FAIL_TSD) -#define SBC_ISR_CAN_TXD_DOM_TO SBC_ISR_VECTOR(SBC_BUS_STAT, SBC_BUS_STAT_CAN_FAIL_Msk, SBC_BUS_STAT_CAN_FAIL_Pos, SBC_CAN_FAIL_TXD_DOM_TO) -#define SBC_ISR_CAN_BUS_DOM_TO SBC_ISR_VECTOR(SBC_BUS_STAT, SBC_BUS_STAT_CAN_FAIL_Msk, SBC_BUS_STAT_CAN_FAIL_Pos, SBC_CAN_FAIL_BUS_DOM_TO) -#define SBC_ISR_VCAN_UV SBC_ISR_VECTOR(SBC_BUS_STAT, SBC_BUS_STAT_VCAN_UV_Msk, SBC_BUS_STAT_VCAN_UV_Pos, SBC_VCAN_UV_EVENT) -#define SBC_ISR_GPIO_OC SBC_ISR_VECTOR(SBC_GPIO_OC_STAT, SBC_GPIO_OC_STAT_GPIO_OC_Msk, SBC_GPIO_OC_STAT_GPIO_OC_Pos, SBC_GPIO_OC_EVENT) -#define SBC_ISR_GPIO_OL SBC_ISR_VECTOR(SBC_GPIO_OL_STAT, SBC_GPIO_OL_STAT_GPIO_OL_Msk, SBC_GPIO_OL_STAT_GPIO_OL_Pos, SBC_GPIO_OL_EVENT) - - -#endif /*TLE94x1_ISR_H*/ diff --git a/cva_asw_m0118/src/TLE9461/TLE94x1_SPI.c b/cva_asw_m0118/src/TLE9461/TLE94x1_SPI.c deleted file mode 100644 index b90577c..0000000 --- a/cva_asw_m0118/src/TLE9461/TLE94x1_SPI.c +++ /dev/null @@ -1,156 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2019, Infineon Technologies AG - * - * - * Distributed under the Boost Software License, Version 1.0. - * - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - *********************************************************************************************************************/ - - -/****************************************************************************************************//** - * @file TLE94x1_SPI.c - * - * @brief Implementation of all SPI related functions - * - * @version V1.0.0 - * @date 15. April 2019 - * @author Markus Noll / markus.noll@infineon.com - * @author Yannek Micha Rixen / Yannek.Rixen@infineon.com - *******************************************************************************************************/ - - - - -/* ================================================================================ */ -/* ============================ HEADER FILES ================================ */ -/* ================================================================================ */ - -#include "TLE94x1_SPI.h" -#include "mcu.h" - -void SPI_PortInit(void); - - - - -/* ================================================================================ */ -/* ======================= SPI communication functions ====================== */ -/* ================================================================================ */ - - -uint8_t spitxbuf[10],spirxbuf[10]; -extern McuType mcu; -uint8_t SBC_SPI_INIT(void) { - SpiDrv_InitCfgType masterCfg; - - SPI_PortInit(); - - SpiDrv_GetDefaultConfig(&masterCfg); - masterCfg.basicParameters.isMasterNode = true; - masterCfg.basicParameters.baudRate = 1000000ul; - masterCfg.basicParameters.pcsSelection = 1; - //masterCfg.basicParameters.clockPolarity = SPIDRV_CLK_POLARITY_IDLE_IN_HIGH; - masterCfg.basicParameters.clockPhase = SPIDRV_CLK_PHASE_DATA_SAMPLE_ON_TRAILING_EDGE; - - while(ClockDrv_GetFreq(&mcu.clockDrv, CLOCKDRV_SPI0, &masterCfg.basicParameters.busClockFreq) == false) - { - ; - } - SpiDrv_SetConfig(&mcu.spiDrv0, &masterCfg); - - SpiDrv_SetRxFifoWaterMask(&mcu.spiDrv0, 0); - //SpiDrv_SetIsrConfig(&mcu.spiDrv0, SPIDRV_ISR_SRC_RX_DATA, true); - - /* Enable the SPI interrupts */ - return 0; -} - - - -uint16_t SBC_SPI_TRANSFER16(uint8_t Upper, uint8_t Lower) { - uint16_t ret; - //LPSPI_DRV_SetPcs(LPSPICOM1,LPSPI_PCS0,LPSPI_ACTIVE_LOW); - spitxbuf[0] = Upper; - spitxbuf[1] = Lower; - - SpiDrv_MasterSyncTransfer(&mcu.spiDrv0,SPIDRV_FRAME_SIZE_BIT_TYPE_BYTE,2,spitxbuf,spirxbuf); - //LPSPI_DRV_MasterTransferBlocking(LPSPICOM1,spitxbuf,spirxbuf,2,10); - ret = spirxbuf[0]; - ret <<= 8; - ret |= spirxbuf[1]; - //LPSPI_DRV_SetPcs(LPSPICOM1,LPSPI_PCS0,LPSPI_ACTIVE_HIGH); - return ret; -} - - -/********************CVA SPI DRV**********************/ - -void SPI0_Handler(void) -{ - if(SpiDrv_GetStatus(&mcu.spiDrv0, SPIDRV_STATUS_RX_DATA) == true && SpiDrv_GetIsrConfig(&mcu.spiDrv0, SPIDRV_ISR_SRC_RX_DATA) == true) - { - //spi0IrqCnt++; - //uint8_t len = SpiDrv_AsyncReceive(&mcu.spiDrv0, (void *)masterRxBuff, true); - } -} - -void SPI_PortInit(void) -{ - /* SPI CS */ - PinsDrv_SetMuxModeSel(&mcu.ptb, 5, PINSDRV_MUX_ALT3); - /* Strength driver */ - PortReg_SetPcrDrvStr(mcu.ptb.port, 5, 1); - /* fast slew rate */ - PortReg_SetPcrSr(mcu.ptb.port, 5, 1); - - /* SPI CLK */ - PinsDrv_SetMuxModeSel(&mcu.ptb, 2, PINSDRV_MUX_ALT3); - /* Strength driver */ - PortReg_SetPcrDrvStr(mcu.ptb.port, 2, 1); - /* fast slew rate */ - PortReg_SetPcrSr(mcu.ptb.port, 2, 1); - - /* SPI SIN */ - PinsDrv_SetMuxModeSel(&mcu.ptb, 4, PINSDRV_MUX_ALT3); - /* Strength driver */ - PortReg_SetPcrDrvStr(mcu.ptb.port, 4, 1); - /* fast slew rate */ - PortReg_SetPcrSr(mcu.ptb.port, 4, 1); - - /* SPI SOUT */ - PinsDrv_SetMuxModeSel(&mcu.ptb, 3, PINSDRV_MUX_ALT3); - /* Strength driver */ - PortReg_SetPcrDrvStr(mcu.ptb.port, 3, 1); - /* fast slew rate */ - PortReg_SetPcrSr(mcu.ptb.port, 3, 1); -} - -void SPI_TEST_TASK(void) -{ - -} \ No newline at end of file diff --git a/cva_asw_m0118/src/TLE9461/TLE94x1_SPI.h b/cva_asw_m0118/src/TLE9461/TLE94x1_SPI.h deleted file mode 100644 index abf88cc..0000000 --- a/cva_asw_m0118/src/TLE9461/TLE94x1_SPI.h +++ /dev/null @@ -1,95 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2019, Infineon Technologies AG - * - * - * Distributed under the Boost Software License, Version 1.0. - * - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - *********************************************************************************************************************/ - - -/****************************************************************************************************//** - * @file TLE94x1_SPI.h - * - * @brief Declaration file for TLE94x1 SBC family device SPI functions - * - * @version V1.0.0 - * @date 15. April 2019 - * @author Markus Noll / markus.noll@infineon.com - * @author Yannek Micha Rixen / Yannek.Rixen@infineon.com - *******************************************************************************************************/ - - - - -#ifndef TLE94x1_SPI_H -#define TLE94x1_SPI_H - - - - - - -/* ================================================================================ */ -/* ============================ HEADER FILES ================================ */ -/* ================================================================================ */ - -#include - - - -/* ================================================================================ */ -/* ============================= SPI Functions ============================== */ -/* ================================================================================ */ - -/** - * @brief IMPORTANT! THIS METHOD HAS TO BE DEFINED BY THE USER - * - * The function has to initialze the SPI of the uC and will be called once during SBC_Init(). - * In case, the SPI hardware is already initialized by some other code before, it can be left blank. - * - * @retval Method has to return 0 if initialization was successful. - */ -uint8_t SBC_SPI_INIT(void); - -/** - * @brief IMPORTANT! THIS METHOD HAS TO BE DEFINED BY THE USER - * - * The function will be called by the library everytime when a SPI communication is needed. - * The function proceeds a bidirectional 16-bit transfer to/from the SBC . - * As some UCs only supports 8-Bit transfers, the input arguments are split in two 8-bit arguments. - * For further implementation details have a look at datasheet chapter 13.1 or at the Arduino-examples. - * - * @param Upper The first 8 bit to transmit to the SBC. - * @param Lower The second 8 bit to transmit to the SBC. - * @retval The function will return all 16 bits received from the SBC. - * Bit[15:8] are the first 8 bits received (Status-Information-Field). - * Bit[7:0] is the data-field transmitted of the SBC. - */ -uint16_t SBC_SPI_TRANSFER16(uint8_t Upper, uint8_t Lower); - -#endif /* TLE94x1_SPI_H */ diff --git a/cva_asw_m0118/src/appTask.c b/cva_asw_m0118/src/appTask.c index 717d9af..fcb35e4 100644 --- a/cva_asw_m0118/src/appTask.c +++ b/cva_asw_m0118/src/appTask.c @@ -4,7 +4,7 @@ #include "appTask.h" #include "canuser.h" #include "uds_user.h" -#include "TLE94x1.h" +#include "key.h" /******************************************************************************* * the defines ******************************************************************************/ @@ -89,7 +89,7 @@ void appTaskInit(void) { /* UDS init */ Uds_UserInit(&udsObj, &udsParam); - + ClearKeyState(); } void appTask(void) @@ -106,6 +106,7 @@ void appTask(void) gSystick1msEvent--; gSystick1msCnt++; gSysTick1sCnt++; + KeyScan(); CANMsgTask(); if (gSystick1msCnt % 5 == 0) { @@ -113,7 +114,7 @@ void appTask(void) } if (gSystick1msCnt % 50 == 0) { - SBC_WD_Trigger();//喂狗 + //SBC_WD_Trigger();//喂狗 } if (gSystick1msCnt % 1000 == 0) { diff --git a/cva_asw_m0118/src/canuser.c b/cva_asw_m0118/src/canuser.c index 16daf14..118b2eb 100644 --- a/cva_asw_m0118/src/canuser.c +++ b/cva_asw_m0118/src/canuser.c @@ -4,6 +4,7 @@ #include "canuser.h" #include "appTask.h" #include "can_message.h" +#include "key.h" /******************************************************************************* * the defines ******************************************************************************/ @@ -75,6 +76,8 @@ const FlexCanDrv_MsgCfgType msgCfgObj[UDS_MSG_IDX_NUM] = { /******************************************************************************* * the functions ******************************************************************************/ +void TxK86Msg(uint8_t *pdata); + void CAN_ORed_0_31_MB_Handler(void) { @@ -169,11 +172,11 @@ void FlexCanBoot_Init(void) flexCanDrv_DemoObj = &mcu.flexCanDrv; /* set PTC1 MUX as GPIO */ - PinsDrv_SetMuxModeSel(&mcu.ptc, 5, PINSDRV_MUX_AS_GPIO); + PinsDrv_SetMuxModeSel(&mcu.ptc, 9, PINSDRV_MUX_AS_GPIO); /* set PTC1 as GPIO output */ - PinsDrv_SetPinDirection(&mcu.ptc, 5, 1); + PinsDrv_SetPinDirection(&mcu.ptc, 9, 1); /* set PTC1 as high to control CAN transceiver STB */ - PinsDrv_WritePin(&mcu.ptc, 5, 1); + PinsDrv_WritePin(&mcu.ptc, 9, 0); /* set PTE4 as MUX 5 - CAN0.RX */ PinsDrv_SetMuxModeSel(&mcu.ptb, 0, PINSDRV_MUX_ALT5); @@ -243,15 +246,48 @@ void TxTestMsg(uint8_t *pdata) //SEGGER_RTT_printf(0,"test data\n"); } +void TxK86Msg(uint8_t *pdata) +{ + FlexCanBoot_TxMessage(APP_TX_TEST1_MSG_ID, pdata, 8); +} + +void FillK86Msg(uint8_t *pdata) +{ + uint8_t buf[8] = {0}; + buf[0] |= GetKeyState(KEY_HG_F) << 0; + buf[0] |= GetKeyState(KEY_HG_R) << 1; + buf[0] |= GetKeyState(KEY_KB_F) << 2; + buf[0] |= GetKeyState(KEY_KB_R) << 3; + buf[0] |= GetKeyState(KEY_TT_U) << 4; + buf[0] |= GetKeyState(KEY_TT_D) << 5; + buf[0] |= GetKeyState(KEY_ZERO_ON) << 6; + buf[0] |= GetKeyState(KEY_ZERO_OFF) << 7; + memcpy(pdata,buf,8); +} +uint8_t K86MsgBuf[8] = {0}; void CANMsgTask(void)//1ms task { static uint16_t msg_counter=0; FlexCan_FrameStructureType rxMsg; - msg_counter++; - if (msg_counter % 100 == 0) + FillK86Msg(K86MsgBuf); + if ((K86MsgBuf[0] & 0x3F) != 0) { - TxTestMsg(NULL); + if (msg_counter % 100 == 0) + { + TxK86Msg(K86MsgBuf); + } + msg_counter++; } + else + { + msg_counter = 0; + } + if (getKeyPressFlag(KEY_ZERO_ON) || getKeyPressFlag(KEY_ZERO_OFF)) + { + TxK86Msg(K86MsgBuf); + } + + if (msg_counter >= 1000) { diff --git a/cva_asw_m0118/src/canuser.h b/cva_asw_m0118/src/canuser.h index 86307b9..dcacb84 100644 --- a/cva_asw_m0118/src/canuser.h +++ b/cva_asw_m0118/src/canuser.h @@ -14,11 +14,11 @@ ******************************************************************************/ #define CAN_DATA_BUFFER_SIZE (64u) -#define UDS_PHYS_RECV_MSG_ID (0x732) +#define UDS_PHYS_RECV_MSG_ID (0x731) #define UDS_FUNC_RECV_MSG_ID (0x7DF) -#define UDS_PHYS_RESP_MSG_ID (0x7B2) +#define UDS_PHYS_RESP_MSG_ID (0x7B1) -#define APP_TX_TEST1_MSG_ID (0x111) +#define APP_TX_TEST1_MSG_ID (0x201) #define APP_TX_TEST2_MSG_ID (0x222) #define APP_RX_TEST1_MSG_ID (0x444) #define APP_RX_TEST2_MSG_ID (0x555) diff --git a/cva_asw_m0118/src/extern.c b/cva_asw_m0118/src/extern.c index d1a741b..75bfed5 100644 --- a/cva_asw_m0118/src/extern.c +++ b/cva_asw_m0118/src/extern.c @@ -3,7 +3,6 @@ * the includes ******************************************************************************/ #include "extern.h" -#include "TLE94x1.h" #include #include "drivers/reset/reset_drv.h" #include "mcu.h" @@ -50,7 +49,7 @@ __root const app_CfgInfoType app_info = { .sAswHeader = ASW_HEAD_MASK,//0x00010400 .appBuildTime = __TIME__,//0x00010404 .appBuildDate = __DATE__,//0x00010410 - .appSW_VERSION = "SW0101_20241211", + .appSW_VERSION = "SW0101_20250204", }; @@ -94,7 +93,8 @@ void getEcuName(unsigned char *pdata) void extHardwareReset(void) { - SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_RESET, NULL); + //SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_RESET, NULL); + ResetDrv_SoftwareResetModule(&mcu.resetDrv,RESETDRV_SWRESET_SYS); } void extSortwareReset(void) { diff --git a/cva_asw_m0118/src/hwctrl.c b/cva_asw_m0118/src/hwctrl.c index 76fffcd..57acc1c 100644 --- a/cva_asw_m0118/src/hwctrl.c +++ b/cva_asw_m0118/src/hwctrl.c @@ -3,7 +3,7 @@ ******************************************************************************/ #include "hwctrl.h" #include "canuser.h" -#include "TLE94x1.h" + /******************************************************************************* * the defines ******************************************************************************/ @@ -30,7 +30,7 @@ * the functions ******************************************************************************/ static void hw_clock_init(void); - +static void GPIO_init(void); @@ -44,14 +44,11 @@ void hw_init(void) //初始化时钟 hw_clock_init(); - SBC_SPI_INIT(); - - /* get CAN controller default configuration */ FlexCanBoot_Init(); - SBC_Init(); + GPIO_init(); } static void hw_clock_init(void) @@ -74,24 +71,6 @@ static void hw_clock_init(void) ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTD, &clockConfig); ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTE, &clockConfig); - /* Setup the Pll div2 clock */ - clockConfig.gating = true; - clockConfig.source = CLOCKDRV_PLL; - clockConfig.div = 1; - ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PLL_DIV, &clockConfig); - - clockConfig.gating = true; - clockConfig.source = CLOCKDRV_PLL; - clockConfig.div = 2; - ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PLL_DIV, &clockConfig); - - /* Setup the SPI clock */ - clockConfig.gating = true; - clockConfig.source = CLOCKDRV_PLL_DIV; - ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_SPI0, &clockConfig); - - uint32_t tTcr = SpiReg_GetTcr((const SpiRegType *)&mcu.spiDrv0.reg); - SpiDrv_SetPrescaler(&tTcr,0x02); /* Set system tick clock, 1ms event */ ClockDrv_GetFreq(&mcu.clockDrv, CLOCKDRV_SYS, &gCpuClockFrequency); @@ -102,5 +81,54 @@ static void hw_clock_init(void) } +static void GPIO_init(void) +{ + PinsDrv_SetMuxModeSel(&mcu.ptd, 0, PINSDRV_MUX_AS_GPIO); + PinsDrv_SetPinDirection(&mcu.ptd, 0, 0); + PinsDrv_SetMuxModeSel(&mcu.ptd, 1, PINSDRV_MUX_AS_GPIO); + PinsDrv_SetPinDirection(&mcu.ptd, 1, 0); + PinsDrv_SetMuxModeSel(&mcu.ptd, 2, PINSDRV_MUX_AS_GPIO); + PinsDrv_SetPinDirection(&mcu.ptd, 2, 0); + PinsDrv_SetMuxModeSel(&mcu.ptd, 3, PINSDRV_MUX_AS_GPIO); + PinsDrv_SetPinDirection(&mcu.ptd, 3, 0); + PinsDrv_SetMuxModeSel(&mcu.ptd, 5, PINSDRV_MUX_AS_GPIO); + PinsDrv_SetPinDirection(&mcu.ptd, 5, 0); + + PinsDrv_SetMuxModeSel(&mcu.ptc, 1, PINSDRV_MUX_AS_GPIO); + PinsDrv_SetPinDirection(&mcu.ptc, 1, 0); + PinsDrv_SetMuxModeSel(&mcu.ptc, 16, PINSDRV_MUX_AS_GPIO); + PinsDrv_SetPinDirection(&mcu.ptc, 16, 0); + PinsDrv_SetMuxModeSel(&mcu.ptc, 15, PINSDRV_MUX_AS_GPIO); + PinsDrv_SetPinDirection(&mcu.ptc, 15, 0); + + //PinsDrv_SetPortInputDisable(&mcu.ptd,0); +} +uint8_t getKeyIO(KEYID_t keyid) +{ + switch (keyid) + { + case KEY_KB_F: + return PinsDrv_ReadPin(&mcu.ptd, 2) == 0 ? 1:0; + case KEY_KB_R: + return PinsDrv_ReadPin(&mcu.ptd, 3) == 0 ? 1:0; + case KEY_HG_F: + return PinsDrv_ReadPin(&mcu.ptd, 1) == 0 ? 1:0; + case KEY_HG_R: + return PinsDrv_ReadPin(&mcu.ptd, 0) == 0 ? 1:0; + + case KEY_TT_U: + return PinsDrv_ReadPin(&mcu.ptd, 5) == 0 ? 1:0; + case KEY_TT_D: + return PinsDrv_ReadPin(&mcu.ptc, 1) == 0 ? 1:0; + + case KEY_ZERO_ON: + return PinsDrv_ReadPin(&mcu.ptc, 15) == 0 ? 1:0; + case KEY_ZERO_OFF: + return PinsDrv_ReadPin(&mcu.ptc, 16) == 0 ? 1:0; + default: + return 0; + } +} + diff --git a/cva_asw_m0118/src/hwctrl.h b/cva_asw_m0118/src/hwctrl.h index 2ae9450..68c049a 100644 --- a/cva_asw_m0118/src/hwctrl.h +++ b/cva_asw_m0118/src/hwctrl.h @@ -5,7 +5,7 @@ * the includes ******************************************************************************/ #include "mcu.h" - +#include "key.h" /******************************************************************************* * the defines ******************************************************************************/ @@ -14,8 +14,7 @@ /******************************************************************************* * the typedefs ******************************************************************************/ - - + /******************************************************************************* * the globals ******************************************************************************/ @@ -27,7 +26,7 @@ * the functions ******************************************************************************/ void hw_init(void); - +uint8_t getKeyIO(KEYID_t keyid); diff --git a/cva_bootloader_m0118/cva_bootloader_m0118.ewd b/cva_bootloader_m0118/cva_bootloader_m0118.ewd index 31ecfc6..c1bba30 100644 --- a/cva_bootloader_m0118/cva_bootloader_m0118.ewd +++ b/cva_bootloader_m0118/cva_bootloader_m0118.ewd @@ -156,7 +156,7 @@ diff --git a/cva_bootloader_m0118/cva_bootloader_m0118.ewp b/cva_bootloader_m0118/cva_bootloader_m0118.ewp index 71ddaa7..5c13bcc 100644 --- a/cva_bootloader_m0118/cva_bootloader_m0118.ewp +++ b/cva_bootloader_m0118/cva_bootloader_m0118.ewp @@ -362,7 +362,6 @@ $PROJ_DIR$\SDK\platform\devices\CVM011x $PROJ_DIR$\src\private_driver $PROJ_DIR$\src\RTT - $PROJ_DIR$\src\TLE9461 - - TLE9461 - - $PROJ_DIR$\src\TLE9461\SBC_TLE94x1.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1.c - - - $PROJ_DIR$\src\TLE9461\TLE94x1.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1_DEFINES.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1_ISR.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1_SPI.c - - - $PROJ_DIR$\src\TLE9461\TLE94x1_SPI.h - - $PROJ_DIR$\src\main.c diff --git a/cva_bootloader_m0118/cva_bootloader_m0118.ewt b/cva_bootloader_m0118/cva_bootloader_m0118.ewt index 5e33b2f..cc2df69 100644 --- a/cva_bootloader_m0118/cva_bootloader_m0118.ewt +++ b/cva_bootloader_m0118/cva_bootloader_m0118.ewt @@ -3618,30 +3618,6 @@ $PROJ_DIR$\src\RTT\SEGGER_RTT_Syscalls_GCC.c - - TLE9461 - - $PROJ_DIR$\src\TLE9461\SBC_TLE94x1.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1.c - - - $PROJ_DIR$\src\TLE9461\TLE94x1.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1_DEFINES.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1_ISR.h - - - $PROJ_DIR$\src\TLE9461\TLE94x1_SPI.c - - - $PROJ_DIR$\src\TLE9461\TLE94x1_SPI.h - - $PROJ_DIR$\src\main.c diff --git a/cva_bootloader_m0118/settings/cva_bootloader_m0118.dbgdt b/cva_bootloader_m0118/settings/cva_bootloader_m0118.dbgdt index f37c31e..dd6f31d 100644 --- a/cva_bootloader_m0118/settings/cva_bootloader_m0118.dbgdt +++ b/cva_bootloader_m0118/settings/cva_bootloader_m0118.dbgdt @@ -140,7 +140,7 @@ 14 - 32 + 27 1 @@ -150,16 +150,16 @@ 1 1 1 - 830000000E001386000001000000488100000100000010860000090000005F8600000200000020810000010000000C81000013000000568600005C00000055840000180000005E860000010000000E810000050000000B81000001000000118600000500000046810000040000000D81000001000000 + 8D00000011001386000001000000108600000B0000004881000001000000009000000100000020810000010000005F860000020000000C81000013000000568600005C000000558400001800000000810000010000000E810000050000005E860000010000000B810000010000001486000001000000118600000900000046810000070000000D81000001000000 0F000D8400000F84000008840000FFFFFFFF54840000328100001C810000098400005384000000DC000001DC000002DC000003DC000004DC00001C970000 - 3600139700005B020000048400004D0000001097000056020000048100001B0000001581000024000000318400005400000007E100003F000000208100002A0000000F81000022000000009000005800000004E100003D00000007970000960200000C8100001F00000001E100003A0000000D80000018000000159700005A020000098100001D000000068400004F0000001297000055020000038400004C00000017810000260000000F970000540200001481000023000000449200000C0000000081000019000000308400009C0100000E8400009A0100001F810000290000000E810000210000001F9200000900000003E100003C000000179700005F0200002D9200000B00000000E10000390000000B81000067010000149700005D020000D184000008000000058400004E00000041E10000460000001197000059020000028400004B000000058100001C00000016810000250000000E970000530200001084000052000000328400005500000005E100003E00000051840000570000000A8400005000000035E100004500000002E100003B0000000D8100006901000016970000600200002C9200000A000000 + 3600048400004D000000139700005B0200001581000024000000048100001B000000109700005602000007E100003F000000318400005400000004E100003D00000000900000580000000F81000022000000208100002A0000000D8000001800000001E100003A0000000C8100001F0000000797000096020000068400004F000000098100001D000000159700005A0200001781000026000000038400004C000000129700005502000014810000230000000F970000540200000E8400009A010000308400009C0100000081000019000000449200000C00000003E100003C0000001F920000090000000E810000210000001F810000290000000B8100006701000000E10000390000002D9200000B000000179700005F02000041E1000046000000058400004E000000D184000008000000149700005D0200001681000025000000058100001C000000028400004B0000001197000059020000328400005500000010840000520000000E97000053020000518400005700000005E100003E0000000D8100006901000002E100003B00000035E10000450000000A840000500000002C9200000A0000001697000060020000 0 0A0000000A0000006E0000006E000000 - 000000001A030000000600002B030000 + 00000000D3030000AB060000E4030000 4096 0 0 @@ -185,7 +185,7 @@ 34052 00000000170000000601000078010000 - 560400004A000000FC05000000030000 + 010500004A000000A7060000B9030000 16384 0 0 @@ -199,7 +199,7 @@ 34072 00000000170000000601000078010000 - 560400004A000000FC05000000030000 + 010500004A000000A7060000B9030000 4096 0 0 @@ -213,7 +213,7 @@ 34095 00000000170000000601000078010000 - 560400004A000000FC05000000030000 + 010500004A000000A7060000B9030000 4096 0 0 @@ -227,7 +227,7 @@ 34101 00000000170000000601000078010000 - 5204000046000000000600001A030000 + FD04000046000000AB060000D3030000 4096 0 0 @@ -259,7 +259,7 @@ 34102 00000000170000000601000078010000 - 560400004A000000FC05000000030000 + 010500004A000000A7060000B9030000 4096 0 0 @@ -273,7 +273,7 @@ 34103 00000000170000000601000078010000 - 560400004A000000FC05000000030000 + 010500004A000000A7060000B9030000 4096 0 0 @@ -287,7 +287,7 @@ 34104 00000000170000000601000078010000 - 560400004A000000FC05000000030000 + 010500004A000000A7060000B9030000 4096 0 0 @@ -328,7 +328,7 @@ 34054 000000001700000022010000C8000000 - 04000000810200004A04000000030000 + 040000003A030000F5040000B9030000 32768 0 0 @@ -341,7 +341,7 @@ 34062 000000001700000022010000C8000000 - 04000000810200004A04000000030000 + 040000003A030000F5040000B9030000 4096 0 0 @@ -354,7 +354,7 @@ 34066 000000001700000022010000C8000000 - 04000000810200004A04000000030000 + 040000003A030000F5040000B9030000 4096 0 0 @@ -367,7 +367,7 @@ 34067 000000001700000022010000C8000000 - 04000000810200004A04000000030000 + 040000003A030000F5040000B9030000 4096 0 0 @@ -380,7 +380,7 @@ 34068 000000001700000022010000C8000000 - 04000000810200004A04000000030000 + 040000003A030000F5040000B9030000 4096 0 0 @@ -393,7 +393,7 @@ 34087 000000001700000022010000C8000000 - 04000000810200004A04000000030000 + 040000003A030000F5040000B9030000 4096 0 0 @@ -406,7 +406,7 @@ 34090 000000001700000022010000C8000000 - 04000000810200004A04000000030000 + 040000003A030000F5040000B9030000 4096 0 0 @@ -419,7 +419,7 @@ 34100 000000001700000022010000C8000000 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34051 diff --git a/cva_bootloader_m0118/settings/cva_bootloader_m0118.dnx b/cva_bootloader_m0118/settings/cva_bootloader_m0118.dnx index c96e006..c23c473 100644 --- a/cva_bootloader_m0118/settings/cva_bootloader_m0118.dnx +++ b/cva_bootloader_m0118/settings/cva_bootloader_m0118.dnx @@ -20,7 +20,7 @@ 0 - 519825789 + 2065733558 1 @@ -47,24 +47,32 @@ 0 + _ 0 + _ 0 12 0 0x10000 0x0 0x0 + + + 50FF70064965565037131987 + + 0 + 0 _ 0 _ 0 - - - 0 - 0 - + 0 1 0 0 + + 0 + 0 + _ 0 _ "" @@ -73,7 +81,7 @@ 0 - _ 0 "EMUL_CODE" "{$PROJ_DIR$\src\bootloader\bootloader.c}.869.25" 0 0 1 "" 0 "" 0 + _ 0 "EMUL_CODE" "{$PROJ_DIR$\src\bootloader\bootloader.c}.872.25" 0 0 1 "" 0 "" 0 1 diff --git a/cva_bootloader_m0118/settings/cva_bootloader_m0118.wsdt b/cva_bootloader_m0118/settings/cva_bootloader_m0118.wsdt index 22b293a..4be1793 100644 --- a/cva_bootloader_m0118/settings/cva_bootloader_m0118.wsdt +++ b/cva_bootloader_m0118/settings/cva_bootloader_m0118.wsdt @@ -75,7 +75,7 @@ _I0 - 1052 + 1223 20 2 @@ -87,6 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diff --git a/cva_bootloader_m0118/src/TLE9461/SBC_TLE94x1.h b/cva_bootloader_m0118/src/TLE9461/SBC_TLE94x1.h deleted file mode 100644 index 146c2cc..0000000 --- a/cva_bootloader_m0118/src/TLE9461/SBC_TLE94x1.h +++ /dev/null @@ -1,101 +0,0 @@ -/** - * @cond - *********************************************************************************************************************** - * - * Copyright (c) 2018, Infineon Technologies AG - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification,are permitted provided that the - * following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this list of conditions and the following - * disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the - * following disclaimer in the documentation and/or other materials provided with the distribution. - * - * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote - * products derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - **********************************************************************************************************************/ -#ifndef SBC_TLE94X1_H -#define SBC_TLE94X1_H - -/* XML Version 0.0.6 */ -#define SBC_XML_VERSION (00006) - -#define CTRL_BUS_CTRL_0 (0x3) /*decimal 3*/ - -#define CTRL_BUS_CTRL_3 (0x0) /*decimal 0*/ - -#define CTRL_GPIO_CTRL (0x4) /*decimal 4*/ - -#define CTRL_HW_CTRL_0 (0x40) /*decimal 64*/ - -#define CTRL_HW_CTRL_1 (0x0) /*decimal 0*/ - -#define CTRL_HW_CTRL_2 (0x40) /*decimal 64*/ - -#define CTRL_HW_CTRL_3 (0x1) /*decimal 1*/ - -#define CTRL_M_S_CTRL (0x13) /*decimal 19*/ - -#define CTRL_PWM_CTRL (0x0) /*decimal 0*/ - -#define CTRL_PWM_FREQ_CTRL (0x0) /*decimal 0*/ - -#define CTRL_SWK_BTL0_CTRL (0x50) /*decimal 80*/ - -#define CTRL_SWK_CAN_FD_CTRL (0x0) /*decimal 0*/ - -#define CTRL_SWK_CDR_CTRL2 (0x1) /*decimal 1*/ - -#define CTRL_SWK_CDR_LIMIT_HIGH_CTRL (0x54) /*decimal 84*/ - -#define CTRL_SWK_CDR_LIMIT_LOW_CTRL (0x4C) /*decimal 76*/ - -#define CTRL_SWK_DATA_H_CTRL 0x00000000 - -#define CTRL_SWK_DATA_L_CTRL 0x00000000 - -#define CTRL_SWK_DLC_CTRL (0x0) /*decimal 0*/ - -#define CTRL_SWK_ID0_CTRL (0x0) /*decimal 0*/ - -#define CTRL_SWK_IDx_CTRL 0x00000000 - -#define CTRL_SWK_MASK_IDx_CTRL 0x00000000 - -#define CTRL_TIMER_CTRL (0x0) /*decimal 0*/ - -#define CTRL_WD_CTRL (0x15) /*decimal 21*/ - -#define CTRL_WK_CTRL_0 (0x0) /*decimal 0*/ - -#define CTRL_WK_CTRL_1 (0x0) /*decimal 0*/ - -#define CTRL_WK_PUPD_CTRL (0x0) /*decimal 0*/ - -#define LED_Math_extendedID (0x1) /*decimal 1*/ - -#define LED_Math_extendedIDMsk (0x1) /*decimal 1*/ - -#define MATH_Baudrate (0x2) /*decimal 2*/ - -#define MATH_CDR_FrequencyMHz (0x28) /*decimal 40*/ - -#define MATH_DoubleCDRFreq (0x0) /*decimal 0*/ - -#define MATH_EN_PN (0x1) /*decimal 1*/ - -#define MATH_PWM_DC (0.0) - -#endif /* SBC_TLE94X1_H */ diff --git a/cva_bootloader_m0118/src/TLE9461/TLE9461.icwp b/cva_bootloader_m0118/src/TLE9461/TLE9461.icwp deleted file mode 100644 index 5a043c4..0000000 --- a/cva_bootloader_m0118/src/TLE9461/TLE9461.icwp +++ /dev/null @@ -1,233 +0,0 @@ - - - 9e8e9087eecb39921ec31dfccce96b2a2efec664bafe2827aea4ddb51cb86761 - TLE94x1_Lib.xml - V0.0.6 - - - CTRL.HW_CTRL_2[4] - 0 - 0 - - - CTRL.HW_CTRL_1[4] - 0 - 0 - - - CTRL.WK_PUPD_CTRL[7:6] - 0 - 0 - - - CTRL.PWM_FREQ_CTRL[1:0] - 0 - 0 - - - MATH.PWM_DC - 0 - 0.0 - - - CTRL.WK_CTRL_1[7] - 0 - 0 - - - CTRL.HW_CTRL_0[0] - 0 - 0 - - - CTRL.HW_CTRL_0[5] - 0 - 0 - - - CTRL.BUS_CTRL_3[4] - 0 - 0 - - - CTRL.WK_PUPD_CTRL[1:0] - 0 - 0 - - - CTRL.WK_CTRL_0[6] - 0 - 0 - - - CTRL.TIMER_CTRL[3:0] - 0 - 0 - - - CTRL.TIMER_CTRL[6:4] - 0 - 0 - - - CTRL.HW_CTRL_1[5] - 0 - 0 - - - CTRL.HW_CTRL_3[2] - 0 - 0 - - - CTRL.WD_CTRL[5] - 0 - 0 - - - CTRL.HW_CTRL_0[2] - 0 - 0 - - - CTRL.HW_CTRL_2[7:5] - 2 - 2 - - - CTRL.HW_CTRL_2[3:2] - 0 - 0 - - - CTRL.SWK_CAN_FD_CTRL[3:1] - 2 - 0 - - - MATH.Baudrate - 2 - 2 - - - CTRL.SWK_ID0_CTRL[0] - 0 - 0 - - - CTRL.SWK_MASK_IDx_CTRL - 0x00000000 - 0 - - - CTRL.SWK_DLC_CTRL[3:0] - 0 - 0 - - - CTRL.SWK_DATA_H_CTRL - 0x00000000 - 0x00000000 - - - CTRL.SWK_DATA_L_CTRL - 0x00000000 - 0x00000000 - - - CTRL.HW_CTRL_1[3] - 0 - 0 - - - CTRL.HW_CTRL_2[0] - 0 - 0 - - - CTRL.M_S_CTRL[4:3] - 2 - 2 - - - MATH.EN_PN - 1 - 1 - - - CTRL.HW_CTRL_3[1:0] - 1 - 1 - - - CTRL.HW_CTRL_0[6] - 1 - 1 - - - CTRL.SWK_CAN_FD_CTRL[0] - 0 - 0 - - - MATH.DoubleCDRFreq - 0 - 0 - - - CTRL.SWK_IDx_CTRL - 0x00000000 - 0 - - - CTRL.GPIO_CTRL[2:0] - 4 - 4 - - - CTRL.WK_CTRL_1[0] - 0 - 0 - - - CTRL.WK_CTRL_1[5] - 0 - 0 - - - CTRL.WK_CTRL_0[2];CTRL.WD_CTRL[6] - 1 - 1 - - - CTRL.WD_CTRL[4] - 1 - 1 - - - CTRL.WD_CTRL[2:0] - 5 - 5 - - - CTRL.M_S_CTRL[1:0] - 3 - 3 - - - CTRL.HW_CTRL_1[7] - 0 - 0 - - - CTRL.M_S_CTRL[2] - 0 - 0 - - - CTRL.BUS_CTRL_0[2:0] - 3 - 3 - - - \ No newline at end of file diff --git a/cva_bootloader_m0118/src/TLE9461/TLE94x1.c b/cva_bootloader_m0118/src/TLE9461/TLE94x1.c deleted file mode 100644 index 73428d2..0000000 --- a/cva_bootloader_m0118/src/TLE9461/TLE94x1.c +++ /dev/null @@ -1,591 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2019, Infineon Technologies AG - * - * - * Distributed under the Boost Software License, Version 1.0. - * - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - *********************************************************************************************************************/ - - -/****************************************************************************************************//** - * @file TLE94x1.c - * - * @brief Implementation of main library functions - * - * @version V1.0.1 - * @date 05. October 2020 - * @author Markus Noll / markus.noll@infineon.com - * @author Yannek Micha Rixen / Yannek.Rixen@infineon.com - ********************************************************************************************************/ - - - -/* ================================================================================ */ -/* ============================ HEADER FILES ================================ */ -/* ================================================================================ */ - -#include "TLE94x1.h" -#include "SBC_TLE94x1.h" -#include - - -/* ================================================================================ */ -/* ============================== Variables ================================= */ -/* ================================================================================ */ - - -/* -------------------------------- ISR Handling --------------------------------- */ - -static SBC_Func_Callback SBC_ISR_Callbacks[30]; -static uint32_t SBC_ISR_Vectors[30]; -static uint8_t SBC_ISR_ReadOutRegs[30]; -static uint8_t SBC_ISR_ReadOutVals[30]; -static uint8_t SBC_RegisteredCallbacks = 0; -static uint8_t SBC_RegisteredRedoutRegs = 0; - - - -/* ================================================================================ */ -/* =========================== Library Functions ============================ */ -/* ================================================================================ */ - - -/* -------------------------------- Main Functions ------------------------------- */ - - -SBC_ErrorCode SBC_WD_Trigger(void) { - /* Read WD config out of SBC and write back to trigger WD */ - uint8_t WD_Data = (uint8_t)SBC_Read_Command(SBC_WD_CTRL); - return SBC_Write_Reg(SBC_WD_CTRL, WD_Data, NULL); -} - - -uint16_t SBC_Read_Command(uint8_t SBC_Reg) { - /* Read and return data - Bit[15:8] = Status Information Field - Bit [7:0] Register data */ - return SBC_SPI_TRANSFER16(SBC_Read_Mask & SBC_Reg, 0x00U); -} - - -uint8_t SBC_Read_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos) { - uint8_t data = ((uint8_t)SBC_Read_Command(SBC_Reg)) & 0xFFU; - return (data & SBC_FieldMsk) >> SBC_FieldPos; -} - - -SBC_ErrorCode SBC_Write_Reg(uint8_t SBC_Reg, uint8_t SBC_Val, uint16_t * returnval) { - SBC_ErrorCode errCode; - uint16_t returndata = SBC_SPI_TRANSFER16(SBC_Write_Bit | SBC_Reg, SBC_Val); - if(returnval != NULL) { - *returnval = returndata; - } - - errCode.SBC_Register = SBC_Reg; - errCode.flippedBitsMask = ((uint8_t)SBC_Read_Command(SBC_Reg)) ^ SBC_Val; - errCode.expectedValue = SBC_Val; - return errCode; -} - - -SBC_ErrorCode SBC_Write_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos, uint8_t SBC_FieldVal, uint16_t * returnval) { - SBC_ErrorCode errCode; - - /* Read data out of register to be manipulated */ - uint16_t returndata = SBC_Read_Command(SBC_Reg); - if(returnval != NULL) { - *returnval = returndata; - } - uint8_t data = (uint8_t)returndata; - - /* Set the used bit field to all 0 */ - data &= ~(SBC_FieldMsk); - - /* Configure new data to bit field */ - data |= (SBC_FieldVal << SBC_FieldPos); - - (void)SBC_SPI_TRANSFER16(SBC_Write_Bit | SBC_Reg, data); - - errCode.SBC_Register = SBC_Reg; - errCode.expectedValue = (SBC_FieldVal << SBC_FieldPos); - uint8_t actualValue = ((uint8_t)SBC_Read_Command(SBC_Reg)) & SBC_FieldMsk; - errCode.flippedBitsMask = errCode.expectedValue ^ actualValue; - return errCode; -} - - -SBC_ErrorCode SBC_Init(void) { - SBC_ErrorCode errCode; - uint8_t WD_Checksum = CTRL_WD_CTRL; - uint8_t WD_CTRL = CTRL_WD_CTRL; - uint8_t SWK_ID3_CTRL, SWK_ID2_CTRL, SWK_ID1_CTRL, SWK_ID0_CTRL; - uint8_t SWK_MASK_ID3_CTRL, SWK_MASK_ID2_CTRL, SWK_MASK_ID1_CTRL, SWK_MASK_ID0_CTRL; - uint8_t SWK_CAN_FD_CTRL = CTRL_SWK_CAN_FD_CTRL; - - /* Calculate checksum */ - WD_Checksum = WD_Checksum ^ WD_Checksum >> 4; - WD_Checksum = WD_Checksum ^ WD_Checksum >> 2; - WD_Checksum = WD_Checksum ^ WD_Checksum >> 1; - - if((WD_Checksum & 1) > 0) { - /* Set parity bit */ - WD_CTRL = CTRL_WD_CTRL | 0x80U; - } - - /* Check if ID is configured to be extended */ - if((CTRL_SWK_ID0_CTRL & SBC_SWK_ID0_CTRL_IDE_Msk) == SBC_IDE_EXTENDED) { - /* extended ID */ - uint32_t SWK_ID_CTRL = CTRL_SWK_IDx_CTRL << 3; - uint32_t SWK_MASK_ID_CTRL = CTRL_SWK_MASK_IDx_CTRL << 3; - - SWK_ID3_CTRL = (uint8_t)(SWK_ID_CTRL >> 24); - SWK_ID2_CTRL = (uint8_t)(SWK_ID_CTRL >> 16); - SWK_ID1_CTRL = (uint8_t)(SWK_ID_CTRL >> 8); - SWK_ID0_CTRL = (((uint8_t)(SWK_ID_CTRL >> 1)) & SBC_SWK_ID0_CTRL_ID4_0_Msk) | SBC_IDE_EXTENDED; - SWK_MASK_ID3_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 24); - SWK_MASK_ID2_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 16); - SWK_MASK_ID1_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 8); - SWK_MASK_ID0_CTRL = (((uint8_t)(SWK_MASK_ID_CTRL >> 1)) & SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk); - } else { - /* Standard length ID */ - uint16_t SWK_ID_CTRL = CTRL_SWK_IDx_CTRL; - uint32_t SWK_MASK_ID_CTRL = CTRL_SWK_MASK_IDx_CTRL; - - SWK_ID3_CTRL = (uint8_t)(SWK_ID_CTRL >> 3); - SWK_ID2_CTRL = (uint8_t)(SWK_ID_CTRL << 5); - SWK_ID1_CTRL = 0x00U; - SWK_ID0_CTRL = 0x00U; - SWK_MASK_ID3_CTRL = (uint8_t)(SWK_MASK_ID_CTRL >> 3); - SWK_MASK_ID2_CTRL = (uint8_t)(SWK_MASK_ID_CTRL << 5); - SWK_MASK_ID1_CTRL = 0x00U; - SWK_MASK_ID0_CTRL = 0x00U; - } - - /* DIS_ERR_CNT is set only when FD Tolerance is set. */ - if((CTRL_SWK_CAN_FD_CTRL & SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk) == SBC_CAN_FD_EN_ENABLED) { - SWK_CAN_FD_CTRL &= SBC_DIS_ERR_CNT_DISABLED << SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos; - } - - /* Describes initialization sequence */ - uint8_t initSequence[39][2] = { - {SBC_WD_CTRL, WD_CTRL}, - {SBC_M_S_CTRL, CTRL_M_S_CTRL}, - {SBC_HW_CTRL_0, CTRL_HW_CTRL_0}, - {SBC_HW_CTRL_3, CTRL_HW_CTRL_3}, - {SBC_BUS_CTRL_3, CTRL_BUS_CTRL_3}, - {SBC_WK_CTRL_0, CTRL_WK_CTRL_0}, - {SBC_WK_CTRL_1, CTRL_WK_CTRL_1}, - {SBC_WK_PUPD_CTRL, CTRL_WK_PUPD_CTRL}, - {SBC_TIMER_CTRL, CTRL_TIMER_CTRL}, - {SBC_PWM_FREQ_CTRL, CTRL_PWM_FREQ_CTRL}, /* The desired duty cycle should be set first before GPIO is enabled as PWM HS or PWM LS. */ - {SBC_PWM_CTRL, CTRL_PWM_CTRL}, - {SBC_GPIO_CTRL, CTRL_GPIO_CTRL}, - {SBC_HW_CTRL_1, CTRL_HW_CTRL_1}, /* May lock configuration (CFG_LOCK_0) */ - {SBC_HW_CTRL_2, CTRL_HW_CTRL_2}, /* May lock configuration (CFG_LOCK_1) */ - {SBC_BUS_CTRL_0, CTRL_BUS_CTRL_0}, - - /* -------------------------- SELECTIVE WAKE REGISTERS --------------------------- */ - - /* Configuring CDR */ - {SBC_SWK_CDR_CTRL2, CTRL_SWK_CDR_CTRL2}, - {SBC_SWK_BTL0_CTRL, CTRL_SWK_BTL0_CTRL}, - {SBC_SWK_CDR_LIMIT_HIGH_CTRL, CTRL_SWK_CDR_LIMIT_HIGH_CTRL}, - {SBC_SWK_CDR_LIMIT_LOW_CTRL, CTRL_SWK_CDR_LIMIT_LOW_CTRL}, - {SBC_SWK_CDR_CTRL1, (SBC_SEL_FILT_TC16 << SBC_SWK_CDR_CTRL1_SEL_FILT_Pos) | (SBC_CDR_EN_ENABLED << SBC_SWK_CDR_CTRL1_CDR_EN_Pos)}, - - - /* Set ID */ - {SBC_SWK_ID3_CTRL, SWK_ID3_CTRL}, - {SBC_SWK_ID2_CTRL, SWK_ID2_CTRL}, - {SBC_SWK_ID1_CTRL, SWK_ID1_CTRL}, - {SBC_SWK_ID0_CTRL, SWK_ID0_CTRL}, - - /* Set Mask */ - {SBC_SWK_MASK_ID3_CTRL, SWK_MASK_ID3_CTRL}, - {SBC_SWK_MASK_ID2_CTRL, SWK_MASK_ID2_CTRL}, - {SBC_SWK_MASK_ID1_CTRL, SWK_MASK_ID1_CTRL}, - {SBC_SWK_MASK_ID0_CTRL, SWK_MASK_ID0_CTRL}, - - /* Set Data */ - {SBC_SWK_DATA7_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 24)}, - {SBC_SWK_DATA6_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 16)}, - {SBC_SWK_DATA5_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 8)}, - {SBC_SWK_DATA4_CTRL, (uint8_t)(CTRL_SWK_DATA_H_CTRL >> 0)}, - {SBC_SWK_DATA3_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 24)}, - {SBC_SWK_DATA2_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 16)}, - {SBC_SWK_DATA1_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 8)}, - {SBC_SWK_DATA0_CTRL, (uint8_t)(CTRL_SWK_DATA_L_CTRL >> 0)}, - - /* Set DLC */ - {SBC_SWK_DLC_CTRL, CTRL_SWK_DLC_CTRL}, - - {SBC_SWK_CAN_FD_CTRL, SWK_CAN_FD_CTRL}, - - /* End Configuration */ - {0x00U, 0x00U} - }; - - /* Call SPI Init */ - if(SBC_SPI_INIT() != 0) { - errCode.SBC_Register = 0x00; - errCode.flippedBitsMask = 0xFF; - errCode.expectedValue = 0x00; - return errCode; - }; - - uint8_t i = 0; - - /* Write all initialization items to Lite SBC */ - while(initSequence[i][0] != 0x00U || initSequence[i][1] != 0x00U) { - errCode = SBC_Write_Reg(initSequence[i][0], initSequence[i][1], NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - i++; - } - - errCode.SBC_Register = 0x00; - errCode.flippedBitsMask = 0x00; - errCode.expectedValue = 0x00; - return errCode; -} - - - -/* -------------------------------- ISR Functions -------------------------------- */ - - -void SBC_Register_Callback(uint32_t ISR_Vector, void (*Callback_Handler)(uint8_t callbackHandler)) { - /* Save callback */ - SBC_ISR_Callbacks[SBC_RegisteredCallbacks] = Callback_Handler; - - /* Save callback vector */ - SBC_ISR_Vectors[SBC_RegisteredCallbacks] = ISR_Vector; - - /* Check if the register will be readout already to avoid double-readout later */ - uint8_t RegFound = 0; - for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) { - if (SBC_ISR_ReadOutRegs[i] == (ISR_Vector >> 24)) { - RegFound = 1; - } - } - - /* If readout status-reg was not found, register in the readout list */ - if (RegFound == 0) { - SBC_ISR_ReadOutRegs[SBC_RegisteredRedoutRegs] = (uint8_t)(ISR_Vector >> 24); - SBC_RegisteredRedoutRegs++; - } - - SBC_RegisteredCallbacks++; -} - - -SBC_ErrorCode SBC_ISR(void) { - SBC_ErrorCode errCode; - - /* Readout all registered status-registers */ - for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) { - SBC_ISR_ReadOutVals[i] = (uint8_t) SBC_Read_Command(SBC_ISR_ReadOutRegs[i]); - } - - /* Handle all interrupts */ - for (uint8_t i = 0; i < SBC_RegisteredCallbacks; i++) { - /* Decode ISR Vector */ - uint8_t Compare = (uint8_t)SBC_ISR_Vectors[i]; - uint8_t FieldPos = (uint8_t)(SBC_ISR_Vectors[i] >> 8); - uint8_t FieldMsk = (uint8_t)(SBC_ISR_Vectors[i] >> 16); - uint8_t RegAddr = (uint8_t)(SBC_ISR_Vectors[i] >> 24); - - /* Readback of associated status-bit */ - uint8_t ReadBack = 0; - for (uint8_t j = 0; j < SBC_RegisteredRedoutRegs; j++) { - if (SBC_ISR_ReadOutRegs[j] == RegAddr) { - ReadBack = SBC_ISR_ReadOutVals[j]; - break; - } - } - - /* If compare-values matched -> proceed callback and clear field */ - if (((ReadBack & FieldMsk) >> FieldPos) == Compare) { - SBC_ISR_Callbacks[i](ReadBack); - } - } - - /* Clear all ISR related registers */ - for (uint8_t i = 0; i < SBC_RegisteredRedoutRegs; i++) { - errCode = SBC_Write_Reg(SBC_ISR_ReadOutRegs[i], 0x00U, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - } - - errCode.SBC_Register = 0x00U; - errCode.flippedBitsMask = 0x00U; - errCode.expectedValue = 0x00U; - return errCode; -} - - - -/* -------------------------------- API Calls ----------------------------------- */ - -SBC_ErrorCode SBC_Mode_Normal(void) { - return SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_NORMAL, NULL); -} - - -SBC_ErrorCode SBC_Mode_Stop(void) { - return SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_STOP, NULL); -} - - -SBC_ErrorCode SBC_Mode_Sleep(void) { - uint8_t registerReadOut; - - SBC_ErrorCode errCode; - - /* If CAN PN is configured */ - if(MATH_EN_PN != 0) { - - /* Reading value of SWK_STAT. */ - registerReadOut = (uint8_t)SBC_Read_Command(SBC_SWK_STAT); - - /* CAN Protocol Handler in sync? The selective wake routine should be aborted if sync is not set. Note: for SYNC to be set the transceiver must have been in Normal Mode and a valid CAN communication must have been sent on the bus by any node. */ - if((registerReadOut & SBC_SWK_STAT_SYNC_Msk) >> SBC_SWK_STAT_SYNC_Pos != SBC_SYNC_VALID_FRAME_RECEIVED) { - errCode.SBC_Register = SBC_SWK_STAT; - errCode.flippedBitsMask = SBC_SWK_STAT_SYNC_Msk; - errCode.expectedValue = SBC_SYNC_VALID_FRAME_RECEIVED << SBC_SWK_STAT_SYNC_Pos; - return errCode; - } - - /* Set SWK Configuration valid */ - errCode = SBC_Write_RegField(SBC_SWK_CTRL, SBC_SWK_CTRL_CFG_VAL_Msk, SBC_SWK_CTRL_CFG_VAL_Pos, SBC_CFG_VAL_VALID, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - - /* Clear SYSERR bit */ - errCode = SBC_Write_RegField(SBC_BUS_STAT, SBC_BUS_STAT_SYSERR_Msk, SBC_BUS_STAT_SYSERR_Pos, 0x00, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - /* Set CAN Mode to off and once again to desired configuration */ - errCode = SBC_Write_Reg(SBC_BUS_CTRL_0, 0x03, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - errCode = SBC_Write_Reg(SBC_BUS_CTRL_0, CTRL_BUS_CTRL_0, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - /* Check SWK_STAT for SYNC == 1 && SWK_SET == 1 && WUF == 0 && WUP == 0. Ignore CANSIL */ - registerReadOut = (uint8_t)SBC_Read_Command(SBC_SWK_STAT); - if( ((SBC_SWK_STAT_SYNC_Msk & registerReadOut) == SBC_SWK_STAT_SYNC_Msk) - && ((SBC_SWK_STAT_SWK_SET_Msk & registerReadOut) == SBC_SWK_STAT_SWK_SET_Msk) - && ((SBC_SWK_STAT_WUP_Msk & registerReadOut) != SBC_SWK_STAT_WUP_Msk) - && ((SBC_SWK_STAT_WUF_Msk & registerReadOut) != SBC_SWK_STAT_WUF_Msk)) { - /* Empty */ - } else { - errCode.SBC_Register = SBC_SWK_STAT; - errCode.expectedValue = 0b01000100U; - errCode.flippedBitsMask = errCode.expectedValue ^ registerReadOut; - return errCode; - } - - - - } - - - - /* Clear Wake Status Registers, so that SBC can sleep. */ - errCode = SBC_Write_Reg(SBC_WK_STAT_0, 0x00, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - errCode = SBC_Write_Reg(SBC_WK_STAT_1, 0x00, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - /* Select sleep mode */ - (void)SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_SLEEP, NULL); - registerReadOut = (uint8_t)SBC_Read_Command(SBC_M_S_CTRL); - - /* This piece of code is ideally never reached as the microcontroller should be already turned off then */ - if(registerReadOut != 0) { - errCode.SBC_Register = SBC_M_S_CTRL; - errCode.flippedBitsMask = registerReadOut; - errCode.expectedValue = 0x00U; - return errCode; - } - - errCode.SBC_Register = 0x00U; - errCode.flippedBitsMask = 0x00U; - errCode.expectedValue = 0x00U; - return errCode; -} - - -SBC_ErrorCode SBC_Set_DutyCycle_PWM (uint8_t PWM_DC) { - return SBC_Write_Reg(SBC_PWM_CTRL, PWM_DC, NULL); -} - - -SBC_ErrorCode SBC_Set_Timer_On (uint8_t OnTime) { - return SBC_Write_RegField(SBC_TIMER_CTRL, SBC_TIMER_CTRL_TIMER_ON_Msk, SBC_TIMER_CTRL_TIMER_ON_Pos, OnTime, NULL); -} - - -SBC_ErrorCode SBC_Set_Timer_Period (uint8_t Period) { - return SBC_Write_RegField(SBC_TIMER_CTRL, SBC_TIMER_CTRL_TIMER_PER_Msk, SBC_TIMER_CTRL_TIMER_PER_Pos, Period, NULL); -} - - -SBC_ErrorCode SBC_FO_Test_On(void) { - return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_FO_ON_Msk, SBC_HW_CTRL_0_FO_ON_Pos, SBC_FO_ON_ACTIVE, NULL); -} - - -SBC_ErrorCode SBC_FO_Test_Off(void) { - return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_FO_ON_Msk, SBC_HW_CTRL_0_FO_ON_Pos, SBC_FO_ON_NOT_ACTIVE, NULL); -} - - -SBC_ErrorCode SBC_CP_On(void) { - return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_CP_EN_Msk, SBC_HW_CTRL_0_CP_EN_Pos, SBC_CP_EN_ON, NULL); -} - - -SBC_ErrorCode SBC_CP_Off(void) { - return SBC_Write_RegField(SBC_HW_CTRL_0, SBC_HW_CTRL_0_CP_EN_Msk, SBC_HW_CTRL_0_CP_EN_Pos, SBC_CP_EN_OFF, NULL); -} - - -SBC_ErrorCode SBC_WK_MEAS_On(void) { - return SBC_Write_RegField(SBC_WK_CTRL_1, SBC_WK_CTRL_1_WK_MEAS_Msk, SBC_WK_CTRL_1_WK_MEAS_Pos, SBC_WK_MEAS_WK_AS_VOLTAGESENSING, NULL); -} - - -SBC_ErrorCode SBC_WK_MEAS_Off(void) { - return SBC_Write_RegField(SBC_WK_CTRL_1, SBC_WK_CTRL_1_WK_MEAS_Msk, SBC_WK_CTRL_1_WK_MEAS_Pos, SBC_WK_MEAS_WK_AS_WAKEUP, NULL); -} - - -SBC_ErrorCode SBC_TIMER_WK_EN_On(void) { - return SBC_Write_RegField(SBC_WK_CTRL_0, SBC_WK_CTRL_0_TIMER_WK_EN_Msk, SBC_WK_CTRL_0_TIMER_WK_EN_Pos, WK_CTRL_0_TIMER_WK_EN_WAKESOURCE, NULL); -} - - -SBC_ErrorCode SBC_TIMER_WK_EN_Off(void) { - return SBC_Write_RegField(SBC_WK_CTRL_0, SBC_WK_CTRL_0_TIMER_WK_EN_Msk, SBC_WK_CTRL_0_TIMER_WK_EN_Pos, WK_CTRL_0_TIMER_WK_EN_WAKEUP_DISABLED, NULL); -} - - -uint16_t SBC_SYS_STAT_Read(void) { - uint16_t systemStatus = 0; - uint16_t returndata = SBC_Read_Command(SBC_SYS_STATUS_CTRL_0); - systemStatus = returndata & 0x00FFU; - systemStatus |= SBC_Read_Command(SBC_SYS_STATUS_CTRL_1) << 8; - return systemStatus; -} - - -SBC_ErrorCode SBC_SYS_STAT_Write(uint16_t SystemStatus) { - SBC_ErrorCode errCode; - - /* Write lower bits */ - errCode = SBC_Write_Reg(SBC_SYS_STATUS_CTRL_0, (uint8_t)SystemStatus, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - /* Write higher bits */ - return SBC_Write_Reg(SBC_SYS_STATUS_CTRL_1, (uint8_t)(SystemStatus >> 8), NULL); -} - - -SBC_ErrorCode SBC_Lock_Configuration(void) { - SBC_ErrorCode errCode; - - /* Lock CP_EN and GPIO cannot be modified */ - errCode = SBC_Write_RegField(SBC_HW_CTRL_1, SBC_HW_CTRL_1_CFG_LOCK_0_Msk, SBC_HW_CTRL_1_CFG_LOCK_0_Pos, SBC_CFG_LOCK_0_LOCKED, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - /* Lock Bits with bit type ‘rwl’ (except CP_EN and GPIO) until next device power-up. */ - errCode = SBC_Write_RegField(SBC_HW_CTRL_2, SBC_HW_CTRL_2_CFG_LOCK_1_Msk, SBC_HW_CTRL_2_CFG_LOCK_1_Pos, SBC_CFG_LOCK_1_LOCKED, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - errCode.SBC_Register = 0x00; - errCode.flippedBitsMask = 0x00; - errCode.expectedValue = 0x00; - return errCode; -} - - -SBC_ErrorCode SBC_Unlock_Configuration(void) { - SBC_ErrorCode errCode; - - /* Unlock CP_EN and GPIO configuration. */ - errCode = SBC_Write_RegField(SBC_HW_CTRL_1, SBC_HW_CTRL_1_CFG_LOCK_0_Msk, SBC_HW_CTRL_1_CFG_LOCK_0_Pos, SBC_CFG_LOCK_0_NOTLOCKED, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - /* Unlock Bits with bit type ‘rwl’ (except CP_EN and GPIO). */ - errCode = SBC_Write_RegField(SBC_HW_CTRL_2, SBC_HW_CTRL_2_CFG_LOCK_1_Msk, SBC_HW_CTRL_2_CFG_LOCK_1_Pos, SBC_CFG_LOCK_1_NOTLOCKED, NULL); - if(errCode.flippedBitsMask > 0) { - return errCode; - } - - errCode.SBC_Register = 0x00; - errCode.flippedBitsMask = 0x00; - errCode.expectedValue = 0x00; - return errCode; -} - -SBC_ErrorCode SBC_Clear_Wake_Status(void) { - SBC_ErrorCode errCode = SBC_Write_Reg(SBC_WK_STAT_0, 0x00, NULL); - if(errCode.flippedBitsMask != 0) { - return errCode; - } - errCode = SBC_Write_Reg(SBC_WK_STAT_1, 0x00, NULL); - if(errCode.flippedBitsMask != 0) { - return errCode; - } - errCode.SBC_Register = 0x00; - errCode.flippedBitsMask = 0x00; - errCode.expectedValue = 0x00; - return errCode; -} diff --git a/cva_bootloader_m0118/src/TLE9461/TLE94x1.h b/cva_bootloader_m0118/src/TLE9461/TLE94x1.h deleted file mode 100644 index a434389..0000000 --- a/cva_bootloader_m0118/src/TLE9461/TLE94x1.h +++ /dev/null @@ -1,393 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2019, Infineon Technologies AG - * - * - * Distributed under the Boost Software License, Version 1.0. - * - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - *********************************************************************************************************************/ - - -/****************************************************************************************************//** - * @file TLE94x1.h - * - * @brief Main header declaration file for TLE94x1 SBC family device - * - * @version V1.0.0 - * @date 15. April 2019 - * @author Markus Noll / markus.noll@infineon.com - * @author Yannek Micha Rixen / Yannek.Rixen@infineon.com - *******************************************************************************************************/ - - - - -#ifndef TLE94x1_H -#define TLE94x1_H - - - - - - -/* ================================================================================ */ -/* ============================ HEADER FILES ================================ */ -/* ================================================================================ */ - - - -#include "TLE94x1_DEFINES.h" -#include "TLE94x1_ISR.h" -#include "TLE94x1_SPI.h" -#include - - - - -/* ================================================================================ */ -/* ================================ MACROS ================================== */ -/* ================================================================================ */ - - -/** - * @def SBC_Write_Bit - * - * @brief This bit has to be set in order to write to a register. - */ -#define SBC_Write_Bit (0x80U) - -/** - * @def SBC_Read_Mask - * - * @brief A mask to prevent the user from accidentally writing to a register. - */ -#define SBC_Read_Mask (0x7FU) - - - - -/* ================================================================================ */ -/* =========================== Library Functions ============================ */ -/* ================================================================================ */ - -struct __SBC_ErrorCode; - -/** - * @brief A structure for simple error readout. - * - * flippedBitsMask is greater than 0 if the value read from the register at SBC_Register differs from expectedValue. - */ -typedef struct __SBC_ErrorCode { - uint8_t SBC_Register; //!< The register where an error occurred. - uint8_t flippedBitsMask; //!< Masks the bits that differ from the expected value. Is 0 if readout is as expected. - uint8_t expectedValue; //!< Expected readout of the register. -} SBC_ErrorCode; - -/** - * @brief Typedef for interrupt callbacks. - */ -typedef void (*SBC_Func_Callback)(uint8_t callbackHandler); - - - - - - -/* -------------------------------- Main Functions ------------------------------- */ - - -/** - * @brief This method will trigger the watchdog. - * - * The function must be called periodically according to the configured watchdog-time. - */ -SBC_ErrorCode SBC_WD_Trigger(void); - - -/** - * @brief This method will proceed a readout of a register. - * - * @param SBC_Reg Address of the register to be read out. See TLE94x1_DEFINES.h for definitions - * @retval A 16 bit value will be returned. - * Bit[15:8] is the Status-Information-Field, Bit [7:0] is the read register-value. - * For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet. - */ -uint16_t SBC_Read_Command(uint8_t SBC_Reg); - - -/** - * @brief This method will proceed a readout of a dedicated bitfield within a register - * - * @param SBC_Reg Address of the register to be readout. See TLE94x1_DEFINES.h for definitions - * @param SBC_FieldMsk Bit mask of the field to be readout. See TLE94x1_DEFINES.h for definitions - * @param SBC_FieldPos Bit position of the field to be readout. See TLE94x1_DEFINES.h for definitions - * - * - * @retval A 8 bit value will be returned and includes the data of the bitfield to be read out * - */ -uint8_t SBC_Read_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos); - - - -/** - * @brief Writes a whole byte to a register and verifies it. - * - * @param SBC_Reg Address of the register to be manipulated. See TLE94x1_DEFINES.h for definitions - * @param SBC_Val Byte to write to SBC_Reg - * @param *returnval A 16 bit value will be returned. - * Bit[15:8] is the Status-Information-Field, Bit [7:0] is the value of the manipulated register before write - * For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet. - * - * @retval See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Write_Reg(uint8_t SBC_Reg, uint8_t SBC_Val, uint16_t * returnval); - - -/** - * @brief This method can be used for manipulating a single bit-field in a control-register. - * - * It will readout the old value of the registers, manipulate the desired bit-field and keep - * the other bit-configuration as it was. - * For usage examples have a look at the implementations of different API calls below. - * - * @param SBC_Reg Address of the register to be manipulated. See TLE94x1_DEFINES.h for definitions - * @param SBC_FieldMsk Bit mask of the field to manipulate. See TLE94x1_DEFINES.h for definitions - * @param SBC_FieldPos Bit position of the field to manipulate. See TLE94x1_DEFINES.h for definitions - * @param SBC_FieldVal New value which will be written to the bit-field. See TLE94x1_DEFINES.h for enumerations - * @param *returnval A 16 bit value will be returned. - * Bit[15:8] is the Status-Information-Field, Bit [7:0] is the value of the manipulated register before write - * For furhter information of the Status-Information-Field see chapter 13.3 in the datasheet. - * - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - * - */ -SBC_ErrorCode SBC_Write_RegField(uint8_t SBC_Reg, uint8_t SBC_FieldMsk, uint8_t SBC_FieldPos, uint8_t SBC_FieldVal, uint16_t * returnval); - - -/** - * @brief This method must be called one time at startup of the microcontroller. - * - * This method will initialize all registers of the SBC with the configuration-data of SBC_TLE94x1.h. - * After this, the SBC can be used as normal. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Init(void); - -/* -------------------------------- ISR Functions -------------------------------- */ - - -/** - * @brief This function can register a self-defined function to a specific interrupt-event of the SBC. - * - * Everytime the SBC_ISR() method is called and the associated status-bit is set, it will consider to - * proceed a callback to this function later. - * See all the possible ISR_Vectors in the TLE94x1_ISR.h - * - * - * @param ISR_Vector Definition of the interrupt event. See all possible events in TLE94x1_ISR.h - * - * @param *Callback_Handler Pointer to the function which will be called back. - * The function must accept a uint8_t as first argument. - */ -void SBC_Register_Callback(uint32_t ISR_Vector, void (*Callback_Handler)(uint8_t callbackHandler)); - - -/** - * @brief Interrupt Service Routine for handling interrupts. - * - * This method must be called automatically everytime a rising-edge on the INTN pin is recognized. - * In case, the INTN pin is not connected, this method can also be called periodically by the user during runtime. - * The ISR will proceed a readout of all registered interrupts. If a status-bit of a registered interrupt is set, - * it will initiate a callback to the registered function and give the registered function the status-register value - * as a parameter. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_ISR(void); - - - -/* -------------------------------- API Calls ----------------------------------- */ - -/** - * @brief Enters SBC normal mode - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Mode_Normal(void); - - -/** - * @brief Enters SBC stop mode - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Mode_Stop(void); - - -/** - * @brief Clears all wake status registers and enter SBC sleep mode. Depending on configuration also the selective-wake feature will be initialized - * before entering sleep mode. In case, the SWK option is enabled and the internal CAN protocol handler is not in sync when calling this function, - * the sleep mode will be not entered. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Mode_Sleep(void); - - -/** - * @brief Sets the duty-cycle of the internal PWM generator - * - * @param PWM_DC Set the duty-cycle with values of 0-255 for 0% to 100% - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Set_DutyCycle_PWM(uint8_t PWM_DC); - - -/** - * @brief Sets the OnTime of the internal timer. - * - * @param OnTime On time which will be configured to the timer. See TLE94x1_DEFINES.h for enumerations. - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Set_Timer_On(uint8_t OnTime); - -/** - * @brief Sets the Period time of the internal timer - * - * @param Period Period time which will be configured to the timer. See TLE94x1_DEFINES.h for enumerations. - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Set_Timer_Period(uint8_t Period); - - -/** - * @brief FO output activated by software for testing. Only working if FO/GPIO is configured as FO - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_FO_Test_On(void); - - -/** - * @brief FO output deactivated by software for testing. Only working if FO/GPIO is configured as FO - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_FO_Test_Off(void); - - -/** - * @brief Charge-Pump (VCP-Pin) is enabled. See chapter 5.3 in datasheet. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_CP_On(void); - - -/** - * @brief Charge-Pump (VCP-Pin) is disabled. See chapter 5.3 in datasheet. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_CP_Off(void); - - -/** - * @brief Enable Voltage Sensing. No wake-up events are generated. See chapter 9.2.4 in datasheet. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_WK_MEAS_On(void); - - -/** - * @brief Disable Voltage Sensing and enable wake-up functionality. See chapter 9.2.4 in datasheet. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_WK_MEAS_Off(void); - - -/** - * @brief WK is enabled as wake source. See chapter 5.2. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_TIMER_WK_EN_On(void); - - -/** - * @brief WK wake-up disabled. See chapter 5.2. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_TIMER_WK_EN_Off(void); - - -/** - * @brief Reads System Status Control, both lower and higher bits. See page 138 in datasheet. - * - * @retval Upper 8 bit are read from register SBC_SYS_STATUS_CTRL_1 and the lower 8 bit from SBC_SYS_STATUS_CTRL_0 - */ -uint16_t SBC_SYS_STAT_Read(void); - - -/** - * @brief Writes System Status Control, both lower and higher bits. See page 138 in datasheet. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_SYS_STAT_Write(uint16_t SystemStatus); - - -/** - * @brief Locks CP_EN, GPIO configuration and 'rwl'-bits. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Lock_Configuration(void); - - -/** - * @brief Unlocks CP_EN, GPIO configuration and 'rwl'-bits. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Unlock_Configuration(void); - - -/** - * @brief Clears both Wake Status registers. - * - * @retval SBC_ErrorCode See description of SBC_ErrorCode. - */ -SBC_ErrorCode SBC_Clear_Wake_Status(void); - -#endif /*TLE94x1_H*/ diff --git a/cva_bootloader_m0118/src/TLE9461/TLE94x1_DEFINES.h b/cva_bootloader_m0118/src/TLE9461/TLE94x1_DEFINES.h deleted file mode 100644 index 57d8ab2..0000000 --- a/cva_bootloader_m0118/src/TLE9461/TLE94x1_DEFINES.h +++ /dev/null @@ -1,3248 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2019, Infineon Technologies AG - * - * - * Distributed under the Boost Software License, Version 1.0. - * - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - *********************************************************************************************************************/ - - -/****************************************************************************************************//** - * @file TLE94x1_DEFINES.h - * - * @brief Main header declaration file for TLE94x1 SBC family device - * - * @version V1.0.0 - * @date 15. April 2019 - * @author Markus Noll / markus.noll@infineon.com - * @author Yannek Micha Rixen / Yannek.Rixen@infineon.com - *******************************************************************************************************/ - - - -#ifndef TLE94x1_DEFINES_H -#define TLE94x1_DEFINES_H - - - - - - -/* ================================================================================ */ -/* ================ General Control Registers ================ */ -/* ================================================================================ */ - - - -/** - * @def SBC_M_S_CTRL - * - * @brief Control register address. - */ -#define SBC_M_S_CTRL (0b00000001U) - -/** - * @def SBC_HW_CTRL_0 - * - * @brief Control register address. - */ -#define SBC_HW_CTRL_0 (0b00000010U) - -/** - * @def SBC_WD_CTRL - * - * @brief Control register address. - */ -#define SBC_WD_CTRL (0b00000011U) - -/** - * @def SBC_BUS_CTRL_0 - * - * @brief Control register address. - */ -#define SBC_BUS_CTRL_0 (0b00000100U) - -/** - * @def SBC_WK_CTRL_0 - * - * @brief Control register address. - */ -#define SBC_WK_CTRL_0 (0b00000110U) - -/** - * @def SBC_WK_CTRL_1 - * - * @brief Control register address. - */ -#define SBC_WK_CTRL_1 (0b00000111U) - -/** - * @def SBC_WK_PUPD_CTRL - * - * @brief Control register address. - */ -#define SBC_WK_PUPD_CTRL (0b00001000U) - -/** - * @def SBC_BUS_CTRL_3 - * - * @brief Control register address. - */ -#define SBC_BUS_CTRL_3 (0b00001011U) - -/** - * @def SBC_TIMER_CTRL - * - * @brief Control register address. - */ -#define SBC_TIMER_CTRL (0b00001100U) - -/** - * @def SBC_HW_CTRL_1 - * - * @brief Control register address. - */ -#define SBC_HW_CTRL_1 (0b00001110U) - -/** - * @def SBC_HW_CTRL_2 - * - * @brief Control register address. - */ -#define SBC_HW_CTRL_2 (0b00001111U) - -/** - * @def SBC_GPIO_CTRL - * - * @brief Control register address. - */ -#define SBC_GPIO_CTRL (0b00010111U) - -/** - * @def SBC_PWM_CTRL - * - * @brief Control register address. - */ -#define SBC_PWM_CTRL (0b00011000U) - -/** - * @def SBC_PWM_FREQ_CTRL - * - * @brief Control register address. - */ -#define SBC_PWM_FREQ_CTRL (0b00011100U) - -/** - * @def SBC_HW_CTRL_3 - * - * @brief Control register address. - */ -#define SBC_HW_CTRL_3 (0b00011101U) - -/** - * @def SBC_SYS_STATUS_CTRL_0 - * - * @brief Control register address. - */ -#define SBC_SYS_STATUS_CTRL_0 (0b00011110U) - -/** - * @def SBC_SYS_STATUS_CTRL_1 - * - * @brief Control register address. - */ -#define SBC_SYS_STATUS_CTRL_1 (0b00011111U) - - - - - - -/* ================================================================================ */ -/* ================ Selective Wake Control Registers ================ */ -/* ================================================================================ */ - - - -/** - * @def SBC_SWK_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_CTRL (0b00100000U) - -/** - * @def SBC_SWK_BTL0_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_BTL0_CTRL (0b00100001U) - -/** - * @def SBC_SWK_BTL1_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_BTL1_CTRL (0b00100010U) - -/** - * @def SBC_SWK_ID3_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_ID3_CTRL (0b00100011U) - -/** - * @def SBC_SWK_ID2_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_ID2_CTRL (0b00100100U) - -/** - * @def SBC_SWK_ID1_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_ID1_CTRL (0b00100101U) - -/** - * @def SBC_SWK_ID0_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_ID0_CTRL (0b00100110U) - -/** - * @def SBC_SWK_MASK_ID3_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_MASK_ID3_CTRL (0b00100111U) - -/** - * @def SBC_SWK_MASK_ID2_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_MASK_ID2_CTRL (0b00101000U) - -/** - * @def SBC_SWK_MASK_ID1_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_MASK_ID1_CTRL (0b00101001U) - -/** - * @def SBC_SWK_MASK_ID0_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_MASK_ID0_CTRL (0b00101010U) - -/** - * @def SBC_SWK_DLC_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DLC_CTRL (0b00101011U) - -/** - * @def SBC_SWK_DATA7_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA7_CTRL (0b00101100U) - -/** - * @def SBC_SWK_DATA6_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA6_CTRL (0b00101101U) - -/** - * @def SBC_SWK_DATA5_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA5_CTRL (0b00101110U) - -/** - * @def SBC_SWK_DATA4_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA4_CTRL (0b00101111U) - -/** - * @def SBC_SWK_DATA3_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA3_CTRL (0b00110000U) - -/** - * @def SBC_SWK_DATA2_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA2_CTRL (0b00110001U) - -/** - * @def SBC_SWK_DATA1_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA1_CTRL (0b00110010U) - -/** - * @def SBC_SWK_DATA0_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_DATA0_CTRL (0b00110011U) - -/** - * @def SBC_SWK_CAN_FD_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_CAN_FD_CTRL (0b00110100U) - -/** - * @def SBC_SWK_OSC_TRIM_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_OSC_TRIM_CTRL (0b00111000U) - -/** - * @def SBC_SWK_OPT_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_OPT_CTRL (0b00111001U) - -/** - * @def SBC_SWK_OSC_CAL_H_STAT - * - * @brief Selective wake register address. - */ -#define SBC_SWK_OSC_CAL_H_STAT (0b00111010U) - -/** - * @def SBC_SWK_OSC_CAL_L_STAT - * - * @brief Selective wake register address. - */ -#define SBC_SWK_OSC_CAL_L_STAT (0b00111011U) - -/** - * @def SBC_SWK_CDR_CTRL1 - * - * @brief Selective wake register address. - */ -#define SBC_SWK_CDR_CTRL1 (0b00111100U) - -/** - * @def SBC_SWK_CDR_CTRL2 - * - * @brief Selective wake register address. - */ -#define SBC_SWK_CDR_CTRL2 (0b00111101U) - -/** - * @def SBC_SWK_CDR_LIMIT_HIGH_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_CDR_LIMIT_HIGH_CTRL (0b00111110U) - -/** - * @def SBC_SWK_CDR_LIMIT_LOW_CTRL - * - * @brief Selective wake register address. - */ -#define SBC_SWK_CDR_LIMIT_LOW_CTRL (0b00111111U) - - - - - - -/* ================================================================================ */ -/* ================ General Status Registers ================ */ -/* ================================================================================ */ - - - - -/** - * @def SBC_SUP_STAT_1 - * - * @brief Status register address. - */ -#define SBC_SUP_STAT_1 (0b01000000U) - -/** - * @def SBC_SUP_STAT_0 - * - * @brief Status register address. - */ -#define SBC_SUP_STAT_0 (0b01000001U) - -/** - * @def SBC_THERM_STAT - * - * @brief Status register address. - */ -#define SBC_THERM_STAT (0b01000010U) - -/** - * @def SBC_DEV_STAT - * - * @brief Status register address. - */ -#define SBC_DEV_STAT (0b01000011U) - -/** - * @def SBC_BUS_STAT - * - * @brief Status register address. - */ -#define SBC_BUS_STAT (0b01000100U) - -/** - * @def SBC_WK_STAT_0 - * - * @brief Status register address. - */ -#define SBC_WK_STAT_0 (0b01000110U) - -/** - * @def SBC_WK_STAT_1 - * - * @brief Status register address. - */ -#define SBC_WK_STAT_1 (0b01000111U) - -/** - * @def SBC_WK_LVL_STAT - * - * @brief Status register address. - */ -#define SBC_WK_LVL_STAT (0b01001000U) - -/** - * @def SBC_GPIO_OC_STAT - * - * @brief Status register address. - */ -#define SBC_GPIO_OC_STAT (0b01010100U) - -/** - * @def SBC_GPIO_OL_STAT - * - * @brief Status register address. - */ -#define SBC_GPIO_OL_STAT (0b01010101U) - - - - - - -/* ================================================================================ */ -/* ================ Selective Wake Status Registers ================ */ -/* ================================================================================ */ - - - - -/** - * @def SBC_SWK_STAT - * - * @brief Selective wake status register address. - */ -#define SBC_SWK_STAT (0b01110000U) - -/** - * @def SBC_SWK_ECNT_STAT - * - * @brief Selective wake status register address. - */ -#define SBC_SWK_ECNT_STAT (0b01110001U) - -/** - * @def SBC_SWK_CDR_STAT1 - * - * @brief Selective wake status register address. - */ -#define SBC_SWK_CDR_STAT1 (0b01110010U) - -/** - * @def SBC_SWK_CDR_STAT2 - * - * @brief Selective wake status register address. - */ -#define SBC_SWK_CDR_STAT2 (0b01110011U) - -/** - * @def SBC_FAM_PROD_STAT - * - * @brief Selective wake status register address. - */ -#define SBC_FAM_PROD_STAT (0b01111110U) - - - - - - -/* ================================================================================ */ -/* ============ General Control Registers Position & Mask ================ */ -/* ================================================================================ */ - - - -/* -------------------------------- M_S_CTRL ------------------------------------ */ - -/** - * @def SBC_M_S_CTRL_MODE_Pos - * - * @brief Control register bit position. - */ -#define SBC_M_S_CTRL_MODE_Pos (6U) -/** - * @def SBC_M_S_CTRL_MODE_Msk - * - * @brief Control register bit mask. - */ -#define SBC_M_S_CTRL_MODE_Msk (0b11000000U) -/** - * @def SBC_M_S_CTRL_VCC2_ON_Pos - * - * @brief Control register bit position. - */ -#define SBC_M_S_CTRL_VCC2_ON_Pos (3U) -/** - * @def SBC_M_S_CTRL_VCC2_ON_Msk - * - * @brief Control register bit mask. - */ -#define SBC_M_S_CTRL_VCC2_ON_Msk (0b00011000U) -/** - * @def SBC_M_S_CTRL_VCC1_OV_RST_Pos - * - * @brief Control register bit position. - */ -#define SBC_M_S_CTRL_VCC1_OV_RST_Pos (2U) -/** - * @def SBC_M_S_CTRL_VCC1_OV_RST_Msk - * - * @brief Control register bit mask. - */ -#define SBC_M_S_CTRL_VCC1_OV_RST_Msk (0b00000100U) -/** - * @def SBC_M_S_CTRL_VCC1_RT_Pos - * - * @brief Control register bit position. - */ -#define SBC_M_S_CTRL_VCC1_RT_Pos (0U) -/** - * @def SBC_M_S_CTRL_VCC1_RT_Msk - * - * @brief Control register bit mask. - */ -#define SBC_M_S_CTRL_VCC1_RT_Msk (0b00000011U) - - -/* -------------------------------- HW_CTRL_0 ----------------------------------- */ - - -/** - * @def SBC_HW_CTRL_0_SOFT_RESET_RST_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_0_SOFT_RESET_RST_Pos (6U) - -/** - * @def SBC_HW_CTRL_0_SOFT_RESET_RST_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_0_SOFT_RESET_RST_Msk (0b01000000U) - -/** - * @def SBC_HW_CTRL_0_FO_ON_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_0_FO_ON_Pos (5U) - -/** - * @def SBC_HW_CTRL_0_FO_ON_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_0_FO_ON_Msk (0b00100000U) - -/** - * @def SBC_HW_CTRL_0_CP_EN_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_0_CP_EN_Pos (2U) - -/** - * @def SBC_HW_CTRL_0_CP_EN_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_0_CP_EN_Msk (0b00000100U) - -/** - * @def SBC_HW_CTRL_0_CFG1_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_0_CFG1_Pos (0U) - -/** - * @def SBC_HW_CTRL_0_CFG1_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_0_CFG1_Msk (0b00000001U) - - -/* -------------------------------- WD_CTRL ----------------------------------- */ - - -/** - * @def SBC_WD_CTRL_CHECKSUM_Pos - * - * @brief Control register bit position. - */ -#define SBC_WD_CTRL_CHECKSUM_Pos (7U) - -/** - * @def SBC_WD_CTRL_CHECKSUM_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WD_CTRL_CHECKSUM_Msk (0b10000000U) - -/** - * @def SBC_WD_CTRL_WD_STM_EN_0_Pos - * - * @brief Control register bit position. - */ -#define SBC_WD_CTRL_WD_STM_EN_0_Pos (6U) - -/** - * @def SBC_WD_CTRL_WD_STM_EN_0_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WD_CTRL_WD_STM_EN_0_Msk (0b01000000U) - -/** - * @def SBC_WD_CTRL_WD_WIN_Pos - * - * @brief Control register bit position. - */ -#define SBC_WD_CTRL_WD_WIN_Pos (5U) - -/** - * @def SBC_WD_CTRL_WD_WIN_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WD_CTRL_WD_WIN_Msk (0b00100000U) - -/** - * @def SBC_WD_CTRL_WD_EN_WK_BUS_Pos - * - * @brief Control register bit position. - */ -#define SBC_WD_CTRL_WD_EN_WK_BUS_Pos (4U) - -/** - * @def SBC_WD_CTRL_WD_EN_WK_BUS_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WD_CTRL_WD_EN_WK_BUS_Msk (0b00010000U) - -/** - * @def SBC_WD_CTRL_WD_TIMER_Pos - * - * @brief Control register bit position. - */ -#define SBC_WD_CTRL_WD_TIMER_Pos (0U) - -/** - * @def SBC_WD_CTRL_WD_TIMER_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WD_CTRL_WD_TIMER_Msk (0b00000111U) - - -/* -------------------------------- BUS_CTRL_0 ---------------------------------- */ - -/** - * @def SBC_BUS_CTRL_0_CAN_Pos - * - * @brief Control register bit position. - */ -#define SBC_BUS_CTRL_0_CAN_Pos (0U) - -/** - * @def SBC_BUS_CTRL_0_CAN_Msk - * - * @brief Control register bit mask. - */ -#define SBC_BUS_CTRL_0_CAN_Msk (0b00000111U) - - -/* -------------------------------- WK_CTRL_0 ----------------------------------- */ - -/** - * @def SBC_WK_CTRL_0_TIMER_WK_EN_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_CTRL_0_TIMER_WK_EN_Pos (6U) - -/** - * @def SBC_WK_CTRL_0_TIMER_WK_EN_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_CTRL_0_TIMER_WK_EN_Msk (0b01000000U) - -/** - * @def SBC_WK_CTRL_0_WD_STM_EN_1_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_CTRL_0_WD_STM_EN_1_Pos (2U) - -/** - * @def SBC_WK_CTRL_0_WD_STM_EN_1_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_CTRL_0_WD_STM_EN_1_Msk (0b00000100U) - - -/* -------------------------------- WK_CTRL_1 ----------------------------------- */ - - -/** - * @def SBC_WK_CTRL_1_INT_GLOBAL_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_CTRL_1_INT_GLOBAL_Pos (7U) - -/** - * @def SBC_WK_CTRL_1_INT_GLOBAL_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_CTRL_1_INT_GLOBAL_Msk (0b10000000U) - -/** - * @def SBC_WK_CTRL_1_WK_MEAS_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_CTRL_1_WK_MEAS_Pos (5U) - -/** - * @def SBC_WK_CTRL_1_WK_MEAS_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_CTRL_1_WK_MEAS_Msk (0b00100000U) - -/** - * @def SBC_WK_CTRL_1_WK_EN_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_CTRL_1_WK_EN_Pos (0U) - -/** - * @def SBC_WK_CTRL_1_WK_EN_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_CTRL_1_WK_EN_Msk (0b00000001U) - - -/* -------------------------------- WK_PUPD_CTRL -------------------------------- */ - - -/** - * @def SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Pos (6U) - -/** - * @def SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_PUPD_CTRL_GPIO_WK_PUPD_Msk (0b11000000U) - -/** - * @def SBC_WK_PUPD_CTRL_WK_PUPD_Pos - * - * @brief Control register bit position. - */ -#define SBC_WK_PUPD_CTRL_WK_PUPD_Pos (0U) - -/** - * @def SBC_WK_PUPD_CTRL_WK_PUPD_Msk - * - * @brief Control register bit mask. - */ -#define SBC_WK_PUPD_CTRL_WK_PUPD_Msk (0b00000011U) - - -/* ------------------------------- BUS_CTRL_3 ---------------------------------- */ - -/** - * @def SBC_BUS_CTRL_3_CAN_FLASH_Pos - * - * @brief Control register bit position. - */ -#define SBC_BUS_CTRL_3_CAN_FLASH_Pos (4U) - -/** - * @def SBC_BUS_CTRL_3_CAN_FLASH_Msk - * - * @brief Control register bit mask. - */ -#define SBC_BUS_CTRL_3_CAN_FLASH_Msk (0b00010000U) - - -/* ------------------------------- TIMER_CTRL ---------------------------------- */ - - -/** - * @def SBC_TIMER_CTRL_TIMER_ON_Pos - * - * @brief Control register bit position. - */ -#define SBC_TIMER_CTRL_TIMER_ON_Pos (4U) - -/** - * @def SBC_TIMER_CTRL_TIMER_ON_Msk - * - * @brief Control register bit mask. - */ -#define SBC_TIMER_CTRL_TIMER_ON_Msk (0b01110000U) - -/** - * @def SBC_TIMER_CTRL_TIMER_PER_Pos - * - * @brief Control register bit position. - */ -#define SBC_TIMER_CTRL_TIMER_PER_Pos (0U) - -/** - * @def SBC_TIMER_CTRL_TIMER_PER_Msk - * - * @brief Control register bit mask. - */ -#define SBC_TIMER_CTRL_TIMER_PER_Msk (0b00001111U) - - -/* -------------------------------- HW_CTRL_1 ----------------------------------- */ - - -/** - * @def SBC_HW_CTRL_1_RSTN_HYS_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_1_RSTN_HYS_Pos (7U) - -/** - * @def SBC_HW_CTRL_1_RSTN_HYS_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_1_RSTN_HYS_Msk (0b10000000U) - -/** - * @def SBC_HW_CTRL_1_TSD2_DEL_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_1_TSD2_DEL_Pos (5U) - -/** - * @def SBC_HW_CTRL_1_TSD2_DEL_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_1_TSD2_DEL_Msk (0b00100000U) - -/** - * @def SBC_HW_CTRL_1_RSTN_DEL_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_1_RSTN_DEL_Pos (4U) - -/** - * @def SBC_HW_CTRL_1_RSTN_DEL_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_1_RSTN_DEL_Msk (0b00010000U) - -/** - * @def SBC_HW_CTRL_1_CFG_LOCK_0_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_1_CFG_LOCK_0_Pos (3U) - -/** - * @def SBC_HW_CTRL_1_CFG_LOCK_0_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_1_CFG_LOCK_0_Msk (0b00001000U) - - -/* -------------------------------- HW_CTRL_2 ----------------------------------- */ - - -/** - * @def SBC_HW_CTRL_2_2MHZ_FREQ_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_2_2MHZ_FREQ_Pos (5U) - -/** - * @def SBC_HW_CTRL_2_2MHZ_FREQ_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_2_2MHZ_FREQ_Msk (0b11100000U) - -/** - * @def SBC_HW_CTRL_2_I_PEAK_TH_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_2_I_PEAK_TH_Pos (4U) - -/** - * @def SBC_HW_CTRL_2_I_PEAK_TH_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_2_I_PEAK_TH_Msk (0b00010000U) - -/** - * @def SBC_HW_CTRL_2_SS_MOD_FR_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_2_SS_MOD_FR_Pos (2U) - -/** - * @def SBC_HW_CTRL_2_SS_MOD_FR_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_2_SS_MOD_FR_Msk (0b00001100U) - -/** - * @def SBC_HW_CTRL_2_CFG_LOCK_1_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_2_CFG_LOCK_1_Pos (0U) - -/** - * @def SBC_HW_CTRL_2_CFG_LOCK_1_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_2_CFG_LOCK_1_Msk (0b00000001U) - - -/* -------------------------------- GPIO_CTRL ----------------------------------- */ - -/** - * @def SBC_GPIO_CTRL_GPIO_Pos - * - * @brief Control register bit position. - */ -#define SBC_GPIO_CTRL_GPIO_Pos (0U) - -/** - * @def SBC_GPIO_CTRL_GPIO_Msk - * - * @brief Control register bit mask. - */ -#define SBC_GPIO_CTRL_GPIO_Msk (0b00000111U) - - -/* -------------------------------- PWM_CTRL -------------------------------------- */ - -/** - * @def SBC_PWM_DC_PWM_DC_Pos - * - * @brief Control register bit position. - */ -#define SBC_PWM_CTRL_PWM_DC_Pos (0U) - -/** - * @def SBC_PWM_DC_PWM_DC_Msk - * - * @brief Control register bit mask. - */ -#define SBC_PWM_CTRL_PWM_DC_Msk (0b11111111U) - - -/* -------------------------------- PWM_FREQ_CTRL -------------------------------------- */ - -/** - * @def SBC_PWM_FREQ_CTRL_PWM_FREQ_Pos - * - * @brief Control register bit position. - */ -#define SBC_PWM_FREQ_CTRL_PWM_FREQ_Pos (0U) - - -/** - * @def SBC_PWM_FREQ_CTRL_PWM_FREQ_Msk - * - * @brief Control register bit mask. - */ -#define SBC_PWM_FREQ_CTRL_PWM_FREQ_Msk (0b00000011U) - - -/* -------------------------------- HW_CTRL_3 ----------------------------------- */ - - -/** - * @def SBC_HW_CTRL_3_TSD_THR_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_3_TSD_THR_Pos (2U) - -/** - * @def SBC_HW_CTRL_3_TSD_THR_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_3_TSD_THR_Msk (0b00000100U) - -/** - * @def SBC_HW_CTRL_3_ICC1_LIM_ADJ_Pos - * - * @brief Control register bit position. - */ -#define SBC_HW_CTRL_3_ICC1_LIM_ADJ_Pos (0U) - -/** - * @def SBC_HW_CTRL_3_ICC1_LIM_ADJ_Msk - * - * @brief Control register bit mask. - */ -#define SBC_HW_CTRL_3_ICC1_LIM_ADJ_Msk (0b00000011U) - - -/* -------------------------------- SYS_STATUS_CTRL_0 --------------------------- */ - -/** - * @def SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Pos - * - * @brief Control register bit position. - */ -#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Pos (0U) - -/** - * @def SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Msk - * - * @brief Control register bit mask. - */ -#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_L_Msk (0b11111111U) - - -/* -------------------------------- SYS_STATUS_CTRL_1 --------------------------- */ - - -/** - * @def SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Pos - * - * @brief Control register bit position. - */ -#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Pos (0U) - -/** - * @def SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Msk - * - * @brief Control register bit mask. - */ -#define SBC_SYS_STATUS_CTRL_0_SYS_STAT_H_Msk (0b11111111U) - - - - - - -/* ================================================================================ */ -/* ======== Selective Wake Control Registers Position & Mask ============= */ -/* ================================================================================ */ - - - -/* -------------------------------- SWK_CTRL ------------------------------------ */ - - -/** - * @def SBC_SWK_CTRL_OSC_CAL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CTRL_OSC_CAL_Pos (7U) - -/** - * @def SBC_SWK_CTRL_OSC_CAL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CTRL_OSC_CAL_Msk (0b10000000U) - -/** - * @def SBC_SWK_CTRL_TRIM_EN_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CTRL_TRIM_EN_Pos (5U) - -/** - * @def SBC_SWK_CTRL_TRIM_EN_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CTRL_TRIM_EN_Msk (0b01100000U) - -/** - * @def SBC_SWK_CTRL_CANTO_MASK_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CTRL_CANTO_MASK_Pos (4U) - -/** - * @def SBC_SWK_CTRL_CANTO_MASK_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CTRL_CANTO_MASK_Msk (0b00010000U) - -/** - * @def SBC_SWK_CTRL_CFG_VAL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CTRL_CFG_VAL_Pos (0U) - -/** - * @def SBC_SWK_CTRL_CFG_VAL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CTRL_CFG_VAL_Msk (0b00000001U) - - -/* -------------------------------- SWK_BTL0_CTRL ------------------------------- */ - - -/** - * @def SBC_SWK_BTL0_CTRL_TBIT_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_BTL0_CTRL_TBIT_Pos (0U) - -/** - * @def SBC_SWK_BTL0_CTRL_TBIT_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_BTL0_CTRL_TBIT_Msk (0b11111111U) - - -/* -------------------------------- SWK_BTL1_CTRL ------------------------------- */ - - -/** - * @def SBC_SWK_BTL1_CTRL_SP_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_BTL1_CTRL_SP_Pos (0U) - -/** - * @def SBC_SWK_BTL1_CTRL_SP_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_BTL1_CTRL_SP_Msk (0b00111111U) - - -/* -------------------------------- SWK_ID3_CTRL -------------------------------- */ - - -/** - * @def SBC_SWK_ID3_CTRL_ID28_21_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_ID3_CTRL_ID28_21_Pos (0U) - -/** - * @def SBC_SWK_ID3_CTRL_ID28_21_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_ID3_CTRL_ID28_21_Msk (0b11111111U) - - -/* -------------------------------- SWK_ID2_CTRL -------------------------------- */ - - -/** - * @def SBC_SWK_ID2_CTRL_ID20_13_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_ID2_CTRL_ID20_13_Pos (0U) - -/** - * @def SBC_SWK_ID2_CTRL_ID20_13_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_ID2_CTRL_ID20_13_Msk (0b11111111U) - - -/* -------------------------------- SWK_ID1_CTRL -------------------------------- */ - - -/** - * @def SBC_SWK_ID1_CTRL_ID12_5_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_ID1_CTRL_ID12_5_Pos (0U) - -/** - * @def SBC_SWK_ID1_CTRL_ID12_5_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_ID1_CTRL_ID12_5_Msk (0b11111111U) - - -/* -------------------------------- SWK_ID0_CTRL -------------------------------- */ - - -/** - * @def SBC_SWK_ID0_CTRL_ID4_0_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_ID0_CTRL_ID4_0_Pos (2U) - -/** - * @def SBC_SWK_ID0_CTRL_ID4_0_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_ID0_CTRL_ID4_0_Msk (0b01111100U) - -/** - * @def SBC_SWK_ID0_CTRL_RTR_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_ID0_CTRL_RTR_Pos (1U) - -/** - * @def SBC_SWK_ID0_CTRL_RTR_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_ID0_CTRL_RTR_Msk (0b00000010U) - -/** - * @def SBC_SWK_ID0_CTRL_IDE_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_ID0_CTRL_IDE_Pos (0U) - -/** - * @def SBC_SWK_ID0_CTRL_IDE_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_ID0_CTRL_IDE_Msk (0b00000001U) - - -/* -------------------------------- SWK_MASK_ID3_CTRL --------------------------- */ - - -/** - * @def SBC_SWK_MASK_ID3_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_MASK_ID3_CTRL_Pos (0U) - -/** - * @def SBC_SWK_MASK_ID3_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_MASK_ID3_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_MASK_ID2_CTRL --------------------------- */ - - -/** - * @def SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Pos (0U) - -/** - * @def SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_MASK_ID2_CTRL_MASK_ID20_13_Msk (0b11111111U) - - -/* -------------------------------- SWK_MASK_ID1_CTRL --------------------------- */ - - -/** - * @def SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Pos (0U) - -/** - * @def SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_MASK_ID1_CTRL_MASK_ID12_5_Msk (0b11111111U) - - -/* -------------------------------- SWK_MASK_ID0_CTRL --------------------------- */ - - -/** - * @def SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Pos (2U) - -/** - * @def SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_MASK_ID0_CTRL_MASK_ID4_0_Msk (0b01111100U) - - -/* -------------------------------- SWK_DLC_CTRL -------------------------------- */ - - -/** - * @def SBC_SWK_DLC_CTRL_DLC_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DLC_CTRL_DLC_Pos (0U) - -/** - * @def SBC_SWK_DLC_CTRL_DLC_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DLC_CTRL_DLC_Msk (0b00001111U) - - -/* -------------------------------- SWK_DATA7_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA7_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA7_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA7_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA7_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA6_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA6_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA6_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA6_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA6_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA5_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA5_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA5_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA5_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA5_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA4_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA4_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA4_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA4_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA4_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA3_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA3_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA3_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA3_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA3_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA2_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA2_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA2_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA2_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA2_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA1_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA1_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA1_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA1_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA1_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_DATA0_CTRL ------------------------------ */ - - -/** - * @def SBC_SWK_DATA0_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_DATA0_CTRL_Pos (0U) - -/** - * @def SBC_SWK_DATA0_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_DATA0_CTRL_Msk (0b11111111U) - - -/* -------------------------------- SWK_CAN_FD_CTRL ----------------------------- */ - - -/** - * @def SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Pos (5U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CAN_FD_CTRL_DIS_ERR_CNT_Msk (0b00100000U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Pos (4U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CAN_FD_CTRL_RX_FILT_BYP_Msk (0b00010000U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_FD_FILTER_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CAN_FD_CTRL_FD_FILTER_Pos (1U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_FD_FILTER_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CAN_FD_CTRL_FD_FILTER_Msk (0b00001110U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Pos (0U) - -/** - * @def SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CAN_FD_CTRL_CAN_FD_EN_Msk (0b00000001U) - - -/* -------------------------------- SWK_OSC_TRIM_CTRL --------------------------- */ - - -/** - * @def SBC_SWK_OSC_TRIM_CTRL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_OSC_TRIM_CTRL_Pos (0U) - -/** - * @def SBC_SWK_OSC_TRIM_CTRL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_OSC_TRIM_CTRL_Msk (0b01111111U) - - -/* -------------------------------- SWK_OPT_CTRL -------------------------------- */ - - -/** - * @def SBC_SWK_OPT_CTRL_RX_WK_SEL_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_OPT_CTRL_RX_WK_SEL_Pos (7U) - -/** - * @def SBC_SWK_OPT_CTRL_RX_WK_SEL_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_OPT_CTRL_RX_WK_SEL_Msk (0b10000000U) - - -/* -------------------------------- SWK_OSC_CAL_H_STAT -------------------------- */ - - -/** - * @def SBC_SWK_OSC_CAL_H_STAT_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_OSC_CAL_H_STAT_Pos (0U) - -/** - * @def SBC_SWK_OSC_CAL_H_STAT_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_OSC_CAL_H_STAT_Msk (0b11111111U) - - -/* -------------------------------- SWK_OPT_CAL_L_STAT -------------------------- */ - - -/** - * @def SBC_SWK_OPT_CAL_L_STAT_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_OPT_CAL_L_STAT_Pos (0U) - -/** - * @def SBC_SWK_OPT_CAL_L_STAT_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_OPT_CAL_L_STAT_Msk (0b11111111U) - - -/* -------------------------------- SWK_CDR_CTRL1 ------------------------------- */ - - -/** - * @def SBC_SWK_CDR_CTRL1_SEL_FILT_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CDR_CTRL1_SEL_FILT_Pos (2U) - -/** - * @def SBC_SWK_CDR_CTRL1_SEL_FILT_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CDR_CTRL1_SEL_FILT_Msk (0b00001100U) - -/** - * @def SBC_SWK_CDR_CTRL1_CDR_EN_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CDR_CTRL1_CDR_EN_Pos (0U) - -/** - * @def SBC_SWK_CDR_CTRL1_CDR_EN_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CDR_CTRL1_CDR_EN_Msk (0b00000001U) - - -/* -------------------------------- SWK_CDR_CTRL2 ------------------------------- */ - - -/** - * @def SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Pos (0U) - -/** - * @def SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CDR_CTRL2_SEL_OSC_CLK_Msk (0b00000011U) - - -/* -------------------------------- SWK_CDR_LIMIT_HIGH_CTRL --------------------- */ - - -/** - * @def SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Pos (0U) - -/** - * @def SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CDR_LIMIT_HIGH_CTRL_CDR_LIM_H_Msk (0b11111111U) - - -/* -------------------------------- SWK_CDR_LIMIT_LOW_CTRL ---------------------- */ - - -/** - * @def SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Pos - * - * @brief Selective wake register bit position. - */ -#define SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Pos (0U) - -/** - * @def SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Msk - * - * @brief Selective wake register bit mask. - */ -#define SBC_SWK_CDR_LIMIT_LOW_CTRL_CDR_LIM_L_Msk (0b11111111U) - - - - - - -/* ================================================================================ */ -/* ============= General Status Registers Position & Mask ================ */ -/* ================================================================================ */ - - - -/* -------------------------------- SUP_STAT_1 ---------------------------------- */ - - -/** - * @def SBC_SUP_STAT_1_VS_UV_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_1_VS_UV_Pos (6U) - -/** - * @def SBC_SUP_STAT_1_VS_UV_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_1_VS_UV_Msk (0b01000000U) - -/** - * @def SBC_SUP_STAT_1_VS_OV_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_1_VS_OV_Pos (5U) - -/** - * @def SBC_SUP_STAT_1_VS_OV_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_1_VS_OV_Msk (0b00100000U) - -/** - * @def SBC_SUP_STAT_1_VCC1_OV_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_1_VCC1_OV_Pos (1U) - -/** - * @def SBC_SUP_STAT_1_VCC1_OV_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_1_VCC1_OV_Msk (0b00000010U) - -/** - * @def SBC_SUP_STAT_1_VCC1_WARN_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_1_VCC1_WARN_Pos (0U) - -/** - * @def SBC_SUP_STAT_1_VCC1_WARN_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_1_VCC1_WARN_Msk (0b00000001U) - - -/* -------------------------------- SUP_STAT_0 ---------------------------------- */ - - -/** - * @def SBC_SUP_STAT_0_POR_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_0_POR_Pos (7U) - -/** - * @def SBC_SUP_STAT_0_POR_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_0_POR_Msk (0b10000000U) - -/** - * @def SBC_SUP_STAT_0_VCC2_OT_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_0_VCC2_OT_Pos (4U) - -/** - * @def SBC_SUP_STAT_0_VCC2_OT_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_0_VCC2_OT_Msk (0b00010000U) - -/** - * @def SBC_SUP_STAT_0_VCC2_UV_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_0_VCC2_UV_Pos (3U) - -/** - * @def SBC_SUP_STAT_0_VCC2_UV_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_0_VCC2_UV_Msk (0b00001000U) - -/** - * @def SBC_SUP_STAT_0_VCC1_SC_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_0_VCC1_SC_Pos (2U) - -/** - * @def SBC_SUP_STAT_0_VCC1_SC_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_0_VCC1_SC_Msk (0b00000100U) - -/** - * @def SBC_SUP_STAT_0_VCC1_UV_Pos - * - * @brief General status register bit position. - */ -#define SBC_SUP_STAT_0_VCC1_UV_Pos (0U) - -/** - * @def SBC_SUP_STAT_0_VCC1_UV_Msk - * - * @brief General status register bit mask. - */ -#define SBC_SUP_STAT_0_VCC1_UV_Msk (0b00000001U) - - -/* -------------------------------- THERM_STAT ---------------------------------- */ - - -/** - * @def SBC_THERM_STAT_TSD2_SAFE_Pos - * - * @brief General status register bit position. - */ -#define SBC_THERM_STAT_TSD2_SAFE_Pos (3U) - -/** - * @def SBC_THERM_STAT_TSD2_SAFE_Msk - * - * @brief General status register bit mask. - */ -#define SBC_THERM_STAT_TSD2_SAFE_Msk (0b00001000U) - -/** - * @def SBC_THERM_STAT_TSD2_Pos - * - * @brief General status register bit position. - */ -#define SBC_THERM_STAT_TSD2_Pos (2U) - -/** - * @def SBC_THERM_STAT_TSD2_Msk - * - * @brief General status register bit mask. - */ -#define SBC_THERM_STAT_TSD2_Msk (0b00000100U) - -/** - * @def SBC_THERM_STAT_TSD1_Pos - * - * @brief General status register bit position. - */ -#define SBC_THERM_STAT_TSD1_Pos (1U) - -/** - * @def SBC_THERM_STAT_TSD1_Msk - * - * @brief General status register bit mask. - */ -#define SBC_THERM_STAT_TSD1_Msk (0b00000010U) - -/** - * @def SBC_THERM_STAT_TPW_Pos - * - * @brief General status register bit position. - */ -#define SBC_THERM_STAT_TPW_Pos (0U) - -/** - * @def SBC_THERM_STAT_TPW_Msk - * - * @brief General status register bit mask. - */ -#define SBC_THERM_STAT_TPW_Msk (0b00000001U) - - -/* -------------------------------- DEV_STAT ------------------------------------ */ - - -/** - * @def SBC_DEV_STAT_DEV_STAT_Pos - * - * @brief General status register bit position. - */ -#define SBC_DEV_STAT_DEV_STAT_Pos (6U) - -/** - * @def SBC_DEV_STAT_DEV_STAT_Msk - * - * @brief General status register bit mask. - */ -#define SBC_DEV_STAT_DEV_STAT_Msk (0b11000000U) - -/** - * @def SBC_DEV_STAT_WD_FAIL_Pos - * - * @brief General status register bit position. - */ -#define SBC_DEV_STAT_WD_FAIL_Pos (2U) - -/** - * @def SBC_DEV_STAT_WD_FAIL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_DEV_STAT_WD_FAIL_Msk (0b00001100U) - -/** - * @def SBC_DEV_STAT_SPI_FAIL_Pos - * - * @brief General status register bit position. - */ -#define SBC_DEV_STAT_SPI_FAIL_Pos (1U) - -/** - * @def SBC_DEV_STAT_SPI_FAIL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_DEV_STAT_SPI_FAIL_Msk (0b00000010U) - -/** - * @def SBC_DEV_STAT_FAILURE_Pos - * - * @brief General status register bit position. - */ -#define SBC_DEV_STAT_FAILURE_Pos (0U) - -/** - * @def SBC_DEV_STAT_FAILURE_Msk - * - * @brief General status register bit mask. - */ -#define SBC_DEV_STAT_FAILURE_Msk (0b00000001U) - - -/* -------------------------------- BUS_STAT ------------------------------------ */ - - -/** - * @def SBC_BUS_STAT_CANTO_Pos - * - * @brief General status register bit position. - */ -#define SBC_BUS_STAT_CANTO_Pos (4U) - -/** - * @def SBC_BUS_STAT_CANTO_Msk - * - * @brief General status register bit mask. - */ -#define SBC_BUS_STAT_CANTO_Msk (0b00010000U) - -/** - * @def SBC_BUS_STAT_SYSERR_Pos - * - * @brief General status register bit position. - */ -#define SBC_BUS_STAT_SYSERR_Pos (3U) - -/** - * @def SBC_BUS_STAT_SYSERR_Msk - * - * @brief General status register bit mask. - */ -#define SBC_BUS_STAT_SYSERR_Msk (0b00001000U) - -/** - * @def SBC_BUS_STAT_CAN_FAIL_Pos - * - * @brief General status register bit position. - */ -#define SBC_BUS_STAT_CAN_FAIL_Pos (1U) - -/** - * @def SBC_BUS_STAT_CAN_FAIL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_BUS_STAT_CAN_FAIL_Msk (0b00000110U) - -/** - * @def SBC_BUS_STAT_VCAN_UV_Pos - * - * @brief General status register bit position. - */ -#define SBC_BUS_STAT_VCAN_UV_Pos (0U) - -/** - * @def SBC_BUS_STAT_VCAN_UV_Msk - * - * @brief General status register bit mask. - */ -#define SBC_BUS_STAT_VCAN_UV_Msk (0b00000001U) - - -/* -------------------------------- WK_STAT_0 ----------------------------------- */ - - -/** - * @def SBC_WK_STAT_0_CAN_WU_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_STAT_0_CAN_WU_Pos (5U) - -/** - * @def SBC_WK_STAT_0_CAN_WU_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_STAT_0_CAN_WU_Msk (0b00100000U) - -/** - * @def SBC_WK_STAT_0_TIMER_WU_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_STAT_0_TIMER_WU_Pos (4U) - -/** - * @def SBC_WK_STAT_0_TIMER_WU_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_STAT_0_TIMER_WU_Msk (0b00010000U) - -/** - * @def SBC_WK_STAT_0_WK_WU_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_STAT_0_WK_WU_Pos (0U) - -/** - * @def SBC_WK_STAT_0_WK_WU_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_STAT_0_WK_WU_Msk (0b00000001U) - - -/* -------------------------------- WK_STAT_1 ----------------------------------- */ - - -/** - * @def SBC_WK_STAT_1_GPIO_WK_WU_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_STAT_1_GPIO_WK_WU_Pos (4U) - -/** - * @def SBC_WK_STAT_1_GPIO_WK_WU_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_STAT_1_GPIO_WK_WU_Msk (0b00010000U) - - -/* -------------------------------- WK_LVL_STAT --------------------------------- */ - - -/** - * @def SBC_WK_LVL_STAT_SBC_DEV_LVL_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_LVL_STAT_SBC_DEV_LVL_Pos (7U) - -/** - * @def SBC_WK_LVL_STAT_SBC_DEV_LVL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_LVL_STAT_SBC_DEV_LVL_Msk (0b10000000U) - -/** - * @def SBC_WK_LVL_STAT_CFG0_STATE_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_LVL_STAT_CFG0_STATE_Pos (6U) - -/** - * @def SBC_WK_LVL_STAT_CFG0_STATE_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_LVL_STAT_CFG0_STATE_Msk (0b01000000U) - -/** - * @def SBC_WK_LVL_STAT_GPIO_LVL_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_LVL_STAT_GPIO_LVL_Pos (4U) - -/** - * @def SBC_WK_LVL_STAT_GPIO_LVL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_LVL_STAT_GPIO_LVL_Msk (0b00010000U) - -/** - * @def SBC_WK_LVL_STAT_WK_LVL_Pos - * - * @brief General status register bit position. - */ -#define SBC_WK_LVL_STAT_WK_LVL_Pos (0U) - -/** - * @def SBC_WK_LVL_STAT_WK_LVL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_WK_LVL_STAT_WK_LVL_Msk (0b00000001U) - - -/* -------------------------------- GPIO_OC_STAT -------------------------------- */ - - -/** - * @def SBC_GPIO_OC_STAT_GPIO_OC_Pos - * - * @brief General status register bit position. - */ -#define SBC_GPIO_OC_STAT_GPIO_OC_Pos (6U) - -/** - * @def SBC_GPIO_OC_STAT_GPIO_OC_Msk - * - * @brief General status register bit mask. - */ -#define SBC_GPIO_OC_STAT_GPIO_OC_Msk (0b01000000U) - - -/* -------------------------------- GPIO_OL_STAT -------------------------------- */ - - -/** - * @def SBC_GPIO_OL_STAT_GPIO_OL_Pos - * - * @brief General status register bit position. - */ -#define SBC_GPIO_OL_STAT_GPIO_OL_Pos (6U) - -/** - * @def SBC_GPIO_OL_STAT_GPIO_OL_Msk - * - * @brief General status register bit mask. - */ -#define SBC_GPIO_OL_STAT_GPIO_OL_Msk (0b01000000U) - - - - - - - -/* ================================================================================ */ -/* ========= Selective Wake Status Registers Position & Mask ============= */ -/* ================================================================================ */ - - - - -/* -------------------------------- SWK_STAT ------------------------------------ */ - - -/** - * @def SBC_SWK_STAT_SYNC_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_STAT_SYNC_Pos (6U) - -/** - * @def SBC_SWK_STAT_SYNC_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_STAT_SYNC_Msk (0b01000000U) - -/** - * @def SBC_SWK_STAT_CANSIL_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_STAT_CANSIL_Pos (3U) - -/** - * @def SBC_SWK_STAT_CANSIL_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_STAT_CANSIL_Msk (0b00001000U) - -/** - * @def SBC_SWK_STAT_SWK_SET_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_STAT_SWK_SET_Pos (2U) - -/** - * @def SBC_SWK_STAT_SWK_SET_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_STAT_SWK_SET_Msk (0b00000100U) - -/** - * @def SBC_SWK_STAT_WUP_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_STAT_WUP_Pos (1U) - -/** - * @def SBC_SWK_STAT_WUP_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_STAT_WUP_Msk (0b00000010U) - -/** - * @def SBC_SWK_STAT_WUF_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_STAT_WUF_Pos (0U) - -/** - * @def SBC_SWK_STAT_WUF_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_STAT_WUF_Msk (0b00000001U) - - - - - -/* -------------------------------- SWK_ECNT_STAT -------------------------------- */ - - -/** - * @def SBC_SWK_ECNT_STAT_ECNT_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_ECNT_STAT_ECNT_Pos (0U) - -/** - * @def SBC_SWK_ECNT_STAT_ECNT_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_ECNT_STAT_ECNT_Msk (0b00111111U) - - -/* -------------------------------- SWK_CDR_STAT1 -------------------------------- */ - - -/** - * @def SBC_SWK_CDR_STAT1_NAVG_SAT_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_CDR_STAT1_NAVG_SAT_Pos (0U) - -/** - * @def SBC_SWK_CDR_STAT1_NAVG_SAT_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_CDR_STAT1_NAVG_SAT_Msk (0b11111111U) - - -/* -------------------------------- SWK_CDR_STAT2 -------------------------------- */ - - -/** - * @def SBC_SWK_CDR_STAT2_NAVG_SAT_Pos - * - * @brief Selective wake status register bit position. - */ -#define SBC_SWK_CDR_STAT2_NAVG_SAT_Pos (4U) - -/** - * @def SBC_SWK_CDR_STAT2_NAVG_SAT_Msk - * - * @brief Selective wake status register bit mask. - */ -#define SBC_SWK_CDR_STAT2_NAVG_SAT_Msk (0b11110000U) - - - - - - -/* ================================================================================ */ -/* ====== Family and Product Information Register Position & Mask ======== */ -/* ================================================================================ */ - - - -/* -------------------------------- FAM_PROD_STAT -------------------------------- */ - - -/** - * @def SBC_FAM_PROD_STAT_FAM_Pos - * - * @brief Family and product register bit position. - */ -#define SBC_FAM_PROD_STAT_FAM_Pos (4U) - -/** - * @def SBC_FAM_PROD_STAT_FAM_Msk - * - * @brief Family and product register bit mask. - */ -#define SBC_FAM_PROD_STAT_FAM_Msk (0b11110000U) - -/** - * @def SBC_FAM_PROD_STAT_PROD_Pos - * - * @brief Family and product register bit position. - */ -#define SBC_FAM_PROD_STAT_PROD_Pos (0U) - -/** - * @def SBC_FAM_PROD_STAT_PROD_Msk - * - * @brief Family and product register bit mask. - */ -#define SBC_FAM_PROD_STAT_PROD_Msk (0b00001111U) - - - - - - -/* ================================================================================ */ -/* =============== General Control Registers Enumerations ================ */ -/* ================================================================================ */ - - - -/* -------------------------------- M_S_CTRL ------------------------------------ */ - -typedef enum -{ - SBC_MODE_NORMAL = 0x00U, - SBC_MODE_SLEEP, - SBC_MODE_STOP, - SBC_MODE_RESET -}; - -typedef enum -{ - SBC_VCC2_OFF = 0x00U, - SBC_VCC2_ON_NORMAL, - SBC_VCC2_ON_NORMAL_STOP, - SBC_VCC2_ON_ALWAYS -}; - -typedef enum -{ - SBC_VCC1_OV_RST_NOACTION = 0x00U, - SBC_VCC1_OV_RST_RESTART_FAILSAFE -}; - -typedef enum -{ - SBC_VCC1_RT_VRT1 = 0x00U, - SBC_VCC1_RT_VRT2, - SBC_VCC1_RT_VRT3, - SBC_VCC1_RT_VRT4 -}; - - -/* -------------------------------- HW_CTRL_0 ----------------------------------- */ - -typedef enum -{ - SBC_SOFT_RESET_RST_TRIGGER_SOFTRST = 0x00U, - SBC_SOFT_RESET_RST_NOTRIGGER_SOFTRST -}; - -typedef enum -{ - SBC_FO_ON_NOT_ACTIVE = 0x00U, - SBC_FO_ON_ACTIVE -}; - -typedef enum -{ - SBC_CP_EN_OFF = 0x00U, - SBC_CP_EN_ON -}; - -typedef enum -{ - SBC_CFG1_RESTART_FAILSAFE_2WDFAIL = 0x00U, - SBC_CFG1_RESTART_FAILSAFE_1WDFAIL -}; - - -/* -------------------------------- WD_CTRL ------------------------------------- */ - -typedef enum -{ - SBC_CHECKSUM_0 = 0x00U, - SBC_CHECKSUM_1 -}; - -typedef enum -{ - SBC_WD_STM_EN_0_ACTIVE_STOPMODE = 0x00U, - SBC_WD_STM_EN_0_NOTACTIVE_STOPMODE -}; - -typedef enum -{ - SBC_WD_WIN_TIMEOUT_WD = 0x00U, - SBC_WD_WIN_WINDOW_WD -}; - -typedef enum -{ - SBC_WD_EN_WK_BUS_NOSTART_AFTER_CANWAKE = 0x00U, - SBC_WD_EN_WK_BUS_START_LONGOPENWINDOW_CANWAKE -}; - -typedef enum -{ - SBC_WD_TIMER_10MS = 0x00U, - SBC_WD_TIMER_20MS, - SBC_WD_TIMER_50MS, - SBC_WD_TIMER_100MS, - SBC_WD_TIMER_200MS, - SBC_WD_TIMER_500MS, - SBC_WD_TIMER_1000MS, - SBC_WD_TIMER_10000MS -}; - - -/* -------------------------------- BUS_CTRL_0 ---------------------------------- */ - -typedef enum -{ - SBC_BUS_CTRL_0_CAN_WAKECAPABLE_NOSWK = 0x01U, - SBC_BUS_CTRL_0_CAN_RECEIVEONLY_NOSWK, - SBC_BUS_CTRL_0_CAN_NORMAL_NOSWK, - SBC_BUS_CTRL_0_CAN_OFF, - SBC_BUS_CTRL_0_CAN_WAKECAPABLE_SWK, - SBC_BUS_CTRL_0_CAN_RECEIVEONLY_SWK, - SBC_BUS_CTRL_0_CAN_NORMAL_SWK -}; - - -/* -------------------------------- WK_CTRL_0 ----------------------------------- */ - -typedef enum -{ - WK_CTRL_0_TIMER_WK_EN_WAKEUP_DISABLED = 0x00U, - WK_CTRL_0_TIMER_WK_EN_WAKESOURCE -}; - -typedef enum -{ - SBC_WD_STM_EN_1_WATCHDOG_STOPMPDE = 0x00U, - SBC_WD_STM_EN_1_NOWATCHDOG_STOPMODE -}; - - -/* -------------------------------- WK_CTRL_1 ----------------------------------- */ - -typedef enum -{ - SBC_INT_GLOBAL_WAKESOURCES_ONLY = 0x00U, - SBC_INT_GLOBAL_ALLINFORMATIONBITS -}; - -typedef enum -{ - SBC_WK_MEAS_WK_AS_WAKEUP = 0x00U, - SBC_WK_MEAS_WK_AS_VOLTAGESENSING -}; - -typedef enum -{ - SBC_WK_EN_WAKEUP_DISABLED = 0x00U, - SBC_WK_EN_WAKEUP_ENABLED -}; - - -/* -------------------------------- WK_PUPD_CTRL -------------------------------- */ - -typedef enum -{ - SBC_GPIO_WK_PUPD_NOPULLING = 0x00U, - SBC_GPIO_WK_PUPD_PULLDOWN, - SBC_GPIO_WK_PUPD_PULLUP, - SBC_GPIO_WK_PUPD_AUTOMATIC_PULLING -}; - -typedef enum -{ - SBC_WK_PUPD_NOPULLING = 0x00U, - SBC_WK_PUPD_PULLDOWN, - SBC_WK_PUPD_PULLUP, - SBC_WK_PUPD_AUTOMATIC_PULLING -}; - - -/* -------------------------------- BUS_CTRL_3 ---------------------------------- */ - -typedef enum -{ - SBC_CAN_FLASH_DISABLED = 0x00U, - SBC_CAN_FLASH_ENABLED -}; - - -/* -------------------------------- TIMER_CTRL ---------------------------------- */ - -typedef enum -{ - SBC_TIMER_ON_TIMEROFF_HSX_LOW = 0x00U, - SBC_TIMER_ON_100US, - SBC_TIMER_ON_300US, - SBC_TIMER_ON_1MS, - SBC_TIMER_ON_10MS, - SBC_TIMER_ON_20MS, - SBC_TIMER_ON_TIMEROFF_HSX_HIGH -}; - -typedef enum -{ - SBC_TIMER_PER_10MS = 0x00U, - SBC_TIMER_PER_20MS, - SBC_TIMER_PER_50MS, - SBC_TIMER_PER_100MS, - SBC_TIMER_PER_200MS, - SBC_TIMER_PER_500MS, - SBC_TIMER_PER_1S, - SBC_TIMER_PER_2S, - SBC_TIMER_PER_5S, - SBC_TIMER_PER_10S, - SBC_TIMER_PER_20S, - SBC_TIMER_PER_50S, - SBC_TIMER_PER_100S, - SBC_TIMER_PER_200S, - SBC_TIMER_PER_500S, - SBC_TIMER_PER_1000S -}; - - -/* -------------------------------- HW_CTRL_1 ----------------------------------- */ - -typedef enum -{ - SBC_RSTN_HYS_DEFAULT = 0x00U, - SBC_RSTN_HYS_HIGHEST_VRT -}; - -typedef enum -{ - SBC_TSD2_DEL_NO_WAIT_RELEASE_EXTENSION = 0x00U, - SBC_TSD2_DEL_64S_AFTER_16_TSD2_EVENTS -}; - -typedef enum -{ - SBC_RSTN_DEL_TRD1 = 0x00U, - SBC_RSTN_DEL_TRD2 -}; - -typedef enum -{ - SBC_CFG_LOCK_0_NOTLOCKED = 0x00U, - SBC_CFG_LOCK_0_LOCKED -}; - - -/* -------------------------------- HW_CTRL_2 ----------------------------------- */ - -typedef enum -{ - SBC_2MHZ_FREQ_1_8_MHZ = 0x00U, - SBC_2MHZ_FREQ_2_0_MHZ, - SBC_2MHZ_FREQ_2_2_MHZ, - SBC_2MHZ_FREQ_2_4_MHZ -}; - -typedef enum -{ - SBC_I_PEAK_TH_LOW = 0x00U, - SBC_I_PEAK_TH_HIGH -}; - -typedef enum -{ - SBC_SS_MOD_FR_DISABLED = 0x00U, - SBC_SS_MOD_FR_15_6KHZ, - SBC_SS_MOD_FR_31_2KHZ, - SBC_SS_MOD_FR_62_5KHZ -}; - -typedef enum -{ - SBC_CFG_LOCK_1_NOTLOCKED = 0x00U, - SBC_CFG_LOCK_1_LOCKED -}; - - -/* -------------------------------- GPIO_CTRL ----------------------------------- */ - -typedef enum -{ - SBC_GPIO_FO = 0x00U, - SBC_GPIO_HSS_TIMER = 0x03U, - SBC_GPIO_OFF, - SBC_GPIO_WAKE_INPUT, - SBC_GPIO_LSS_PWM, - SBC_GPIO_HSS_PWM -}; - - -/* -------------------------------- PWM_CTRL ------------------------------------ */ - -typedef enum -{ - SBC_PWM_DC_0 = 0x00U, - SBC_PWM_DC_10 = 0x19U, - SBC_PWM_DC_20 = 0x51U, - SBC_PWM_DC_30 = 0x4DU, - SBC_PWM_DC_40 = 0x66U, - SBC_PWM_DC_50 = 0x80U, - SBC_PWM_DC_60 = 0x99U, - SBC_PWM_DC_70 = 0xB3U, - SBC_PWM_DC_80 = 0xCCU, - SBC_PWM_DC_90 = 0xE6U, - SBC_PWM_DC_100 = 0xFFU -}; - - -/* -------------------------------- PWM_FREQ_CTRL ------------------------------- */ - -typedef enum -{ - SBC_PWM_FREQ_100HZ = 0x00U, - SBC_PWM_FREQ_200HZ, - SBC_PWM_FREQ_325HZ, - SBC_PWM_FREQ_400HZ -}; - - -/* -------------------------------- HW_CTRL_3 ----------------------------------- */ - -typedef enum -{ - SBC_TSD_THR_DEFAULT = 0x00U, - SBC_TSD_THR_HIGHER -}; - -typedef enum -{ - SBC_ICC1_LIM_ADJ_750MA = 0x00U, - SBC_ICC1_LIM_ADJ_1000MA, - SBC_ICC1_LIM_ADJ_1200MA, - SBC_ICC1_LIM_ADJ_1500MA -}; - - - - - - -/* ================================================================================ */ -/* ========== Selective Wake Control Registers Enumerations ============== */ -/* ================================================================================ */ - - - -/* -------------------------------- SWK_CTRL ------------------------------------ */ - -typedef enum -{ - SBC_OSC_CAL_DISABLED = 0x00U, - SBC_OSC_CAL_ENABLED -}; - -typedef enum -{ - SBC_TRIM_EN_LOCKED = 0x00U, - SBC_TRIM_EN_UNLOCKED = 0x03U -}; - -typedef enum -{ - SBC_CANTO_MASK_NOINT = 0x00U, - SBC_CANTO_MASK_INT_ON_TO -}; - -typedef enum -{ - SBC_CFG_VAL_NOTVALID = 0x00U, - SBC_CFG_VAL_VALID -}; - - -/* -------------------------------- SWK_ID0_CTRL --------------------------------- */ - -typedef enum -{ - SBC_RTR_NORMAL_DATA_FRAME = 0x00U, - SBC_RTR_REMOTE_TRANSMIT_REQUEST -}; - -typedef enum -{ - SBC_IDE_STANDARD = 0x00U, - SBC_IDE_EXTENDED -}; - - -/* -------------------------------- SWK_DLC_CTRL --------------------------------- */ - -typedef enum -{ - SBC_DLC_0BYTES = 0x00U, - SBC_DLC_1BYTES, - SBC_DLC_2BYTES, - SBC_DLC_3BYTES, - SBC_DLC_4BYTES, - SBC_DLC_5BYTES, - SBC_DLC_6BYTES, - SBC_DLC_7BYTES, - SBC_DLC_8BYTES -}; - - -/* -------------------------------- SWK_CAN_FD_CTRL ------------------------------ */ - -typedef enum -{ - SBC_DIS_ERR_CNT_ENABLED = 0x00U, - SBC_DIS_ERR_CNT_DISABLED -}; - -typedef enum -{ - SBC_RX_FILT_BYP_NOTBYPASSED = 0x00U, - SBC_RX_FILT_BYP_BYPASSED -}; - -typedef enum -{ - SBC_FD_FILTER_50NS = 0x00U, - SBC_FD_FILTER_100NS, - SBC_FD_FILTER_150NS, - SBC_FD_FILTER_200NS, - SBC_FD_FILTER_250NS, - SBC_FD_FILTER_300NS, - SBC_FD_FILTER_350NS, - SBC_FD_FILTER_700NS -}; - -typedef enum -{ - SBC_CAN_FD_EN_DISABLED = 0x00U, - SBC_CAN_FD_EN_ENABLED -}; - - -/* -------------------------------- SWK_OPT_CTRL --------------------------------- */ - -typedef enum -{ - SBC_RX_WK_SEL_LOWPOWER = 0x00U, - SBC_RX_WK_SEL_STANDARD -}; - - -/* -------------------------------- SWK_CDR_CTRL1 -------------------------------- */ - -typedef enum -{ - SBC_SEL_FILT_TC8 = 0x00U, - SBC_SEL_FILT_TC16, - SBC_SEL_FILT_TC32, - SBC_SEL_FILT_ADAPT -}; - -typedef enum -{ - SBC_CDR_EN_DISABLED = 0x00U, - SBC_CDR_EN_ENABLED -}; - - -/* -------------------------------- SWK_CDR_CTRL2 -------------------------------- */ - -typedef enum -{ - SBC_SEL_OSC_CLK_80MHZ = 0x00U, - SBC_SEL_OSC_CLK_40MHZ, - SBC_SEL_OSC_CLK_20MHZ, - SBC_SEL_OSC_CLK_10MHZ -}; - - - - - - -/* ================================================================================ */ -/* ========== General Status Information Registers Enumerations ========== */ -/* ================================================================================ */ - - - -/* -------------------------------- SUP_STAT_1 ---------------------------------- */ - -typedef enum -{ - SBC_VS_UV_NOEVENT = 0x00U, - SBC_VS_UV_EVENT -}; - -typedef enum -{ - SBC_VS_OV_NOEVENT = 0x00U, - SBC_VS_OV_EVENT -}; - -typedef enum -{ - SBC_VCC1_OV_NOEVENT = 0x00U, - SBC_VCC1_OV_EVENT -}; - -typedef enum -{ - SBC_VCC1_UV_PREWARN_NOEVENT = 0x00U, - SBC_VCC1_UV_PREWARN_EVENT -}; - - -/* -------------------------------- SUP_STAT_0 ----------------------------------- */ - -typedef enum -{ - SBC_POR_NOEVENT = 0x00U, - SBC_POR_EVENT -}; - -typedef enum -{ - SBC_VCC2_OT_NOEVENT = 0x00U, - SBC_VCC2_OT_EVENT -}; - -typedef enum -{ - SBC_VCC2_UV_NOEVENT = 0x00U, - SBC_VCC2_UV_EVENT -}; - -typedef enum -{ - SBC_VCC1_SC_NOEVENT = 0x00U, - SBC_VCC1_SC_TO_GND_EVENT -}; - -typedef enum -{ - SBC_VCC1_UV_NOEVENT = 0x00U, - SBC_VCC1_UV_EVENT -}; - - -/* -------------------------------- THERM_STAT ----------------------------------- */ - -typedef enum -{ - SBC_TSD2_SAFE_NOSAFESTATE = 0x00U, - SBC_TSD2_SAFE_SAFESTATE_DETECTED -}; - -typedef enum -{ - SBC_TSD2_NOEVENT = 0x00U, - SBC_TSD2_EVENT -}; - -typedef enum -{ - SBC_TSD1_NOEVENT = 0x00U, - SBC_TSD1_EVENT -}; - -typedef enum -{ - SBC_TPW_NOEVENT = 0x00U, - SBC_TPW_EVENT -}; - - -/* -------------------------------- DEV_STAT ------------------------------------- */ - -typedef enum -{ - SBC_DEV_STAT_CLEARED = 0x00U, - SBC_DEV_STAT_RESTART_AFTER_FAIL, - SBC_DEV_STAT_SLEEP_MODE -}; - -typedef enum -{ - SBC_WD_FAIL_NOFAIL = 0x00U, - SBC_WD_FAIL_1FAIL, - SBC_WD_FAIL_2FAIL -}; - -typedef enum -{ - SBC_SPI_FAIL_NOEVENT = 0x00U, - SBC_SPI_FAIL_EVENT -}; - -typedef enum -{ - SBC_FAILURE_NOEVENT = 0x00U, - SBC_FAILURE_EVENT -}; - - -/* -------------------------------- BUS_STAT ------------------------------------- */ - -typedef enum -{ - SBC_CANTO_NORMAL = 0x00U, - SBC_CANTO_TIMEOUT -}; - -typedef enum -{ - SBC_SYSERR_NOEVENT = 0x00U, - SBC_SYSERR_DETECTED -}; - -typedef enum -{ - SBC_CAN_FAIL_NO_FAIL = 0x00U, - SBC_CAN_FAIL_TSD, - SBC_CAN_FAIL_TXD_DOM_TO, - SBC_CAN_FAIL_BUS_DOM_TO -}; - -typedef enum -{ - SBC_VCAN_UV_NOEVENT = 0x00U, - SBC_VCAN_UV_EVENT -}; - - -/* -------------------------------- WK_STAT_0 ------------------------------------ */ - -typedef enum -{ - SBC_CAN_WU_NOEVENT = 0x00U, - SBC_CAN_WU_EVENT -}; - -typedef enum -{ - SBC_TIMER_WU_NOEVENT = 0x00U, - SBC_TIMER_WU_EVENT -}; - -typedef enum -{ - SBC_WK_WU_NOEVENT = 0x00U, - SBC_WK_WU_EVENT -}; - - -/* -------------------------------- WK_STAT_1 ------------------------------------ */ - -typedef enum -{ - SBC_GPIO_WK_WU_NOEVENT = 0x00U, - SBC_GPIO_WK_WU_EVENT -}; - - -/* -------------------------------- WK_LVL_STAT ---------------------------------- */ - -typedef enum -{ - SBC_DEV_LVL_NORMAL = 0x00U, - SBC_DEV_LVL_DEVELOPMENT_MODE -}; - -typedef enum -{ - SBC_CFG0_STATE_CONFIG_2_4 = 0x00U, - SBC_CFG0_STATE_CONFIG_1_3 -}; - -typedef enum -{ - SBC_GPIO_LVL_LOW = 0x00U, - SBC_GPIO_LVL_HIGH -}; - -typedef enum -{ - SBC_WK_LVL_LOW = 0x00U, - SBC_WK_LVL_HIGH -}; - - -/* -------------------------------- GPIO_OC_STAT --------------------------------- */ - -typedef enum -{ - SBC_GPIO_OC_NOEVENT = 0x00U, - SBC_GPIO_OC_EVENT -}; - - -/* -------------------------------- GPIO_OL_STAT --------------------------------- */ - -typedef enum -{ - SBC_GPIO_OL_NOEVENT = 0x00U, - SBC_GPIO_OL_EVENT -}; - - - - - - -/* ================================================================================ */ -/* ============= Selective Wake Status Registers Enumerations ============ */ -/* ================================================================================ */ - - - -/* -------------------------------- SWK_STAT ------------------------------------ */ - -typedef enum -{ - SBC_SYNC_NOT_SYNCHRONOUS = 0x00U, - SBC_SYNC_VALID_FRAME_RECEIVED -}; - -typedef enum -{ - SBC_CANSIL_NOT_EXCEEDED = 0x00U, - SBC_CANSIL_EXCEEDED -}; - -typedef enum -{ - SBC_SWK_SET_SWK_NOT_ACTIVE = 0x00U, - SBC_SWK_SET_SWK_ACTIVE -}; - -typedef enum -{ - SBC_WUP_NO_WUP = 0x00U, - SBC_WUP_DETECTED -}; - -typedef enum -{ - SBC_WUF_NO_WUF = 0x00U, - SBC_WUF_DETECTED -}; - - -/* -------------------------------- SWK_ECNT_STAT ------------------------------ */ - -typedef enum -{ - SBC_ECNT_NOEVENT = 0x00U, - SBC_ECNT_31_FRAME_ERRORS = 0x1FU, - SBC_ECNT_ERROR_OVERFLOW = 0x20U -}; - - -/* ================================================================================ */ -/* ======== Family and Product Information Registers Enumerations ======== */ -/* ================================================================================ */ - - - -/* -------------------------------- FAM_PROD_STAT ------------------------------- */ - -typedef enum -{ - SBC_FAM_DRIVER = 0x01U, - SBC_FAM_DCDC, - SBC_FAM_MIDRANGE, - SBC_FAM_MULTICAN, - SBC_FAM_LITE, - SBC_FAM_MIDRANGEPLUS = 0x07U -}; - -typedef enum -{ - SBC_PROD_TLE9461 = 0x06U, - SBC_PROD_TLE9461V33, - SBC_PROD_TLE9471 = 0x0EU, - SBC_PROD_TLE9471V33 -}; - - -#endif /* TLE94x1_DEFINES_H */ diff --git a/cva_bootloader_m0118/src/TLE9461/TLE94x1_ISR.h b/cva_bootloader_m0118/src/TLE9461/TLE94x1_ISR.h deleted file mode 100644 index b40bbbe..0000000 --- a/cva_bootloader_m0118/src/TLE9461/TLE94x1_ISR.h +++ /dev/null @@ -1,127 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2019, Infineon Technologies AG - * - * - * Distributed under the Boost Software License, Version 1.0. - * - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - *********************************************************************************************************************/ - - -/****************************************************************************************************//** - * @file TLE94x1_ISR.h - * - * @brief Declaration file for ISR-Vectors and ISR related functions - * - * @version V1.0.0 - * @date 15. April 2019 - * @author Markus Noll / markus.noll@infineon.com - * @author Yannek Micha Rixen / Yannek.Rixen@infineon.com - *******************************************************************************************************/ - - - - -#ifndef TLE94x1_ISR_H -#define TLE94x1_ISR_H - - - - - - - -/* ================================================================================ */ -/* ============================ HEADER FILES ================================== */ -/* ================================================================================ */ - -#include "TLE94x1_DEFINES.h" - - - - - - - - -/* ================================================================================ */ -/* ================================ MACROS ==================================== */ -/* ================================================================================ */ - - -/** - * @def SBC_ISR_VECTOR - * - * @brief Vector defining the handling of interrupts. - * - * Vectors of this type have to be registered by the SBC_Register_Callback method. - */ -#define SBC_ISR_VECTOR(REG,MASK,POS,COMPARE) ((((uint32_t)REG) << 24) | (((uint32_t)MASK) << 16) | (((uint32_t)POS) << 8) | ((uint32_t)COMPARE)) - - - - - - -/* ================================================================================ */ -/* ======================= General Interrupt Defines ========================== */ -/* ================================================================================ */ - - - -/* Interrupts based on WK_STAT_0 and WK_STAT_1 register are always available */ -#define SBC_ISR_CAN_WU SBC_ISR_VECTOR(SBC_WK_STAT_0, SBC_WK_STAT_0_CAN_WU_Msk, SBC_WK_STAT_0_CAN_WU_Pos, SBC_CAN_WU_EVENT) -#define SBC_ISR_TIMER_WU SBC_ISR_VECTOR(SBC_WK_STAT_0, SBC_WK_STAT_0_TIMER_WU_Msk, SBC_WK_STAT_0_TIMER_WU_Pos, SBC_TIMER_WU_EVENT) -#define SBC_ISR_WK_WU SBC_ISR_VECTOR(SBC_WK_STAT_0, SBC_WK_STAT_0_WK_WU_Msk, SBC_WK_STAT_0_WK_WU_Pos, SBC_WK_WU_EVENT) -#define SBC_ISR_GPIO_WK_WU SBC_ISR_VECTOR(SBC_WK_STAT_1, SBC_WK_STAT_1_GPIO_WK_WU_Msk, SBC_WK_STAT_1_GPIO_WK_WU_Pos, SBC_GPIO_WK_WU_EVENT) - - -/* Following interrupts only usable if INT_GLOBAL bit is set to '1' */ -#define SBC_ISR_VS_UV SBC_ISR_VECTOR(SBC_SUP_STAT_1, SBC_SUP_STAT_1_VS_UV_Msk, SBC_SUP_STAT_1_VS_UV_Pos, SBC_VS_UV_EVENT) -#define SBC_ISR_VS_OV SBC_ISR_VECTOR(SBC_SUP_STAT_1, SBC_SUP_STAT_1_VS_OV_Msk, SBC_SUP_STAT_1_VS_OV_Pos, SBC_VS_OV_EVENT) -#define SBC_ISR_VCC1_OV SBC_ISR_VECTOR(SBC_SUP_STAT_1, SBC_SUP_STAT_1_VCC1_OV_Msk, SBC_SUP_STAT_1_VCC1_OV_Pos, SBC_VCC1_OV_EVENT) -#define SBC_ISR_VCC1_UV_PREWARN SBC_ISR_VECTOR(SBC_SUP_STAT_1, SBC_SUP_STAT_1_VCC1_WARN_Msk, SBC_SUP_STAT_1_VCC1_WARN_Pos, SBC_VCC1_UV_PREWARN_EVENT) -#define SBC_ISR_VCC2_OT SBC_ISR_VECTOR(SBC_SUP_STAT_0, SBC_SUP_STAT_0_VCC2_OT_Msk, SBC_SUP_STAT_0_VCC2_OT_Pos, SBC_VCC2_OT_EVENT) -#define SBC_ISR_VCC2_UV SBC_ISR_VECTOR(SBC_SUP_STAT_0, SBC_SUP_STAT_0_VCC2_UV_Msk, SBC_SUP_STAT_0_VCC2_UV_Pos, SBC_VCC2_UV_EVENT) -#define SBC_ISR_VCC1_UV SBC_ISR_VECTOR(SBC_SUP_STAT_0, SBC_SUP_STAT_0_VCC1_UV_Msk, SBC_SUP_STAT_0_VCC1_UV_Pos, SBC_VCC1_UV_EVENT) -#define SBC_ISR_TSD2_SAFESTATE SBC_ISR_VECTOR(SBC_THERM_STAT, SBC_THERM_STAT_TSD2_SAFE_Msk, SBC_THERM_STAT_TSD2_SAFE_Pos, SBC_TSD2_SAFE_SAFESTATE_DETECTED) -#define SBC_ISR_TSD1 SBC_ISR_VECTOR(SBC_THERM_STAT, SBC_THERM_STAT_TSD1_Msk, SBC_THERM_STAT_TSD1_Pos, SBC_TSD1_EVENT) -#define SBC_ISR_TPW SBC_ISR_VECTOR(SBC_THERM_STAT, SBC_THERM_STAT_TPW_Msk, SBC_THERM_STAT_TPW_Pos, SBC_TPW_EVENT) -#define SBC_ISR_RESTART_AFTER_FAIL SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_DEV_STAT_Msk, SBC_DEV_STAT_DEV_STAT_Pos, SBC_DEV_STAT_RESTART_AFTER_FAIL) -#define SBC_ISR_FROM_SLEEPMODE SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_DEV_STAT_Msk, SBC_DEV_STAT_DEV_STAT_Pos, SBC_DEV_STAT_SLEEP_MODE) -#define SBC_ISR_WD_FAIL_1 SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_WD_FAIL_Msk, SBC_DEV_STAT_WD_FAIL_Pos, SBC_WD_FAIL_1FAIL) -#define SBC_ISR_WD_FAIL_2 SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_WD_FAIL_Msk, SBC_DEV_STAT_WD_FAIL_Pos, SBC_WD_FAIL_2FAIL) -#define SBC_ISR_FAILURE SBC_ISR_VECTOR(SBC_DEV_STAT, SBC_DEV_STAT_FAILURE_Msk, SBC_DEV_STAT_FAILURE_Pos, SBC_FAILURE_EVENT) -#define SBC_ISR_CAN_TSD SBC_ISR_VECTOR(SBC_BUS_STAT, SBC_BUS_STAT_CAN_FAIL_Msk, SBC_BUS_STAT_CAN_FAIL_Pos, SBC_CAN_FAIL_TSD) -#define SBC_ISR_CAN_TXD_DOM_TO SBC_ISR_VECTOR(SBC_BUS_STAT, SBC_BUS_STAT_CAN_FAIL_Msk, SBC_BUS_STAT_CAN_FAIL_Pos, SBC_CAN_FAIL_TXD_DOM_TO) -#define SBC_ISR_CAN_BUS_DOM_TO SBC_ISR_VECTOR(SBC_BUS_STAT, SBC_BUS_STAT_CAN_FAIL_Msk, SBC_BUS_STAT_CAN_FAIL_Pos, SBC_CAN_FAIL_BUS_DOM_TO) -#define SBC_ISR_VCAN_UV SBC_ISR_VECTOR(SBC_BUS_STAT, SBC_BUS_STAT_VCAN_UV_Msk, SBC_BUS_STAT_VCAN_UV_Pos, SBC_VCAN_UV_EVENT) -#define SBC_ISR_GPIO_OC SBC_ISR_VECTOR(SBC_GPIO_OC_STAT, SBC_GPIO_OC_STAT_GPIO_OC_Msk, SBC_GPIO_OC_STAT_GPIO_OC_Pos, SBC_GPIO_OC_EVENT) -#define SBC_ISR_GPIO_OL SBC_ISR_VECTOR(SBC_GPIO_OL_STAT, SBC_GPIO_OL_STAT_GPIO_OL_Msk, SBC_GPIO_OL_STAT_GPIO_OL_Pos, SBC_GPIO_OL_EVENT) - - -#endif /*TLE94x1_ISR_H*/ diff --git a/cva_bootloader_m0118/src/TLE9461/TLE94x1_SPI.c b/cva_bootloader_m0118/src/TLE9461/TLE94x1_SPI.c deleted file mode 100644 index b90577c..0000000 --- a/cva_bootloader_m0118/src/TLE9461/TLE94x1_SPI.c +++ /dev/null @@ -1,156 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2019, Infineon Technologies AG - * - * - * Distributed under the Boost Software License, Version 1.0. - * - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - *********************************************************************************************************************/ - - -/****************************************************************************************************//** - * @file TLE94x1_SPI.c - * - * @brief Implementation of all SPI related functions - * - * @version V1.0.0 - * @date 15. April 2019 - * @author Markus Noll / markus.noll@infineon.com - * @author Yannek Micha Rixen / Yannek.Rixen@infineon.com - *******************************************************************************************************/ - - - - -/* ================================================================================ */ -/* ============================ HEADER FILES ================================ */ -/* ================================================================================ */ - -#include "TLE94x1_SPI.h" -#include "mcu.h" - -void SPI_PortInit(void); - - - - -/* ================================================================================ */ -/* ======================= SPI communication functions ====================== */ -/* ================================================================================ */ - - -uint8_t spitxbuf[10],spirxbuf[10]; -extern McuType mcu; -uint8_t SBC_SPI_INIT(void) { - SpiDrv_InitCfgType masterCfg; - - SPI_PortInit(); - - SpiDrv_GetDefaultConfig(&masterCfg); - masterCfg.basicParameters.isMasterNode = true; - masterCfg.basicParameters.baudRate = 1000000ul; - masterCfg.basicParameters.pcsSelection = 1; - //masterCfg.basicParameters.clockPolarity = SPIDRV_CLK_POLARITY_IDLE_IN_HIGH; - masterCfg.basicParameters.clockPhase = SPIDRV_CLK_PHASE_DATA_SAMPLE_ON_TRAILING_EDGE; - - while(ClockDrv_GetFreq(&mcu.clockDrv, CLOCKDRV_SPI0, &masterCfg.basicParameters.busClockFreq) == false) - { - ; - } - SpiDrv_SetConfig(&mcu.spiDrv0, &masterCfg); - - SpiDrv_SetRxFifoWaterMask(&mcu.spiDrv0, 0); - //SpiDrv_SetIsrConfig(&mcu.spiDrv0, SPIDRV_ISR_SRC_RX_DATA, true); - - /* Enable the SPI interrupts */ - return 0; -} - - - -uint16_t SBC_SPI_TRANSFER16(uint8_t Upper, uint8_t Lower) { - uint16_t ret; - //LPSPI_DRV_SetPcs(LPSPICOM1,LPSPI_PCS0,LPSPI_ACTIVE_LOW); - spitxbuf[0] = Upper; - spitxbuf[1] = Lower; - - SpiDrv_MasterSyncTransfer(&mcu.spiDrv0,SPIDRV_FRAME_SIZE_BIT_TYPE_BYTE,2,spitxbuf,spirxbuf); - //LPSPI_DRV_MasterTransferBlocking(LPSPICOM1,spitxbuf,spirxbuf,2,10); - ret = spirxbuf[0]; - ret <<= 8; - ret |= spirxbuf[1]; - //LPSPI_DRV_SetPcs(LPSPICOM1,LPSPI_PCS0,LPSPI_ACTIVE_HIGH); - return ret; -} - - -/********************CVA SPI DRV**********************/ - -void SPI0_Handler(void) -{ - if(SpiDrv_GetStatus(&mcu.spiDrv0, SPIDRV_STATUS_RX_DATA) == true && SpiDrv_GetIsrConfig(&mcu.spiDrv0, SPIDRV_ISR_SRC_RX_DATA) == true) - { - //spi0IrqCnt++; - //uint8_t len = SpiDrv_AsyncReceive(&mcu.spiDrv0, (void *)masterRxBuff, true); - } -} - -void SPI_PortInit(void) -{ - /* SPI CS */ - PinsDrv_SetMuxModeSel(&mcu.ptb, 5, PINSDRV_MUX_ALT3); - /* Strength driver */ - PortReg_SetPcrDrvStr(mcu.ptb.port, 5, 1); - /* fast slew rate */ - PortReg_SetPcrSr(mcu.ptb.port, 5, 1); - - /* SPI CLK */ - PinsDrv_SetMuxModeSel(&mcu.ptb, 2, PINSDRV_MUX_ALT3); - /* Strength driver */ - PortReg_SetPcrDrvStr(mcu.ptb.port, 2, 1); - /* fast slew rate */ - PortReg_SetPcrSr(mcu.ptb.port, 2, 1); - - /* SPI SIN */ - PinsDrv_SetMuxModeSel(&mcu.ptb, 4, PINSDRV_MUX_ALT3); - /* Strength driver */ - PortReg_SetPcrDrvStr(mcu.ptb.port, 4, 1); - /* fast slew rate */ - PortReg_SetPcrSr(mcu.ptb.port, 4, 1); - - /* SPI SOUT */ - PinsDrv_SetMuxModeSel(&mcu.ptb, 3, PINSDRV_MUX_ALT3); - /* Strength driver */ - PortReg_SetPcrDrvStr(mcu.ptb.port, 3, 1); - /* fast slew rate */ - PortReg_SetPcrSr(mcu.ptb.port, 3, 1); -} - -void SPI_TEST_TASK(void) -{ - -} \ No newline at end of file diff --git a/cva_bootloader_m0118/src/TLE9461/TLE94x1_SPI.h b/cva_bootloader_m0118/src/TLE9461/TLE94x1_SPI.h deleted file mode 100644 index abf88cc..0000000 --- a/cva_bootloader_m0118/src/TLE9461/TLE94x1_SPI.h +++ /dev/null @@ -1,95 +0,0 @@ -/********************************************************************************************************************* - * Copyright (c) 2019, Infineon Technologies AG - * - * - * Distributed under the Boost Software License, Version 1.0. - * - * - * Boost Software License - Version 1.0 - August 17th, 2003 - * - * Permission is hereby granted, free of charge, to any person or organization - * obtaining a copy of the software and accompanying documentation covered by - * this license (the "Software") to use, reproduce, display, distribute, - * execute, and transmit the Software, and to prepare derivative works of the - * Software, and to permit third-parties to whom the Software is furnished to - * do so, all subject to the following: - * - * The copyright notices in the Software and this entire statement, including - * the above license grant, this restriction and the following disclaimer, - * must be included in all copies of the Software, in whole or in part, and - * all derivative works of the Software, unless such copies or derivative - * works are solely in the form of machine-executable object code generated by - * a source language processor. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT - * SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE - * FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - *********************************************************************************************************************/ - - -/****************************************************************************************************//** - * @file TLE94x1_SPI.h - * - * @brief Declaration file for TLE94x1 SBC family device SPI functions - * - * @version V1.0.0 - * @date 15. April 2019 - * @author Markus Noll / markus.noll@infineon.com - * @author Yannek Micha Rixen / Yannek.Rixen@infineon.com - *******************************************************************************************************/ - - - - -#ifndef TLE94x1_SPI_H -#define TLE94x1_SPI_H - - - - - - -/* ================================================================================ */ -/* ============================ HEADER FILES ================================ */ -/* ================================================================================ */ - -#include - - - -/* ================================================================================ */ -/* ============================= SPI Functions ============================== */ -/* ================================================================================ */ - -/** - * @brief IMPORTANT! THIS METHOD HAS TO BE DEFINED BY THE USER - * - * The function has to initialze the SPI of the uC and will be called once during SBC_Init(). - * In case, the SPI hardware is already initialized by some other code before, it can be left blank. - * - * @retval Method has to return 0 if initialization was successful. - */ -uint8_t SBC_SPI_INIT(void); - -/** - * @brief IMPORTANT! THIS METHOD HAS TO BE DEFINED BY THE USER - * - * The function will be called by the library everytime when a SPI communication is needed. - * The function proceeds a bidirectional 16-bit transfer to/from the SBC . - * As some UCs only supports 8-Bit transfers, the input arguments are split in two 8-bit arguments. - * For further implementation details have a look at datasheet chapter 13.1 or at the Arduino-examples. - * - * @param Upper The first 8 bit to transmit to the SBC. - * @param Lower The second 8 bit to transmit to the SBC. - * @retval The function will return all 16 bits received from the SBC. - * Bit[15:8] are the first 8 bits received (Status-Information-Field). - * Bit[7:0] is the data-field transmitted of the SBC. - */ -uint16_t SBC_SPI_TRANSFER16(uint8_t Upper, uint8_t Lower); - -#endif /* TLE94x1_SPI_H */ diff --git a/cva_bootloader_m0118/src/bootloader/bootloader.c b/cva_bootloader_m0118/src/bootloader/bootloader.c index fafa7c0..4ef2c11 100644 --- a/cva_bootloader_m0118/src/bootloader/bootloader.c +++ b/cva_bootloader_m0118/src/bootloader/bootloader.c @@ -25,7 +25,6 @@ #include "uds.h" #include "uds_user.h" #include "mcu.h" -#include "TLE94x1.h" #include "SEGGER_RTT.h" /******************************************************************************* @@ -62,7 +61,7 @@ __root const Bootloade_CfgInfoType sBootloader_Version = { .BLVersion = "BL0101", .bootBuildDate = __DATE__, .bootBuildTime = __TIME__, - .ECUName = "RP-77B", + .ECUName = "WK-K86", }; static Bootloader_CbType sBootloader_Cb; @@ -477,7 +476,7 @@ static void Bootloader_Reset(void) static void Bootloader_HardReset(void) { /* TODO */ - SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_RESET, NULL); + //SBC_Write_RegField(SBC_M_S_CTRL, SBC_M_S_CTRL_MODE_Msk, SBC_M_S_CTRL_MODE_Pos, SBC_MODE_RESET, NULL); } /*! \brief pgm positive respose to eol @@ -1280,15 +1279,16 @@ void Bootloader_TimingProcess(uint8_t periodms) if(sBootloader_Cb.resetReqEn == true) { sBootloader_Cb.resetReqEn = false; + /*//SBC RESET if (sBootloader_Cb.resetReqMode == 1) { Bootloader_HardReset(); - Bootloader_Reset(); + } else { Bootloader_Reset(); - } - + }*/ + Bootloader_Reset(); } } diff --git a/cva_bootloader_m0118/src/main.c b/cva_bootloader_m0118/src/main.c index 63c8fd0..3fc9b6b 100644 --- a/cva_bootloader_m0118/src/main.c +++ b/cva_bootloader_m0118/src/main.c @@ -28,7 +28,7 @@ #include "fls.h" #include "uds_user.h" #include "SEGGER_RTT.h" -#include "TLE94x1.h" + /******************************************************************************* * the defines @@ -305,23 +305,6 @@ void BootReqInit(void) clockConfig.div = 1; ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PLL_DIV, &clockConfig); - clockConfig.gating = true; - clockConfig.source = CLOCKDRV_PLL; - clockConfig.div = 2; - ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PLL_DIV, &clockConfig); - - /* Setup the SPI clock */ - clockConfig.gating = true; - clockConfig.source = CLOCKDRV_PLL_DIV; - ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_SPI0, &clockConfig); - - uint32_t tTcr = SpiReg_GetTcr((const SpiRegType *)&mcu.spiDrv0.reg); - SpiDrv_SetPrescaler(&tTcr,0x02); - - SBC_SPI_INIT(); - - - SBC_Init(); } uint32_t rollingcounter; @@ -347,8 +330,6 @@ int main(void) - - /* Enable the clock for all port peripheral */ clockConfig.gating = true; clockConfig.div = 1; @@ -358,12 +339,13 @@ int main(void) ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTD, &clockConfig); ClockDrv_ConfigureClock(&mcu.clockDrv, CLOCKDRV_PORTE, &clockConfig); + + //STB /* set PTC1 MUX as GPIO */ - PinsDrv_SetMuxModeSel(&mcu.ptd, 1, PINSDRV_MUX_AS_GPIO); + PinsDrv_SetMuxModeSel(&mcu.ptc, 9, PINSDRV_MUX_AS_GPIO); /* set PTC1 as GPIO output */ - PinsDrv_SetPinDirection(&mcu.ptd, 1, 0); - PinsDrv_SetPullSel(&mcu.ptd,1,PINSDRV_INTERNAL_PULL_UP); - + PinsDrv_SetPinDirection(&mcu.ptc, 9, 1); + PinsDrv_WritePin(&mcu.ptc, 9, 0); /* get CAN controller default configuration */ FlexCanBoot_Init(); @@ -393,11 +375,6 @@ int main(void) if (gSystick1msCnt % 10 == 0) { - //SEGGER_RTT_printf(0,"-----SBC_WD_Trigger-----\n"); - if (BootReqFlag == 1) - { - SBC_WD_Trigger(); - } } @@ -406,21 +383,8 @@ int main(void) { gSystick1msCnt = 0; //TxTestMsg(testdata); - - //SEGGER_RTT_printf(0,"-boot running-\n"); - uint8_t ret = SBC_Read_Command(SBC_M_S_CTRL); - SEGGER_RTT_printf(0,"%04d : M_S_CTRL = 0x%x\n",rollingcounter++,ret); - } - if (BootReqFlag == 0) - { - BootReqDelay++; - if (BootReqDelay > 10) - { - BootReqFlag = 1; - BootReqInit(); - } - } +