247 lines
9.9 KiB
C
247 lines
9.9 KiB
C
/**
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* @copyright 2022 indie Semiconductor
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*
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* This file is proprietary to indie Semiconductor.
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* All rights reserved. Reproduction or distribution, in whole
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* or in part, is forbidden except by express written permission
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* of indie Semiconductor.
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*
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* @file sar_ctrl_sfr.h
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*/
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#ifndef SAR_CTRL_SFR_H__
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#define SAR_CTRL_SFR_H__
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#include <stdint.h>
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/* ------- Start of section using anonymous unions and disabling warnings ------- */
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#if defined (__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined (__ICCARM__)
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#pragma language=extended
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wc11-extensions"
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#pragma clang diagnostic ignored "-Wreserved-id-macro"
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning 586
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/**
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* @brief A structure to represent Special Function Registers for SAR_CTRL.
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*/
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typedef struct {
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uint16_t DATA; /* +0x000 */
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uint16_t _RESERVED; /* +0x002 */
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}SAR_Data_t;
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typedef struct {
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SAR_Data_t DATA[10]; /* +0x000 */
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union {
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struct {
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uint8_t : 7; /* (reserved) */
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uint8_t ROUND : 1; /*!< ADC round enable */
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uint8_t TRIGSRC : 8; /*!< SAR Converion Trigger Source Selects */
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uint8_t PWMAUXTRIGSEL : 4; /*!< SAR Converion Trigger Selects of PWMAUX */
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uint8_t PWMAUXCHSEL : 3; /*!< PWMAUX Trigger Channel Selects */
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uint8_t TRIGSEL : 1; /*!< SAR Trigger Signal Selects */
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uint8_t TRIGDLY : 8; /*!< trigger delay */
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};
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uint32_t WORD;
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} SARCFG; /* +0x028 */
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union {
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struct {
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uint8_t ADCSELVINVCMEXT : 1; /*!< Select External Inputs to ADC */
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uint8_t : 6; /* (reserved) */
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uint8_t SARAFEEN : 1; /*!< ADC AFE Enable */
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uint8_t SARPREAMPEN : 8; /*!< adc pre-amp enable */
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uint16_t : 16; /* (reserved) */
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};
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uint32_t WORD;
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} AFECTRL; /* +0x02C */
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union {
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struct {
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uint8_t SARENAREQ : 8; /*!< SAR ADC Enable */
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uint8_t : 2; /* (reserved) */
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uint8_t DIGRESET : 1; /*!< SAR Digital Part Reset */
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uint8_t : 5; /* (reserved) */
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uint8_t CONVERT : 1; /*!< ADC START/STATUS Register */
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uint8_t : 1; /* (reserved) */
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uint8_t CONT : 1; /*!< Continuous Conversion Enable */
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uint8_t : 5; /* (reserved) */
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} SARCTRL; /* +0x030 */
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union {
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struct {
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uint8_t SEQCNT : 4; /*!< Channel Sequence count */
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uint8_t : 1; /* (reserved) */
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uint32_t CH1SEL : 5; /*!< Channel1 Selection !!misaligned!! */
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uint8_t CH2SEL : 5; /*!< Channel2 Selection */
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uint8_t : 1; /* (reserved) */
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uint8_t CH3SEL : 8; /*!< Channel3 Selection */
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uint8_t CH4SEL : 5; /*!< Channel4 Selection */
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uint8_t : 2; /* (reserved) */
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uint8_t TESTBATTERYGAINCHOOSE : 1; /*!< VBAT Gain Select */
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};
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uint32_t WORD;
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} ADCCHCONF; /* +0x034 */
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union {
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struct {
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uint8_t CH5SEL : 5; /*!< Channel5 Selection */
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uint32_t CH6SEL : 5; /*!< Channel6 Selection !!misaligned!! */
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uint8_t CH7SEL : 5; /*!< Channel7 Selection */
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uint32_t CH8SEL : 5; /*!< Channel8 Selection !!misaligned!! */
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uint32_t CH9SEL : 5; /*!< Channel9 Selection !!misaligned!! */
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uint8_t CH10SEL : 5; /*!< Channel10 Selection */
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uint8_t : 2; /* (reserved) */
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};
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uint32_t WORD;
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} ADCCHSELR; /* +0x038 */
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union {
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struct {
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uint8_t SAR_INPUT_MODE_CH1 : 2; /*!< CH1 AFE Input Modes */
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uint8_t SAR_INPUT_MODE_CH2 : 2; /*!< CH2 AFE Input Modes */
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uint8_t SAR_INPUT_MODE_CH3 : 2; /*!< CH3 AFE Input Modes */
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uint8_t SAR_INPUT_MODE_CH4 : 2; /*!< CH4 AFE Input Modes */
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uint8_t SAR_INPUT_MODE_CH5 : 2; /*!< CH5 AFE Input Modes */
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uint8_t SAR_INPUT_MODE_CH6 : 2; /*!< CH6 AFE Input Modes */
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uint8_t SAR_INPUT_MODE_CH7 : 2; /*!< CH7 AFE Input Modes */
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uint8_t SAR_INPUT_MODE_CH8 : 2; /*!< CH8 AFE Input Modes */
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uint8_t SAR_INPUT_MODE_CH9 : 2; /*!< CH9 AFE Input Modes */
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uint8_t SAR_INPUT_MODE_CH10 : 2; /*!< CH10 AFE Input Modes */
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uint8_t SARINPUTGAINCH1 : 1; /*!< ADC Channel1 input gain */
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uint8_t SARINPUTGAINCH2 : 1; /*!< ADC Channel2 input gain */
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uint8_t SARINPUTGAINCH3 : 1; /*!< ADC Channel3 input gain */
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uint8_t SARINPUTGAINCH4 : 1; /*!< ADC Channel4 input gain */
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uint8_t SARINPUTGAINCH5 : 1; /*!< ADC Channel5 input gain */
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uint8_t SARINPUTGAINCH6 : 1; /*!< ADC Channel6 input gain */
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uint8_t SARINPUTGAINCH7 : 1; /*!< ADC Channel7 input gain */
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uint8_t SARINPUTGAINCH8 : 1; /*!< ADC Channel8 input gain */
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uint8_t SARINPUTGAINCH9 : 1; /*!< ADC Channel9 input gain */
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uint8_t SARINPUTGAINCH10 : 1; /*!< ADC Channel10 input gain */
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uint8_t : 2; /* (reserved) */
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};
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uint32_t WORD;
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} ADCCHCTRL0R; /* +0x03C */
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union {
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struct {
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uint8_t SAMPCYCCH1 : 4; /*!< Channel1 Sample cycle */
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uint8_t SAMPCYCCH2 : 4; /*!< Channel2 Sample cycle */
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uint8_t SAMPCYCCH3 : 4; /*!< Channel3 Sample cycle */
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uint8_t SAMPCYCCH4 : 4; /*!< Channel4 Sample cycle */
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uint8_t SAMPCYCCH5 : 4; /*!< Channel5 Sample cycle */
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uint8_t SAMPCYCCH6 : 4; /*!< Channel6 Sample cycle */
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uint8_t SAMPCYCCH7 : 4; /*!< Channel7 Sample cycle */
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uint8_t SAMPCYCCH8 : 4; /*!< Channel8 Sample cycle */
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};
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uint32_t WORD;
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} ADCCHCTRL1R; /* +0x040 */
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union {
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struct {
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uint8_t SAMPCYCCH9 : 4; /*!< Channel9 Sample cycle */
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uint8_t SAMPCYCCH10 : 4; /*!< Channel10 Sample cycle */
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uint8_t ADCVREFSELCH1 : 2; /*!< Channel1 adc vref select */
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uint8_t ADCVREFSELCH2 : 2; /*!< Channel2 adc vref select */
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uint8_t ADCVREFSELCH3 : 2; /*!< Channel3 adc vref select */
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uint8_t ADCVREFSELCH4 : 2; /*!< Channel4 adc vref select */
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uint8_t ADCVREFSELCH5 : 2; /*!< Channel5 adc vref select */
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uint8_t ADCVREFSELCH6 : 2; /*!< Channel6 adc vref select */
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uint8_t ADCVREFSELCH7 : 2; /*!< Channel7 adc vref select */
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uint8_t ADCVREFSELCH8 : 2; /*!< Channel8 adc vref select */
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uint8_t ADCVREFSELCH9 : 2; /*!< Channel9 adc vref select */
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uint8_t ADCVREFSELCH10 : 2; /*!< Channel10 adc vref select */
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uint8_t : 4; /* (reserved) */
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};
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uint32_t WORD;
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} ADCCHCTRL2R; /* +0x044 */
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union {
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struct {
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union {
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struct {
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uint8_t INT_CONV_DONE_ENA : 1; /*!< Convert Done Interrupt Enable */
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uint8_t INT_TRIG_CLASH_ENA : 1; /*!< Trigger Clash Interrupt Enable */
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uint8_t : 6; /* (reserved) */
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};
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uint8_t BYTE;
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} ENABLE;
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union {
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struct {
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uint8_t INT_CONV_DONE_CLR : 1; /*!< Convert Done Interrupt Clear */
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uint8_t INT_TRIG_CLASH_CLR : 1; /*!< Trigger Clash Interrupt Clear */
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uint8_t : 6; /* (reserved) */
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};
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uint8_t BYTE;
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} CLEAR;
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union {
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struct {
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uint8_t CONV_DONE : 1; /*!< Convert Done */
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uint8_t TRIG_CLASH : 1; /*!< Trigger Clash */
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uint8_t : 6; /* (reserved) */
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};
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uint8_t BYTE;
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} STATUS;
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union {
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struct {
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uint8_t INT_CONV_DONE : 1; /*!< Convert Done Interrupt */
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uint8_t INT_TRIG_CLASH : 1; /*!< Trigger Clash Interrupt */
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uint8_t : 6; /* (reserved) */
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};
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uint8_t BYTE;
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} IRQ;
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};
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uint32_t WORD;
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} SARINT; /* +0x048 */
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uint8_t SARCLKDIV; /*<! SAR CLOCK DIVIDE +0x04C */
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uint8_t _RESERVED_4D[3]; /* +0x04D */
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} SAR_CTRL_SFRS_t;
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/* -------- End of section using anonymous unions and disabling warnings -------- */
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#if defined (__CC_ARM)
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#pragma pop
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#elif defined (__ICCARM__)
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/* leave anonymous unions enabled */
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#elif (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic pop
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning restore
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/**
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* @brief The starting address of SAR_CTRL SFRS.
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*/
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#define SAR_CTRL_SFRS ((__IO SAR_CTRL_SFRS_t *)0x40013400)
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#endif /* end of __SAR_CTRL_SFR_H__ section */
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