242 lines
9.9 KiB
C
242 lines
9.9 KiB
C
/**
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* @copyright 2022 indie Semiconductor
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*
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* This file is proprietary to indie Semiconductor.
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* All rights reserved. Reproduction or distribution, in whole
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* or in part, is forbidden except by express written permission
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* of indie Semiconductor.
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*
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* @file crga_sfr.h
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*/
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#ifndef CRGA_SFR_H__
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#define CRGA_SFR_H__
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#include <stdint.h>
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/* ------- Start of section using anonymous unions and disabling warnings ------- */
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#if defined (__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined (__ICCARM__)
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#pragma language=extended
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wc11-extensions"
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#pragma clang diagnostic ignored "-Wreserved-id-macro"
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning 586
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/**
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* @brief A structure to represent Special Function Registers for CRGA.
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*/
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typedef struct {
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union {
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struct {
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uint8_t LFRCSTS : 8; /*!< Slow oscillator status */
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uint8_t CLKLFSEL : 8; /*!< LF Clock Source select */
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uint16_t : 16; /* (reserved) */
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};
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uint32_t WORD;
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} LFCLKCTRL; /* +0x000 */
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union {
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struct {
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uint8_t HFRCENA : 1; /*!< Fast oscillator enable */
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uint8_t HFRCSTS : 1; /*!< Fast oscillator status */
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uint8_t UHFRCENA : 1; /*!< Ultra high frequency oscillator enable */
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uint8_t UHFRCHIGHBWEN : 1; /*!< Ultra high frequency oscillator comparator high bandwidth enable */
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uint8_t : 4; /* (reserved) */
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uint8_t SYSCLKSEL : 1; /*!< System clock select */
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uint8_t SELFASTCLK : 1; /*!< Fast clock select */
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uint8_t : 6; /* (reserved) */
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uint8_t DIVSYSCLK : 3; /*!< Clock div select */
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uint8_t : 1; /* (reserved) */
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uint8_t HF_RC_LDO_VSEL : 2;
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uint8_t UHFRCLDOVSEL : 2;
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uint8_t CLKSOFTSTRTEN : 1;
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uint8_t : 1; /* (reserved) */
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uint8_t CLKSOFTSTRTDLY : 3;
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uint8_t : 3; /* (reserved) */
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};
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uint32_t WORD;
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} SYSCLKCTRL; /* +0x004 */
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union {
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struct {
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uint8_t PORFLAG : 1; /*!< Power on reset flag */
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uint8_t OVFLAG : 1; /*!< Over Voltage Monitor flag */
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uint8_t BOR3V3FLAG : 1; /*!< BOR 3v3 flag */
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uint8_t UVFLAG : 1; /*!< Under Voltage Monitor flag */
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uint8_t BOR1V5FLAG : 1; /*!< BOR 1v5 flag */
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uint8_t WDTFLAG : 1; /*!< Watchdog bark flag */
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uint8_t OVTEMPFLAG : 1; /*!< Over Temp Violation flag */
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uint8_t FSSOFLAG : 1; /*!< FSSO flag */
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uint8_t PORFLAGCLR : 1; /*!< POR flag clear */
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uint8_t OVFLAGCLR : 1; /*!< OV flag clear */
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uint8_t : 1; /* (reserved) */
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uint8_t UVFLAGCLR : 1; /*!< UV flag clear */
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uint8_t : 1; /* (reserved) */
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uint8_t WDTFLAGCLR : 1; /*!< WDT flag clear */
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uint8_t OVTEMPFLAGCLR : 1; /*!< OVTEMP flag clear */
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uint8_t FSSOFLAGCLR : 1; /*!< FSSO flag clear */
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uint8_t HARDRSTREQ : 1; /*!< Hard reset request */
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uint8_t SAFEMODEREQ : 1; /*!< Safe Mode request */
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uint8_t : 2; /* (reserved) */
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uint8_t SAFEMODEENA : 1; /*!< Safe Mode enable */
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uint8_t : 3; /* (reserved) */
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uint8_t SOFTRSTREQ : 8; /*!< Soft reset request */
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};
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uint32_t WORD;
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} RESETCTRL; /* +0x008 */
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union {
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struct {
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uint8_t ADCSTOP : 1; /*!< ADC Stop */
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uint8_t PWMSTOP : 1; /*!< PWM Stop */
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uint8_t CTTSTOP : 1; /*!< CTT Stop */
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uint8_t GTMSTOP : 1; /*!< GTM Stop */
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uint8_t SPISTOP : 1; /*!< SPI Stop */
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uint8_t UARTSTOP : 1; /*!< UART Stop */
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uint8_t MATHDIVSTOP : 1; /*!< MATHDIV Stop */
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uint8_t CRCSTOP : 1; /*!< CRC Stop */
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uint8_t PWMAUXSTOP : 8; /*!< PWMAUX Stop */
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uint16_t : 16; /* (reserved) */
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};
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uint32_t WORD;
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} MODUCLKSTOP; /* +0x00C */
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union {
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struct {
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uint8_t ADCSLEEPEN : 1; /*!< ADC Sleep Enable */
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uint8_t PWMSLEEPEN : 1; /*!< PWM Sleep Enable */
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uint8_t CTTSLEEPEN : 1; /*!< CTT Sleep Enable */
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uint8_t GTMSLEEPEN : 1; /*!< GTM Sleep Enable */
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uint8_t SPISLEEPEN : 1; /*!< SPI Sleep Enable */
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uint8_t UARTSLEEPEN : 1; /*!< UART Sleep Enable */
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uint8_t MATHDIVSLEEPEN : 1; /*!< MATHDIV Sleep Enable */
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uint8_t CRCSLEEPEN : 1; /*!< CRC Sleep Enable */
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uint8_t PWMAUXSLEEPEN : 1; /*!< PWMAUX Sleep Enable */
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uint8_t : 6; /* (reserved) */
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uint8_t FLASHSLEEPEN : 1; /*!< Flash Sleep Enable */
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uint16_t : 16; /* (reserved) */
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};
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uint32_t WORD;
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} MODUSLEEPEN; /* +0x010 */
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union {
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struct {
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uint8_t ADCDEEPSLEEPEN : 1; /*!< ADC Deep Sleep Enable */
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uint8_t PWMDEEPSLEEPEN : 1; /*!< PWM Deep Sleep Enable */
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uint8_t CTTDEEPSLEEPEN : 1; /*!< CTT Deep Sleep Enable */
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uint8_t GTMDEEPSLEEPEN : 1; /*!< GTM Deep Sleep Enable */
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uint8_t SPIDEEPSLEEPEN : 1; /*!< SPI Deep Sleep Enable */
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uint8_t UARTDEEPSLEEPEN : 1; /*!< UART Deep Sleep Enable */
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uint8_t MATHDIVDEEPSLEEPEN : 1; /*!< MATHDIV Deep Sleep Enable */
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uint8_t CRCDEEPSLEEPEN : 1; /*!< CRC Deep Sleep Enable */
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uint8_t PWMAUXDEEPSLEEPEN : 1; /*!< PWMAUX Deep Sleep Enable */
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uint8_t : 6; /* (reserved) */
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uint8_t FLASHDEEPSLEEPEN : 1; /*!< Flash Deep Sleep Enable */
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uint16_t : 16; /* (reserved) */
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};
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uint32_t WORD;
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} MODUDEEPSLEEPEN; /* +0x014 */
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uint16_t MODULERSTREQ; /*<! Module Soft reset request +0x018 */
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uint8_t _RESERVED_1A[2]; /* +0x01A */
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union {
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struct {
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uint8_t WDTACTION : 1; /*!< Watchdog action */
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uint8_t FSSORSTEN : 1; /*!< FSSO Reset Enable */
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uint8_t : 6; /* (reserved) */
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uint8_t WDTBARKCNT : 8; /*!< WatchDog Bark Counter */
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uint8_t WDTBARKCNTCLR : 8; /*!< WatchDog Bark Counter Clear */
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} WDTACTION; /* +0x01C */
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uint8_t KILLLFRC; /*<! Kill slow RC oscillator +0x020 */
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uint8_t _RESERVED_21[3]; /* +0x021 */
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union {
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struct {
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uint8_t OVTEMP : 8; /*!< Over Temperature action */
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uint8_t : 8; /* (reserved) */
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uint8_t : 8; /* (reserved) */
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uint8_t OVERTEMP_EN : 1; /*!< OverTemp Monitor Enable bit */
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uint8_t : 6; /* (reserved) */
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uint8_t OVTEMP_LOCK : 1;
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};
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uint32_t WORD;
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} OVTEMPACTION; /* +0x024 */
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union {
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struct {
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uint8_t OV_ACTION : 1; /*!< Over Voltage action */
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uint8_t : 3; /* (reserved) */
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uint8_t UV_ACTION : 1; /*!< Under Voltage action */
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uint8_t : 3; /* (reserved) */
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uint8_t : 8; /* (reserved) */
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uint8_t : 8; /* (reserved) */
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uint8_t : 3; /* (reserved) */
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uint8_t OV_LOCK : 1;
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uint8_t : 3; /* (reserved) */
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uint8_t UV_LOCK : 1;
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};
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uint32_t WORD;
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} OVUVACTION; /* +0x028 */
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union {
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struct {
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uint8_t CRSTEXTENA : 1; /*!< M0 core extend reset enable */
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uint8_t CRSTEXTFLAG : 1; /*!< M0 core extend reset flag */
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uint8_t : 6; /* (reserved) */
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uint8_t CRSTEXTCLR : 8; /*!< M0 core extend reset clear */
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uint8_t SWDFLAG : 8; /*!< SWD wakeup flag */
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uint8_t SWDFLAGCLR : 8; /*!< SWD Wakeup flag clear */
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};
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uint32_t WORD;
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} SWDCTRL; /* +0x02C */
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} CRGA_SFRS_t;
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/* -------- End of section using anonymous unions and disabling warnings -------- */
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#if defined (__CC_ARM)
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#pragma pop
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#elif defined (__ICCARM__)
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/* leave anonymous unions enabled */
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#elif (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic pop
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning restore
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/**
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* @brief The starting address of CRGA SFRS.
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*/
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#define CRGA_SFRS ((__IO CRGA_SFRS_t *)0x40000000)
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#endif /* end of __CRGA_SFR_H__ section */
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