413 lines
18 KiB
C
413 lines
18 KiB
C
/**
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* @copyright 2023 indie Semiconductor
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*
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* This file is proprietary to indie Semiconductor.
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* All rights reserved. Reproduction or distribution, in whole
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* or in part, is forbidden except by express written permission
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* of indie Semiconductor.
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*
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* @file pwm_sfr.h
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*/
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#ifndef PWM_SFR_H__
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#define PWM_SFR_H__
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#include <stdint.h>
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/* ------- Start of section using anonymous unions and disabling warnings ------- */
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#if defined (__CC_ARM)
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#pragma push
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#pragma anon_unions
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#elif defined (__ICCARM__)
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#pragma language=extended
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#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wc11-extensions"
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#pragma clang diagnostic ignored "-Wreserved-id-macro"
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning 586
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/**
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* @brief A structure to represent Special Function Registers for PWM.
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*/
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typedef struct {
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uint16_t PT0PERIOD; /*<! <b>Period</b> +0x000 */
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uint8_t _RESERVED_02[2]; /* +0x002 */
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uint16_t PT0CV; /* +0x004 */
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uint8_t _RESERVED_06[2]; /* +0x006 */
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uint16_t PT1PERIOD; /*<! <b>Period</b> +0x008 */
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uint8_t _RESERVED_0A[2]; /* +0x00A */
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uint16_t PT1CV; /* +0x00C */
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uint8_t _RESERVED_0E[2]; /* +0x00E */
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union {
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struct {
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uint8_t PT0RC : 1;
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uint8_t PT0RS : 1;
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uint8_t PT0RST : 1; /*!< <b>PT0 reset</b> */
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uint8_t PT0DTR : 1; /*!< <b>PT0 dead-time counter reset</b> */
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uint8_t : 1; /* (reserved) */
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uint8_t PT0CEVT : 1; /*!< <b>PT0 count event</b> */
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uint8_t PT0UPEC : 1;
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uint8_t PT0UPES : 1;
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uint8_t : 8; /* (reserved) */
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uint8_t PT1RC : 1;
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uint8_t PT1RS : 1;
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uint8_t PT1RST : 1; /*!< <b>PT1 reset</b> */
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uint8_t PT1DTR : 1; /*!< <b>PT1 dead-time counter reset</b> */
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uint8_t : 1; /* (reserved) */
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uint8_t PT1CEVT : 1; /*!< <b>PT1 count event</b> */
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uint8_t PT1UPEC : 1;
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uint8_t PT1UPES : 1;
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} CTRL0R; /* +0x010 */
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union {
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struct {
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uint8_t PT0PRES : 4; /*!< <b>Prescaler select</b> */
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uint8_t PT0R : 1; /*!< <b>Timer PT0 run bit</b> */
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uint8_t PT0UPE : 1; /*!< <b>Timer PT0 update enable</b> */
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uint8_t PT0CDWN : 1; /*!< <b>Count direction of timer PT0</b> */
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uint8_t PT0MODE : 1; /*!< <b>PT0 operating mode</b> */
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uint8_t PT0CIN : 2; /*!< <b>Input event select for PT0 counting</b> */
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uint8_t PT0SSE : 1; /*!< <b>PT0 single shot enable</b> */
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uint8_t PT0HRSEL : 2; /*!< <b>PT0 hardware run selection</b> */
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uint8_t : 3; /* (reserved) */
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uint8_t PT1PRES : 4; /*!< <b>Prescaler select</b> */
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uint8_t PT1R : 1; /*!< <b>Timer PT1 run bit</b> */
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uint8_t PT1UPE : 1; /*!< <b>Timer PT1 update enable</b> */
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uint8_t PT1CDWN : 1; /*!< <b>Count direction of timer PT1</b> */
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uint8_t PT1MODE : 1; /*!< <b>PT1 operating mode</b> */
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uint8_t PT1CIN : 2; /*!< <b>Input event select for PT1 counting</b> */
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uint8_t PT1SSE : 1; /*!< <b>PT1 single shot enable</b> */
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uint8_t PT1HRSEL : 2; /*!< <b>PT1 hardware run selection</b> */
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uint8_t CC1CNTS : 1; /*!< <b>Compare Channel 1 counter selection</b> */
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uint8_t CC2CNTS : 1; /*!< <b>Compare Channel 2 counter selection</b> */
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uint8_t CC3CNTS : 1; /*!< <b>Compare Channel 3 counter selection</b> */
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};
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uint32_t WORD;
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} CTRL1R; /* +0x014 */
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union {
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struct {
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uint8_t PT1TES : 4;
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uint8_t PT1TED : 2;
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uint8_t : 2; /* (reserved) */
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uint32_t : 24; /* (reserved) */
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};
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uint32_t WORD;
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} TRIGR; /* +0x018 */
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union {
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struct {
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uint8_t PT0DT : 8;
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uint8_t PT1DT : 8;
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uint8_t CCXDTE : 8;
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} DTCR; /* +0x01C */
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union {
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struct {
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uint16_t PFALL0 : 16; /*!< <b>State Pulse Fall CC0</b> */
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uint16_t PRISE0 : 16; /*!< <b>State Pulse Rise CC0</b> */
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};
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uint32_t WORD;
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} PULSE0R; /* +0x020 */
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union {
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struct {
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uint16_t PFALL1 : 16; /*!< <b>State Pulse Fall CC1</b> */
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uint16_t PRISE1 : 16; /*!< <b>State Pulse Rise CC1</b> */
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};
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uint32_t WORD;
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} PULSE1R; /* +0x024 */
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union {
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struct {
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uint16_t PFALL2 : 16; /*!< <b>State Pulse Fall CC2</b> */
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uint16_t PRISE2 : 16; /*!< <b>State Pulse Rise CC2</b> */
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};
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uint32_t WORD;
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} PULSE2R; /* +0x028 */
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union {
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struct {
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uint16_t PFALL3 : 16; /*!< <b>State Pulse Fall CC3</b> */
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uint16_t PRISE3 : 16; /*!< <b>State Pulse Rise CC3</b> */
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};
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uint32_t WORD;
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} PULSE3R; /* +0x02C */
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union {
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struct {
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uint8_t CCXCS : 8;
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uint8_t CC00PS : 1;
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uint8_t CC01PS : 1;
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uint8_t CC10PS : 1;
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uint8_t CC11PS : 1;
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uint8_t CC20PS : 1;
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uint8_t CC21PS : 1;
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uint8_t CC30PS : 1;
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uint8_t CC31PS : 1;
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uint8_t CC30IM : 8;
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} CMPSTATR; /* +0x030 */
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union {
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struct {
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uint8_t CCXCSS : 8;
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uint8_t CCXCSC : 8;
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uint16_t : 16; /* (reserved) */
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};
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uint32_t WORD;
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} CMPMDFIR; /* +0x034 */
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uint8_t PSL; /* +0x038 */
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uint8_t _RESERVED_39[3]; /* +0x039 */
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union {
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struct {
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uint8_t SWSEL : 3;
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uint8_t : 1; /* (reserved) */
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uint8_t SWSYNC : 2;
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uint8_t : 2; /* (reserved) */
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uint8_t MCUPEPT0U : 1;
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uint8_t MCUPEPT0D : 1;
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uint8_t MCUPEPT1U : 1;
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uint8_t MCUPEPT1D : 1;
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uint8_t : 4; /* (reserved) */
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uint16_t : 16; /* (reserved) */
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};
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uint32_t WORD;
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} MCCTRLR; /* +0x03C */
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union {
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struct {
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uint8_t MCPTN : 8;
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uint8_t : 1; /* (reserved) */
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uint8_t NTIF : 1;
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uint8_t : 6; /* (reserved) */
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uint8_t MCPTNS : 8;
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uint8_t MCUPR : 8;
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};
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uint32_t WORD;
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} MCOUTR; /* +0x040 */
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union {
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struct {
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uint8_t TRPSCM : 2;
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uint8_t TRPFCM : 1;
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uint8_t : 5; /* (reserved) */
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uint8_t TRPEN : 8;
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uint8_t TRPPEN : 1;
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uint8_t OCPFAST : 1;
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uint8_t : 2; /* (reserved) */
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uint8_t OCPFILTS : 4;
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} TRPCTRLR; /* +0x044 */
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union {
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struct {
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uint8_t CCXMODEN : 8;
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uint8_t PT1MODEN : 8;
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uint8_t MCEN : 8;
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} MODCTRLR; /* +0x048 */
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union {
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struct {
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uint8_t PWM0RMP : 2; /*!< <b>PWM0 remap selection</b> */
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uint8_t : 2; /* (reserved) */
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uint8_t PWM1RMP : 2; /*!< <b>PWM1 remap selection</b> */
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uint8_t : 2; /* (reserved) */
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uint8_t PWM2RMP : 2; /*!< <b>PWM2 remap selection</b> */
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uint8_t : 2; /* (reserved) */
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uint8_t PWM3RMP : 2; /*!< <b>PWM3 remap selection</b> */
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uint8_t : 2; /* (reserved) */
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uint16_t : 16; /* (reserved) */
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};
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uint32_t WORD;
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} CHREMAPR; /* +0x04C */
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union {
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struct {
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uint16_t CMPTRIG0V : 16; /*!< <b>Trigger0 Compare Value</b> */
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uint8_t TRIG0PT : 1; /*!< <b>Trigger0 Compare Counter Selection</b> */
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uint8_t : 3; /* (reserved) */
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uint8_t TRIG0MD : 1; /*!< <b>Trigger0 Compare Mode</b> */
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uint8_t : 3; /* (reserved) */
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} CMPTRIG0R; /* +0x050 */
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union {
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struct {
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uint16_t CMPTRIG1V : 16; /*!< <b>Trigger1 Compare Value</b> */
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uint8_t TRIG1PT : 1; /*!< <b>Trigger1 Compare Counter Selection</b> */
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uint8_t : 3; /* (reserved) */
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uint8_t TRIG1MD : 1; /*!< <b>Trigger1 Compare Mode</b> */
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uint8_t : 3; /* (reserved) */
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} CMPTRIG1R; /* +0x054 */
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union {
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struct {
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uint8_t CC0INTOL : 2; /*!< <b>CC0 interrupt output line selection</b> */
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uint8_t CC1INTOL : 2; /*!< <b>CC1 interrupt output line selection</b> */
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uint8_t CC2INTOL : 2; /*!< <b>CC2 interrupt output line selection</b> */
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uint8_t CC3INTOL : 2; /*!< <b>CC3 interrupt output line selection</b> */
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uint8_t PT0INTOL : 2; /*!< <b>PT0 interrupt output line selection</b> */
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uint8_t PT1INTOL : 2; /*!< <b>PT1 interrupt output line selection</b> */
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uint8_t MCUPFINTOL : 2; /*!< <b>MCUPF interrupt output line selection</b> */
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uint8_t TRPINTOL : 2; /*!< <b>TRPIS interrupt output line selection</b> */
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uint8_t CT0FINTOL : 2; /*!< <b>CT0F interrupt output line selection</b> */
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uint8_t CT1FINTOL : 2; /*!< <b>CT1F interrupt output line selection</b> */
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uint8_t : 4; /* (reserved) */
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} INTOLR; /* +0x058 */
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union {
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struct {
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uint8_t CCXRIE : 4; /*!< <b>CCx Rise-Match interrupt enable</b> */
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uint8_t CCXFIE : 4; /*!< <b>CCx Fall-Match interrupt enable</b> */
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uint8_t PTXOMIE : 2; /*!< <b>PTx One-Match interrupt enable</b> */
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uint8_t PTXPMIE : 2; /*!< <b>PTx Period-Match interrupt enable</b> */
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uint8_t MCUPFIE : 1; /*!< <b>Multi-channel mode updated interrupt enable</b> */
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uint8_t : 2; /* (reserved) */
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uint8_t TRPIE : 1; /*!< <b>Trap interrupt enable</b> */
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uint8_t CT0IE : 1; /*!< <b>Compare Trigger0 interrupt enable</b> */
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uint8_t CT1IE : 1; /*!< <b>Compare Trigger1 interrupt enable</b> */
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uint8_t : 6; /* (reserved) */
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} INTCTRLR; /* +0x05C */
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union {
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struct {
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uint8_t CCXRS : 4; /*!< <b>CCx Rise-Match Flag Set</b> */
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uint8_t CCXFS : 4; /*!< <b>CCx Fall-Match Flag Set</b> */
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uint8_t PTXOMS : 2; /*!< <b>PTx One-Match Flag Set</b> */
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uint8_t PTXPMS : 2; /*!< <b>PTx Period-Match Flag Set</b> */
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uint8_t MCUPFS : 1; /*!< <b>Multi-channel mode updated Flag Set</b> */
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uint8_t : 2; /* (reserved) */
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uint8_t TRPISS : 1; /*!< <b>Trap Interrupt Status Set</b> */
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uint8_t CT0FS : 1; /*!< <b>Compare Trigger0 Interrupt Status Set</b> */
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uint8_t CT1FS : 1; /*!< <b>Compare Trigger1 Interrupt Status Set</b> */
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uint8_t : 6; /* (reserved) */
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} INTSETR; /* +0x060 */
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union {
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struct {
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uint8_t CCXRC : 4; /*!< <b>CCx Rise-Match Flag Clear</b> */
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uint8_t CCXFC : 4; /*!< <b>CCx Fall-Match Flag Clear</b> */
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uint8_t PTXOMC : 2; /*!< <b>PTx One-Match Flag Clear</b> */
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uint8_t PTXPMC : 2; /*!< <b>PTx Period-Match Flag Clear</b> */
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uint8_t MCUPFC : 1; /*!< <b>Multi-channel mode updated Flag Clear</b> */
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uint8_t TRPFC : 1; /*!< <b>Trap Flag Clear</b> */
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uint8_t : 1; /* (reserved) */
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uint8_t TRPISC : 1; /*!< <b>Trap Interrupt Status Clear</b> */
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uint8_t CT0FC : 1; /*!< <b>Compare Trigger0 Interrupt Status Clear</b> */
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uint8_t CT1FC : 1; /*!< <b>Compare Trigger1 Interrupt Status Clear</b> */
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uint8_t : 6; /* (reserved) */
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} INTCLRR; /* +0x064 */
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union {
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struct {
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uint8_t CCXR : 4; /*!< <b>CCx Rise-Match Flag</b> */
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uint8_t CCXF : 4; /*!< <b>CCx Fall-Match Flag</b> */
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uint8_t PTXOM : 2; /*!< <b>PTx One-Match Flag</b> */
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uint8_t PTXPM : 2; /*!< <b>PTx Period-Match Flag</b> */
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uint8_t MCUPF : 1; /*!< <b>Multi-channel mode updated Flag</b> */
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uint8_t TRPF : 1; /*!< <b>Trap Flag</b> */
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uint8_t TRPS : 1; /*!< <b>Trap State</b> */
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uint8_t TRPIS : 1; /*!< <b>Trap Interrupt Status</b> */
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uint8_t CT0F : 1; /*!< <b>Compare trigger0 Flag</b> */
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uint8_t CT1F : 1; /*!< <b>Compare trigger1 Flag</b> */
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uint8_t : 6; /* (reserved) */
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} INTRAWSTATR; /* +0x068 */
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union {
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struct {
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uint8_t CCXRIRQ : 4; /*!< <b>Corresponding CCx Rise-Match interrupt active</b> */
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uint8_t CCXFIRQ : 4; /*!< <b>Corresponding CCx Fall-Match interrupt active</b> */
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uint8_t PTXOMIRQ : 2; /*!< <b>Corresponding PTx One-Match interrupt active</b> */
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uint8_t PTXPMIRQ : 2; /*!< <b>Corresponding PTx Period-Match interrupt active</b> */
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uint8_t MCUPFIRQ : 1; /*!< <b>Multi-channel mode updated interrupt active</b> */
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uint8_t : 2; /* (reserved) */
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uint8_t TRPIRQ : 1; /*!< <b>Trap interrupt active</b> */
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uint8_t CT0IRQ : 1; /*!< <b>Compare trigger0 interrupt active</b> */
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uint8_t CT1IRQ : 1; /*!< <b>Compare trigger1 interrupt active</b> */
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uint8_t : 6; /* (reserved) */
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uint8_t : 8; /* (reserved) */
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};
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uint32_t WORD;
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} INTACTSTATR; /* +0x06C */
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} PWM_SFRS_t;
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/* -------- End of section using anonymous unions and disabling warnings -------- */
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#if defined (__CC_ARM)
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#pragma pop
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#elif defined (__ICCARM__)
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/* leave anonymous unions enabled */
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#elif (__ARMCC_VERSION >= 6010050)
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#pragma clang diagnostic pop
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#elif defined (__GNUC__)
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/* anonymous unions are enabled by default */
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#elif defined (__TMS470__)
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/* anonymous unions are enabled by default */
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#elif defined (__TASKING__)
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#pragma warning restore
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#elif defined (__CSMC__)
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/* anonymous unions are enabled by default */
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#else
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#warning Not supported compiler type
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#endif
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/**
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* @brief The starting address of PWM SFRS.
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*/
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#define PWM_SFRS ((__IO PWM_SFRS_t *)0x40010000)
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#endif /* end of __PWM_SFR_H__ section */
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