67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
#ifndef META_H__
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#define META_H__
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// declare an enumerated type that can be used to refer to interrupts by name, e.g. in calls to the NVIC configuration
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// functions - the definitions here must match the vector table positions, offset so that IRQ0 (the 1st ASIC IRQ) has
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// the value 0...
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//
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typedef enum IRQn
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{
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// Cortex-M0 core exceptions...
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Reset_IRQn = -15,
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NMI_IRQn = -14,
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HardFault_IRQn = -13,
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SVC_IRQn = -5,
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PendSV_IRQn = -2,
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SysTick_IRQn = -1,
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// ASIC-specific IRQs... (should match the vector defined in dig_meta_top.sv)
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IOCTRLA_IRQn = 0,
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OVTEMP_IRQn = 1,
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GPIO_IRQn = 2,
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PWM_AUX_IRQn = 3,
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GT4_5_IRQn = 4,
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WUTIMER_IRQn = 5,
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WatchdogA_IRQn = 6,
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ADC_IRQn = 7,
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SPI_IRQn = 8,
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WULIN_IRQn = 9,
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UART0_IRQn = 10,
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DIV_IRQn = 11,
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LIN_IRQn = 12,
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FLASH_IRQn = 13,
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SRAM_ECCC_IQn = 14,
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GT1_IRQn = 15,
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GT2_IRQn = 16,
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GT3_IRQn = 17,
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CT2_IRQn = 18,
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CT3_IRQn = 19,
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CT4_IRQn = 20,
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CT5_IRQn = 21,
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CT6_IRQn = 22,
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CR_IRQn = 23,
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PWM_INTOL0_IRQn = 24,
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PWM_INTOL1_IRQn = 25,
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PWM_INTOL2_IRQn = 26,
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PWM_INTOL3_IRQn = 27,
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BOR_IRQn = 28,
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UV_OV_IRQn = 29,
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CSP_OCP_IRQn = 30,
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Lullaby_IRQn = 31
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} IRQn_Type;
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//
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// and define a tell-tale macro that will prevent the clough.h header from attempting to re-define this with the
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// default (non-ASIC-specific) version...
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//
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#define __IRQn_Type
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#define TRUE (1U)
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#define FALSE (0U)
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#include <stdint.h>
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#include "sfrs/meta_sfr.h"
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#include "verne.h"
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#endif
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