/** * @copyright 2022 indie Semiconductor * * This file is proprietary to indie Semiconductor. * All rights reserved. Reproduction or distribution, in whole * or in part, is forbidden except by express written permission * of indie Semiconductor. * * @file sar_ctrl_sfr.h */ #ifndef SAR_CTRL_SFR_H__ #define SAR_CTRL_SFR_H__ #include /* ------- Start of section using anonymous unions and disabling warnings ------- */ #if defined (__CC_ARM) #pragma push #pragma anon_unions #elif defined (__ICCARM__) #pragma language=extended #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wc11-extensions" #pragma clang diagnostic ignored "-Wreserved-id-macro" #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning 586 #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /** * @brief A structure to represent Special Function Registers for SAR_CTRL. */ typedef struct { uint16_t DATA; /* +0x000 */ uint16_t _RESERVED; /* +0x002 */ }SAR_Data_t; typedef struct { SAR_Data_t DATA[10]; /* +0x000 */ union { struct { uint8_t : 7; /* (reserved) */ uint8_t ROUND : 1; /*!< ADC round enable */ uint8_t TRIGSRC : 8; /*!< SAR Converion Trigger Source Selects */ uint8_t PWMAUXTRIGSEL : 4; /*!< SAR Converion Trigger Selects of PWMAUX */ uint8_t PWMAUXCHSEL : 3; /*!< PWMAUX Trigger Channel Selects */ uint8_t TRIGSEL : 1; /*!< SAR Trigger Signal Selects */ uint8_t TRIGDLY : 8; /*!< trigger delay */ }; uint32_t WORD; } SARCFG; /* +0x028 */ union { struct { uint8_t ADCSELVINVCMEXT : 1; /*!< Select External Inputs to ADC */ uint8_t : 6; /* (reserved) */ uint8_t SARAFEEN : 1; /*!< ADC AFE Enable */ uint8_t SARPREAMPEN : 8; /*!< adc pre-amp enable */ uint16_t : 16; /* (reserved) */ }; uint32_t WORD; } AFECTRL; /* +0x02C */ union { struct { uint8_t SARENAREQ : 8; /*!< SAR ADC Enable */ uint8_t : 2; /* (reserved) */ uint8_t DIGRESET : 1; /*!< SAR Digital Part Reset */ uint8_t : 5; /* (reserved) */ uint8_t CONVERT : 1; /*!< ADC START/STATUS Register */ uint8_t : 1; /* (reserved) */ uint8_t CONT : 1; /*!< Continuous Conversion Enable */ uint8_t : 5; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } SARCTRL; /* +0x030 */ union { struct { uint8_t SEQCNT : 4; /*!< Channel Sequence count */ uint8_t : 1; /* (reserved) */ uint32_t CH1SEL : 5; /*!< Channel1 Selection !!misaligned!! */ uint8_t CH2SEL : 5; /*!< Channel2 Selection */ uint8_t : 1; /* (reserved) */ uint8_t CH3SEL : 8; /*!< Channel3 Selection */ uint8_t CH4SEL : 5; /*!< Channel4 Selection */ uint8_t : 2; /* (reserved) */ uint8_t TESTBATTERYGAINCHOOSE : 1; /*!< VBAT Gain Select */ }; uint32_t WORD; } ADCCHCONF; /* +0x034 */ union { struct { uint8_t CH5SEL : 5; /*!< Channel5 Selection */ uint32_t CH6SEL : 5; /*!< Channel6 Selection !!misaligned!! */ uint8_t CH7SEL : 5; /*!< Channel7 Selection */ uint32_t CH8SEL : 5; /*!< Channel8 Selection !!misaligned!! */ uint32_t CH9SEL : 5; /*!< Channel9 Selection !!misaligned!! */ uint8_t CH10SEL : 5; /*!< Channel10 Selection */ uint8_t : 2; /* (reserved) */ }; uint32_t WORD; } ADCCHSELR; /* +0x038 */ union { struct { uint8_t SAR_INPUT_MODE_CH1 : 2; /*!< CH1 AFE Input Modes */ uint8_t SAR_INPUT_MODE_CH2 : 2; /*!< CH2 AFE Input Modes */ uint8_t SAR_INPUT_MODE_CH3 : 2; /*!< CH3 AFE Input Modes */ uint8_t SAR_INPUT_MODE_CH4 : 2; /*!< CH4 AFE Input Modes */ uint8_t SAR_INPUT_MODE_CH5 : 2; /*!< CH5 AFE Input Modes */ uint8_t SAR_INPUT_MODE_CH6 : 2; /*!< CH6 AFE Input Modes */ uint8_t SAR_INPUT_MODE_CH7 : 2; /*!< CH7 AFE Input Modes */ uint8_t SAR_INPUT_MODE_CH8 : 2; /*!< CH8 AFE Input Modes */ uint8_t SAR_INPUT_MODE_CH9 : 2; /*!< CH9 AFE Input Modes */ uint8_t SAR_INPUT_MODE_CH10 : 2; /*!< CH10 AFE Input Modes */ uint8_t SARINPUTGAINCH1 : 1; /*!< ADC Channel1 input gain */ uint8_t SARINPUTGAINCH2 : 1; /*!< ADC Channel2 input gain */ uint8_t SARINPUTGAINCH3 : 1; /*!< ADC Channel3 input gain */ uint8_t SARINPUTGAINCH4 : 1; /*!< ADC Channel4 input gain */ uint8_t SARINPUTGAINCH5 : 1; /*!< ADC Channel5 input gain */ uint8_t SARINPUTGAINCH6 : 1; /*!< ADC Channel6 input gain */ uint8_t SARINPUTGAINCH7 : 1; /*!< ADC Channel7 input gain */ uint8_t SARINPUTGAINCH8 : 1; /*!< ADC Channel8 input gain */ uint8_t SARINPUTGAINCH9 : 1; /*!< ADC Channel9 input gain */ uint8_t SARINPUTGAINCH10 : 1; /*!< ADC Channel10 input gain */ uint8_t : 2; /* (reserved) */ }; uint32_t WORD; } ADCCHCTRL0R; /* +0x03C */ union { struct { uint8_t SAMPCYCCH1 : 4; /*!< Channel1 Sample cycle */ uint8_t SAMPCYCCH2 : 4; /*!< Channel2 Sample cycle */ uint8_t SAMPCYCCH3 : 4; /*!< Channel3 Sample cycle */ uint8_t SAMPCYCCH4 : 4; /*!< Channel4 Sample cycle */ uint8_t SAMPCYCCH5 : 4; /*!< Channel5 Sample cycle */ uint8_t SAMPCYCCH6 : 4; /*!< Channel6 Sample cycle */ uint8_t SAMPCYCCH7 : 4; /*!< Channel7 Sample cycle */ uint8_t SAMPCYCCH8 : 4; /*!< Channel8 Sample cycle */ }; uint32_t WORD; } ADCCHCTRL1R; /* +0x040 */ union { struct { uint8_t SAMPCYCCH9 : 4; /*!< Channel9 Sample cycle */ uint8_t SAMPCYCCH10 : 4; /*!< Channel10 Sample cycle */ uint8_t ADCVREFSELCH1 : 2; /*!< Channel1 adc vref select */ uint8_t ADCVREFSELCH2 : 2; /*!< Channel2 adc vref select */ uint8_t ADCVREFSELCH3 : 2; /*!< Channel3 adc vref select */ uint8_t ADCVREFSELCH4 : 2; /*!< Channel4 adc vref select */ uint8_t ADCVREFSELCH5 : 2; /*!< Channel5 adc vref select */ uint8_t ADCVREFSELCH6 : 2; /*!< Channel6 adc vref select */ uint8_t ADCVREFSELCH7 : 2; /*!< Channel7 adc vref select */ uint8_t ADCVREFSELCH8 : 2; /*!< Channel8 adc vref select */ uint8_t ADCVREFSELCH9 : 2; /*!< Channel9 adc vref select */ uint8_t ADCVREFSELCH10 : 2; /*!< Channel10 adc vref select */ uint8_t : 4; /* (reserved) */ }; uint32_t WORD; } ADCCHCTRL2R; /* +0x044 */ union { struct { union { struct { uint8_t INT_CONV_DONE_ENA : 1; /*!< Convert Done Interrupt Enable */ uint8_t INT_TRIG_CLASH_ENA : 1; /*!< Trigger Clash Interrupt Enable */ uint8_t : 6; /* (reserved) */ }; uint8_t BYTE; } ENABLE; union { struct { uint8_t INT_CONV_DONE_CLR : 1; /*!< Convert Done Interrupt Clear */ uint8_t INT_TRIG_CLASH_CLR : 1; /*!< Trigger Clash Interrupt Clear */ uint8_t : 6; /* (reserved) */ }; uint8_t BYTE; } CLEAR; union { struct { uint8_t CONV_DONE : 1; /*!< Convert Done */ uint8_t TRIG_CLASH : 1; /*!< Trigger Clash */ uint8_t : 6; /* (reserved) */ }; uint8_t BYTE; } STATUS; union { struct { uint8_t INT_CONV_DONE : 1; /*!< Convert Done Interrupt */ uint8_t INT_TRIG_CLASH : 1; /*!< Trigger Clash Interrupt */ uint8_t : 6; /* (reserved) */ }; uint8_t BYTE; } IRQ; }; uint32_t WORD; } SARINT; /* +0x048 */ uint8_t SARCLKDIV; /*= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning restore #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /** * @brief The starting address of SAR_CTRL SFRS. */ #define SAR_CTRL_SFRS ((__IO SAR_CTRL_SFRS_t *)0x40013400) #endif /* end of __SAR_CTRL_SFR_H__ section */