/** * @copyright 2022 indie Semiconductor * * This file is proprietary to indie Semiconductor. * All rights reserved. Reproduction or distribution, in whole * or in part, is forbidden except by express written permission * of indie Semiconductor. * * @file crga_sfr.h */ #ifndef CRGA_SFR_H__ #define CRGA_SFR_H__ #include /* ------- Start of section using anonymous unions and disabling warnings ------- */ #if defined (__CC_ARM) #pragma push #pragma anon_unions #elif defined (__ICCARM__) #pragma language=extended #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wc11-extensions" #pragma clang diagnostic ignored "-Wreserved-id-macro" #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning 586 #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /** * @brief A structure to represent Special Function Registers for CRGA. */ typedef struct { union { struct { uint8_t LFRCSTS : 8; /*!< Slow oscillator status */ uint8_t CLKLFSEL : 8; /*!< LF Clock Source select */ uint16_t : 16; /* (reserved) */ }; uint32_t WORD; } LFCLKCTRL; /* +0x000 */ union { struct { uint8_t HFRCENA : 1; /*!< Fast oscillator enable */ uint8_t HFRCSTS : 1; /*!< Fast oscillator status */ uint8_t UHFRCENA : 1; /*!< Ultra high frequency oscillator enable */ uint8_t UHFRCHIGHBWEN : 1; /*!< Ultra high frequency oscillator comparator high bandwidth enable */ uint8_t : 4; /* (reserved) */ uint8_t SYSCLKSEL : 1; /*!< System clock select */ uint8_t SELFASTCLK : 1; /*!< Fast clock select */ uint8_t : 6; /* (reserved) */ uint8_t DIVSYSCLK : 3; /*!< Clock div select */ uint8_t : 1; /* (reserved) */ uint8_t HF_RC_LDO_VSEL : 2; uint8_t UHFRCLDOVSEL : 2; uint8_t CLKSOFTSTRTEN : 1; uint8_t : 1; /* (reserved) */ uint8_t CLKSOFTSTRTDLY : 3; uint8_t : 3; /* (reserved) */ }; uint32_t WORD; } SYSCLKCTRL; /* +0x004 */ union { struct { uint8_t PORFLAG : 1; /*!< Power on reset flag */ uint8_t OVFLAG : 1; /*!< Over Voltage Monitor flag */ uint8_t BOR3V3FLAG : 1; /*!< BOR 3v3 flag */ uint8_t UVFLAG : 1; /*!< Under Voltage Monitor flag */ uint8_t BOR1V5FLAG : 1; /*!< BOR 1v5 flag */ uint8_t WDTFLAG : 1; /*!< Watchdog bark flag */ uint8_t OVTEMPFLAG : 1; /*!< Over Temp Violation flag */ uint8_t FSSOFLAG : 1; /*!< FSSO flag */ uint8_t PORFLAGCLR : 1; /*!< POR flag clear */ uint8_t OVFLAGCLR : 1; /*!< OV flag clear */ uint8_t : 1; /* (reserved) */ uint8_t UVFLAGCLR : 1; /*!< UV flag clear */ uint8_t : 1; /* (reserved) */ uint8_t WDTFLAGCLR : 1; /*!< WDT flag clear */ uint8_t OVTEMPFLAGCLR : 1; /*!< OVTEMP flag clear */ uint8_t FSSOFLAGCLR : 1; /*!< FSSO flag clear */ uint8_t HARDRSTREQ : 1; /*!< Hard reset request */ uint8_t SAFEMODEREQ : 1; /*!< Safe Mode request */ uint8_t : 2; /* (reserved) */ uint8_t SAFEMODEENA : 1; /*!< Safe Mode enable */ uint8_t : 3; /* (reserved) */ uint8_t SOFTRSTREQ : 8; /*!< Soft reset request */ }; uint32_t WORD; } RESETCTRL; /* +0x008 */ union { struct { uint8_t ADCSTOP : 1; /*!< ADC Stop */ uint8_t PWMSTOP : 1; /*!< PWM Stop */ uint8_t CTTSTOP : 1; /*!< CTT Stop */ uint8_t GTMSTOP : 1; /*!< GTM Stop */ uint8_t SPISTOP : 1; /*!< SPI Stop */ uint8_t UARTSTOP : 1; /*!< UART Stop */ uint8_t MATHDIVSTOP : 1; /*!< MATHDIV Stop */ uint8_t CRCSTOP : 1; /*!< CRC Stop */ uint8_t PWMAUXSTOP : 8; /*!< PWMAUX Stop */ uint16_t : 16; /* (reserved) */ }; uint32_t WORD; } MODUCLKSTOP; /* +0x00C */ union { struct { uint8_t ADCSLEEPEN : 1; /*!< ADC Sleep Enable */ uint8_t PWMSLEEPEN : 1; /*!< PWM Sleep Enable */ uint8_t CTTSLEEPEN : 1; /*!< CTT Sleep Enable */ uint8_t GTMSLEEPEN : 1; /*!< GTM Sleep Enable */ uint8_t SPISLEEPEN : 1; /*!< SPI Sleep Enable */ uint8_t UARTSLEEPEN : 1; /*!< UART Sleep Enable */ uint8_t MATHDIVSLEEPEN : 1; /*!< MATHDIV Sleep Enable */ uint8_t CRCSLEEPEN : 1; /*!< CRC Sleep Enable */ uint8_t PWMAUXSLEEPEN : 1; /*!< PWMAUX Sleep Enable */ uint8_t : 6; /* (reserved) */ uint8_t FLASHSLEEPEN : 1; /*!< Flash Sleep Enable */ uint16_t : 16; /* (reserved) */ }; uint32_t WORD; } MODUSLEEPEN; /* +0x010 */ union { struct { uint8_t ADCDEEPSLEEPEN : 1; /*!< ADC Deep Sleep Enable */ uint8_t PWMDEEPSLEEPEN : 1; /*!< PWM Deep Sleep Enable */ uint8_t CTTDEEPSLEEPEN : 1; /*!< CTT Deep Sleep Enable */ uint8_t GTMDEEPSLEEPEN : 1; /*!< GTM Deep Sleep Enable */ uint8_t SPIDEEPSLEEPEN : 1; /*!< SPI Deep Sleep Enable */ uint8_t UARTDEEPSLEEPEN : 1; /*!< UART Deep Sleep Enable */ uint8_t MATHDIVDEEPSLEEPEN : 1; /*!< MATHDIV Deep Sleep Enable */ uint8_t CRCDEEPSLEEPEN : 1; /*!< CRC Deep Sleep Enable */ uint8_t PWMAUXDEEPSLEEPEN : 1; /*!< PWMAUX Deep Sleep Enable */ uint8_t : 6; /* (reserved) */ uint8_t FLASHDEEPSLEEPEN : 1; /*!< Flash Deep Sleep Enable */ uint16_t : 16; /* (reserved) */ }; uint32_t WORD; } MODUDEEPSLEEPEN; /* +0x014 */ uint16_t MODULERSTREQ; /*= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning restore #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /** * @brief The starting address of CRGA SFRS. */ #define CRGA_SFRS ((__IO CRGA_SFRS_t *)0x40000000) #endif /* end of __CRGA_SFR_H__ section */