/** * @copyright 2023 indie Semiconductor * * This file is proprietary to indie Semiconductor. * All rights reserved. Reproduction or distribution, in whole * or in part, is forbidden except by express written permission * of indie Semiconductor. * * @file pwm_sfr.h */ #ifndef PWM_SFR_H__ #define PWM_SFR_H__ #include /* ------- Start of section using anonymous unions and disabling warnings ------- */ #if defined (__CC_ARM) #pragma push #pragma anon_unions #elif defined (__ICCARM__) #pragma language=extended #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wc11-extensions" #pragma clang diagnostic ignored "-Wreserved-id-macro" #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning 586 #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /** * @brief A structure to represent Special Function Registers for PWM. */ typedef struct { uint16_t PT0PERIOD; /*Period +0x000 */ uint8_t _RESERVED_02[2]; /* +0x002 */ uint16_t PT0CV; /* +0x004 */ uint8_t _RESERVED_06[2]; /* +0x006 */ uint16_t PT1PERIOD; /*Period +0x008 */ uint8_t _RESERVED_0A[2]; /* +0x00A */ uint16_t PT1CV; /* +0x00C */ uint8_t _RESERVED_0E[2]; /* +0x00E */ union { struct { uint8_t PT0RC : 1; uint8_t PT0RS : 1; uint8_t PT0RST : 1; /*!< PT0 reset */ uint8_t PT0DTR : 1; /*!< PT0 dead-time counter reset */ uint8_t : 1; /* (reserved) */ uint8_t PT0CEVT : 1; /*!< PT0 count event */ uint8_t PT0UPEC : 1; uint8_t PT0UPES : 1; uint8_t : 8; /* (reserved) */ uint8_t PT1RC : 1; uint8_t PT1RS : 1; uint8_t PT1RST : 1; /*!< PT1 reset */ uint8_t PT1DTR : 1; /*!< PT1 dead-time counter reset */ uint8_t : 1; /* (reserved) */ uint8_t PT1CEVT : 1; /*!< PT1 count event */ uint8_t PT1UPEC : 1; uint8_t PT1UPES : 1; uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } CTRL0R; /* +0x010 */ union { struct { uint8_t PT0PRES : 4; /*!< Prescaler select */ uint8_t PT0R : 1; /*!< Timer PT0 run bit */ uint8_t PT0UPE : 1; /*!< Timer PT0 update enable */ uint8_t PT0CDWN : 1; /*!< Count direction of timer PT0 */ uint8_t PT0MODE : 1; /*!< PT0 operating mode */ uint8_t PT0CIN : 2; /*!< Input event select for PT0 counting */ uint8_t PT0SSE : 1; /*!< PT0 single shot enable */ uint8_t PT0HRSEL : 2; /*!< PT0 hardware run selection */ uint8_t : 3; /* (reserved) */ uint8_t PT1PRES : 4; /*!< Prescaler select */ uint8_t PT1R : 1; /*!< Timer PT1 run bit */ uint8_t PT1UPE : 1; /*!< Timer PT1 update enable */ uint8_t PT1CDWN : 1; /*!< Count direction of timer PT1 */ uint8_t PT1MODE : 1; /*!< PT1 operating mode */ uint8_t PT1CIN : 2; /*!< Input event select for PT1 counting */ uint8_t PT1SSE : 1; /*!< PT1 single shot enable */ uint8_t PT1HRSEL : 2; /*!< PT1 hardware run selection */ uint8_t CC1CNTS : 1; /*!< Compare Channel 1 counter selection */ uint8_t CC2CNTS : 1; /*!< Compare Channel 2 counter selection */ uint8_t CC3CNTS : 1; /*!< Compare Channel 3 counter selection */ }; uint32_t WORD; } CTRL1R; /* +0x014 */ union { struct { uint8_t PT1TES : 4; uint8_t PT1TED : 2; uint8_t : 2; /* (reserved) */ uint32_t : 24; /* (reserved) */ }; uint32_t WORD; } TRIGR; /* +0x018 */ union { struct { uint8_t PT0DT : 8; uint8_t PT1DT : 8; uint8_t CCXDTE : 8; uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } DTCR; /* +0x01C */ union { struct { uint16_t PFALL0 : 16; /*!< State Pulse Fall CC0 */ uint16_t PRISE0 : 16; /*!< State Pulse Rise CC0 */ }; uint32_t WORD; } PULSE0R; /* +0x020 */ union { struct { uint16_t PFALL1 : 16; /*!< State Pulse Fall CC1 */ uint16_t PRISE1 : 16; /*!< State Pulse Rise CC1 */ }; uint32_t WORD; } PULSE1R; /* +0x024 */ union { struct { uint16_t PFALL2 : 16; /*!< State Pulse Fall CC2 */ uint16_t PRISE2 : 16; /*!< State Pulse Rise CC2 */ }; uint32_t WORD; } PULSE2R; /* +0x028 */ union { struct { uint16_t PFALL3 : 16; /*!< State Pulse Fall CC3 */ uint16_t PRISE3 : 16; /*!< State Pulse Rise CC3 */ }; uint32_t WORD; } PULSE3R; /* +0x02C */ union { struct { uint8_t CCXCS : 8; uint8_t CC00PS : 1; uint8_t CC01PS : 1; uint8_t CC10PS : 1; uint8_t CC11PS : 1; uint8_t CC20PS : 1; uint8_t CC21PS : 1; uint8_t CC30PS : 1; uint8_t CC31PS : 1; uint8_t CC30IM : 8; uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } CMPSTATR; /* +0x030 */ union { struct { uint8_t CCXCSS : 8; uint8_t CCXCSC : 8; uint16_t : 16; /* (reserved) */ }; uint32_t WORD; } CMPMDFIR; /* +0x034 */ uint8_t PSL; /* +0x038 */ uint8_t _RESERVED_39[3]; /* +0x039 */ union { struct { uint8_t SWSEL : 3; uint8_t : 1; /* (reserved) */ uint8_t SWSYNC : 2; uint8_t : 2; /* (reserved) */ uint8_t MCUPEPT0U : 1; uint8_t MCUPEPT0D : 1; uint8_t MCUPEPT1U : 1; uint8_t MCUPEPT1D : 1; uint8_t : 4; /* (reserved) */ uint16_t : 16; /* (reserved) */ }; uint32_t WORD; } MCCTRLR; /* +0x03C */ union { struct { uint8_t MCPTN : 8; uint8_t : 1; /* (reserved) */ uint8_t NTIF : 1; uint8_t : 6; /* (reserved) */ uint8_t MCPTNS : 8; uint8_t MCUPR : 8; }; uint32_t WORD; } MCOUTR; /* +0x040 */ union { struct { uint8_t TRPSCM : 2; uint8_t TRPFCM : 1; uint8_t : 5; /* (reserved) */ uint8_t TRPEN : 8; uint8_t TRPPEN : 1; uint8_t OCPFAST : 1; uint8_t : 2; /* (reserved) */ uint8_t OCPFILTS : 4; uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } TRPCTRLR; /* +0x044 */ union { struct { uint8_t CCXMODEN : 8; uint8_t PT1MODEN : 8; uint8_t MCEN : 8; uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } MODCTRLR; /* +0x048 */ union { struct { uint8_t PWM0RMP : 2; /*!< PWM0 remap selection */ uint8_t : 2; /* (reserved) */ uint8_t PWM1RMP : 2; /*!< PWM1 remap selection */ uint8_t : 2; /* (reserved) */ uint8_t PWM2RMP : 2; /*!< PWM2 remap selection */ uint8_t : 2; /* (reserved) */ uint8_t PWM3RMP : 2; /*!< PWM3 remap selection */ uint8_t : 2; /* (reserved) */ uint16_t : 16; /* (reserved) */ }; uint32_t WORD; } CHREMAPR; /* +0x04C */ union { struct { uint16_t CMPTRIG0V : 16; /*!< Trigger0 Compare Value */ uint8_t TRIG0PT : 1; /*!< Trigger0 Compare Counter Selection */ uint8_t : 3; /* (reserved) */ uint8_t TRIG0MD : 1; /*!< Trigger0 Compare Mode */ uint8_t : 3; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } CMPTRIG0R; /* +0x050 */ union { struct { uint16_t CMPTRIG1V : 16; /*!< Trigger1 Compare Value */ uint8_t TRIG1PT : 1; /*!< Trigger1 Compare Counter Selection */ uint8_t : 3; /* (reserved) */ uint8_t TRIG1MD : 1; /*!< Trigger1 Compare Mode */ uint8_t : 3; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } CMPTRIG1R; /* +0x054 */ union { struct { uint8_t CC0INTOL : 2; /*!< CC0 interrupt output line selection */ uint8_t CC1INTOL : 2; /*!< CC1 interrupt output line selection */ uint8_t CC2INTOL : 2; /*!< CC2 interrupt output line selection */ uint8_t CC3INTOL : 2; /*!< CC3 interrupt output line selection */ uint8_t PT0INTOL : 2; /*!< PT0 interrupt output line selection */ uint8_t PT1INTOL : 2; /*!< PT1 interrupt output line selection */ uint8_t MCUPFINTOL : 2; /*!< MCUPF interrupt output line selection */ uint8_t TRPINTOL : 2; /*!< TRPIS interrupt output line selection */ uint8_t CT0FINTOL : 2; /*!< CT0F interrupt output line selection */ uint8_t CT1FINTOL : 2; /*!< CT1F interrupt output line selection */ uint8_t : 4; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } INTOLR; /* +0x058 */ union { struct { uint8_t CCXRIE : 4; /*!< CCx Rise-Match interrupt enable */ uint8_t CCXFIE : 4; /*!< CCx Fall-Match interrupt enable */ uint8_t PTXOMIE : 2; /*!< PTx One-Match interrupt enable */ uint8_t PTXPMIE : 2; /*!< PTx Period-Match interrupt enable */ uint8_t MCUPFIE : 1; /*!< Multi-channel mode updated interrupt enable */ uint8_t : 2; /* (reserved) */ uint8_t TRPIE : 1; /*!< Trap interrupt enable */ uint8_t CT0IE : 1; /*!< Compare Trigger0 interrupt enable */ uint8_t CT1IE : 1; /*!< Compare Trigger1 interrupt enable */ uint8_t : 6; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } INTCTRLR; /* +0x05C */ union { struct { uint8_t CCXRS : 4; /*!< CCx Rise-Match Flag Set */ uint8_t CCXFS : 4; /*!< CCx Fall-Match Flag Set */ uint8_t PTXOMS : 2; /*!< PTx One-Match Flag Set */ uint8_t PTXPMS : 2; /*!< PTx Period-Match Flag Set */ uint8_t MCUPFS : 1; /*!< Multi-channel mode updated Flag Set */ uint8_t : 2; /* (reserved) */ uint8_t TRPISS : 1; /*!< Trap Interrupt Status Set */ uint8_t CT0FS : 1; /*!< Compare Trigger0 Interrupt Status Set */ uint8_t CT1FS : 1; /*!< Compare Trigger1 Interrupt Status Set */ uint8_t : 6; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } INTSETR; /* +0x060 */ union { struct { uint8_t CCXRC : 4; /*!< CCx Rise-Match Flag Clear */ uint8_t CCXFC : 4; /*!< CCx Fall-Match Flag Clear */ uint8_t PTXOMC : 2; /*!< PTx One-Match Flag Clear */ uint8_t PTXPMC : 2; /*!< PTx Period-Match Flag Clear */ uint8_t MCUPFC : 1; /*!< Multi-channel mode updated Flag Clear */ uint8_t TRPFC : 1; /*!< Trap Flag Clear */ uint8_t : 1; /* (reserved) */ uint8_t TRPISC : 1; /*!< Trap Interrupt Status Clear */ uint8_t CT0FC : 1; /*!< Compare Trigger0 Interrupt Status Clear */ uint8_t CT1FC : 1; /*!< Compare Trigger1 Interrupt Status Clear */ uint8_t : 6; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } INTCLRR; /* +0x064 */ union { struct { uint8_t CCXR : 4; /*!< CCx Rise-Match Flag */ uint8_t CCXF : 4; /*!< CCx Fall-Match Flag */ uint8_t PTXOM : 2; /*!< PTx One-Match Flag */ uint8_t PTXPM : 2; /*!< PTx Period-Match Flag */ uint8_t MCUPF : 1; /*!< Multi-channel mode updated Flag */ uint8_t TRPF : 1; /*!< Trap Flag */ uint8_t TRPS : 1; /*!< Trap State */ uint8_t TRPIS : 1; /*!< Trap Interrupt Status */ uint8_t CT0F : 1; /*!< Compare trigger0 Flag */ uint8_t CT1F : 1; /*!< Compare trigger1 Flag */ uint8_t : 6; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } INTRAWSTATR; /* +0x068 */ union { struct { uint8_t CCXRIRQ : 4; /*!< Corresponding CCx Rise-Match interrupt active */ uint8_t CCXFIRQ : 4; /*!< Corresponding CCx Fall-Match interrupt active */ uint8_t PTXOMIRQ : 2; /*!< Corresponding PTx One-Match interrupt active */ uint8_t PTXPMIRQ : 2; /*!< Corresponding PTx Period-Match interrupt active */ uint8_t MCUPFIRQ : 1; /*!< Multi-channel mode updated interrupt active */ uint8_t : 2; /* (reserved) */ uint8_t TRPIRQ : 1; /*!< Trap interrupt active */ uint8_t CT0IRQ : 1; /*!< Compare trigger0 interrupt active */ uint8_t CT1IRQ : 1; /*!< Compare trigger1 interrupt active */ uint8_t : 6; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } INTACTSTATR; /* +0x06C */ } PWM_SFRS_t; /* -------- End of section using anonymous unions and disabling warnings -------- */ #if defined (__CC_ARM) #pragma pop #elif defined (__ICCARM__) /* leave anonymous unions enabled */ #elif (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning restore #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /** * @brief The starting address of PWM SFRS. */ #define PWM_SFRS ((__IO PWM_SFRS_t *)0x40010000) #endif /* end of __PWM_SFR_H__ section */