/**
 * @copyright 2023 indie Semiconductor
 *
 * This file is proprietary to indie Semiconductor.
 * All rights reserved. Reproduction or distribution, in whole
 * or in part, is forbidden except by express written permission
 * of indie Semiconductor.
 *
 * @file mathdiv_sfr.h
 */

#ifndef MATHDIV_SFR_H__
#define MATHDIV_SFR_H__

#include <stdint.h>

/* -------  Start of section using anonymous unions and disabling warnings  ------- */
#if   defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

/**
 * @brief A structure to represent Special Function Registers for MATHDIV.
 */
typedef struct {

  union {
    struct {
      uint8_t  DVDRC                    :  2; /*!< <b>Dividend Register Result Chaining</b> */
      uint8_t                           :  1; /*   (reserved) */
      uint8_t  DVSRC                    :  2; /*!< <b>Dividend Register Result Chaining</b> */
      uint8_t                           :  3; /*   (reserved) */
      uint8_t                           :  8; /*   (reserved) */
      uint8_t  SUSCFG                   :  8; /*!< <b>Suspend Mode Configuration</b> */
      uint8_t                           :  7; /*   (reserved) */
      uint8_t  MATHEN                   :  1; /*!< <b>Enable Math Module</b> */
    };
    uint32_t WORD;
  } GLBCON; /* +0x000 */

  union {
    struct {
      uint8_t  DIVEOCQ                  :  1;
      uint8_t  DIVERRQ                  :  1;
      uint8_t                           :  6; /*   (reserved) */
      uint8_t  DIVEOC                   :  1;
      uint8_t  DIVERR                   :  1;
      uint8_t                           :  6; /*   (reserved) */
      uint16_t                          : 16; /*   (reserved) */
    };
    uint32_t WORD;
  } DIVINTSTATR; /* +0x004 */

  union {
    struct {
      uint8_t  DIVEOCS                  :  1;
      uint8_t  DIVERRS                  :  1;
      uint8_t                           :  6; /*   (reserved) */
      uint8_t  DIVEOCC                  :  1;
      uint8_t  DIVERRC                  :  1;
      uint8_t                           :  6; /*   (reserved) */
      uint8_t  DIVEOCIE                 :  1;
      uint8_t  DIVERRIE                 :  1;
      uint8_t                           :  6; /*   (reserved) */
      uint8_t                           :  8; /*   (reserved) */
    };
    uint32_t WORD;
  } DIVINTPROCR; /* +0x008 */

  uint32_t DVDVAL;                            /* +0x00C */

  uint32_t DVSVAL;                            /* +0x010 */

  uint32_t QUOTVAL;                           /* +0x014 */

  uint32_t RMDVAL;                            /* +0x018 */

  uint8_t  BUSY;                              /* +0x01C */
  uint8_t  _RESERVED_1D[3];                   /* +0x01D */

  union {
    struct {
      uint8_t  ST                       :  1; /*!< <b>Start Bit</b> */
      uint8_t  STMODE                   :  1; /*!< <b>Start Mode</b> */
      uint8_t  USIGN                    :  1; /*!< <b>Unsigned Division Enable</b> */
      uint8_t  DIVMODE                  :  2; /*!< <b>Division Mode</b> */
      uint8_t                           :  3; /*   (reserved) */
      uint8_t  QSCNT                    :  5; /*!< <b>Quotient Shift Count</b> */
      uint8_t                           :  2; /*   (reserved) */
      uint8_t  QSDIR                    :  1; /*!< <b>Quotient Shift Direction</b> */
      uint8_t  DVDSLC                   :  8; /*!< <b>Dividend Shift Left Count</b> */
      uint8_t  DVSSRC                   :  8; /*!< <b>Divisor Shift Right Count</b> */
    };
    uint32_t WORD;
  } DIVCON; /* +0x020 */

} MATHDIV_SFRS_t;

/* --------  End of section using anonymous unions and disabling warnings  -------- */
#if   defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

/**
 * @brief The starting address of MATHDIV SFRS.
 */
#define MATHDIV_SFRS ((__IO MATHDIV_SFRS_t *)0x40021800)

#endif /* end of __MATHDIV_SFR_H__ section */