#ifndef META_H__
#define META_H__

// declare an enumerated type that can be used to refer to interrupts by name, e.g. in calls to the NVIC configuration
// functions - the definitions here must match the vector table positions, offset so that IRQ0 (the 1st ASIC IRQ) has
// the value 0...
//
typedef enum IRQn
{
  // Cortex-M0 core exceptions...
  Reset_IRQn        = -15,
  NMI_IRQn          = -14,       
  HardFault_IRQn    = -13,
  SVC_IRQn          = -5, 
  PendSV_IRQn       = -2, 
  SysTick_IRQn      = -1, 
  // ASIC-specific IRQs... (should match the vector defined in dig_meta_top.sv)
  IOCTRLA_IRQn      = 0, 
  OVTEMP_IRQn       = 1, 
  GPIO_IRQn         = 2, 
  PWM_AUX_IRQn      = 3, 
  GT4_5_IRQn        = 4, 
  WUTIMER_IRQn      = 5, 
  WatchdogA_IRQn    = 6, 
  ADC_IRQn          = 7,
  SPI_IRQn          = 8,
  WULIN_IRQn        = 9,
  UART0_IRQn        = 10,
  DIV_IRQn          = 11,
  LIN_IRQn          = 12,
  FLASH_IRQn        = 13,
  SRAM_ECCC_IQn     = 14,
  GT1_IRQn          = 15,
  GT2_IRQn          = 16,
  GT3_IRQn          = 17,
  CT2_IRQn          = 18,
  CT3_IRQn          = 19,
  CT4_IRQn          = 20,
  CT5_IRQn          = 21,
  CT6_IRQn          = 22,
  CR_IRQn           = 23,
  PWM_INTOL0_IRQn   = 24,
  PWM_INTOL1_IRQn   = 25,
  PWM_INTOL2_IRQn   = 26,
  PWM_INTOL3_IRQn   = 27,
  BOR_IRQn          = 28, 
  UV_OV_IRQn        = 29, 
  CSP_OCP_IRQn      = 30, 
  Lullaby_IRQn      = 31

} IRQn_Type;
//
// and define a tell-tale macro that will prevent the clough.h header from attempting to re-define this with the
// default (non-ASIC-specific) version...
//
#define __IRQn_Type

#define TRUE                    (1U)
#define FALSE                   (0U)

#include <stdint.h>
#include "sfrs/meta_sfr.h"
#include "verne.h"

#endif