/** * @copyright 2022 indie Semiconductor * * This file is proprietary to indie Semiconductor. * All rights reserved. Reproduction or distribution, in whole * or in part, is forbidden except by express written permission * of indie Semiconductor. * * @file ctt_sfr.h */ #ifndef CTT_SFR_H__ #define CTT_SFR_H__ #include /* ------- Start of section using anonymous unions and disabling warnings ------- */ #if defined (__CC_ARM) #pragma push #pragma anon_unions #elif defined (__ICCARM__) #pragma language=extended #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wc11-extensions" #pragma clang diagnostic ignored "-Wreserved-id-macro" #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning 586 #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /** * @brief A structure to represent Special Function Registers for CTT. */ typedef struct { union { struct { uint8_t SELCT2IN : 1; /*!< Select for CT2IN */ uint8_t SELCT2EUD : 1; /*!< Select for CT2EUD */ uint8_t SELCT3IN : 2; /*!< Select for CT3IN */ uint8_t SELCT3EUD : 1; /*!< Select for CT3EUD */ uint8_t : 1; /* (reserved) */ uint8_t SELCT4IN : 2; /*!< Select for CT4IN */ uint8_t SELCT4EUD : 1; /*!< Select for CT4EUD */ uint8_t : 1; /* (reserved) */ uint8_t SELCT5IN : 1; /*!< Select for CT5IN */ uint8_t SELCT5EUD : 1; /*!< Select for CT5EUD */ uint8_t SELCT6IN : 1; /*!< Select for CT6IN */ uint8_t SELCT6EUD : 1; /*!< Select for CT6EUD */ uint8_t SELCAPIN : 2; /*!< Select for CAPIN */ uint16_t : 16; /* (reserved) */ }; uint32_t WORD; } CTTINSR; /* +0x000 */ union { struct { uint8_t CT2I : 3; /*!< Timer CT2 Input Parameter Selection */ uint8_t CT2M : 3; /*!< Timer CT2 Mode Control */ uint8_t CT2R : 1; /*!< Timer CT2 Run Bit */ uint8_t CT2UD : 1; /*!< Timer CT2 Up/Down Control */ uint8_t CT2EUDE : 1; /*!< Timer CT2 External Up/Down Enable */ uint8_t CT2RC : 1; /*!< Timer CT2 Remote Control */ uint8_t : 2; /* (reserved) */ uint8_t CT2IIMIDIS : 1; /*!< Timer CT2 Incrmental Interrupt Disable */ uint8_t CT2EDGE : 1; /*!< Timer CT2 Edge Detection */ uint8_t CT2DIRCH : 1; /*!< Timer CT2 Count Direction Change */ uint8_t CT2DIR : 1; /*!< Timer CT2 Count Direction */ uint8_t CT2PRESHI : 1; /*!< Timer CT2 Prescaler High Bit */ uint8_t : 1; /* (reserved) */ uint8_t CT2EDGEC : 1; /*!< Timer CT2 Edge Detection Clear */ uint8_t : 1; /* (reserved) */ uint8_t CT2DIRCHC : 1; /*!< Timer CT2 Count Direction Change Clear */ uint8_t : 3; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } CT2CTRLR; /* +0x004 */ union { struct { uint8_t CT3I : 3; /*!< Timer CT3 Input Parameter Selection */ uint8_t CT3M : 3; /*!< Timer CT3 Mode Control */ uint8_t CT3R : 1; /*!< Timer CT3 Run Bit */ uint8_t CT3UD : 1; /*!< Timer CT3 Up/Down Control */ uint8_t CT3EUDE : 1; /*!< Timer CT3 External Up/Down Enable */ uint8_t CT3OE : 1; /*!< Timer CT3 Output Enable */ uint8_t CT3OTL : 1; /*!< Timer CT3 Overflow/underflow Toggle Latch */ uint8_t : 1; /* (reserved) */ uint8_t CT3IIMIDIS : 1; /*!< Timer CT3 Incrmental Interrupt Disable */ uint8_t CT3EDGE : 1; /*!< Timer CT3 Edge Detection */ uint8_t CT3DIRCH : 1; /*!< Timer CT3 Count Direction Change */ uint8_t CT3DIR : 1; /*!< Timer CT3 Count Direction */ uint8_t CT3PRESHI : 1; /*!< Timer CT3 Prescaler High Bit */ uint8_t : 1; /* (reserved) */ uint8_t CT3EDGEC : 1; /*!< Timer CT3 Edge Detection Clear */ uint8_t : 1; /* (reserved) */ uint8_t CT3DIRCHC : 1; /*!< Timer CT3 Count Direction Change Clear */ uint8_t : 3; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } CT3CTRLR; /* +0x008 */ union { struct { uint8_t CT4I : 3; /*!< Timer CT4 Input Parameter Selection */ uint8_t CT4M : 3; /*!< Timer CT4 Mode Control */ uint8_t CT4R : 1; /*!< Timer CT4 Run Bit */ uint8_t CT4UD : 1; /*!< Timer CT4 Up/Down Control */ uint8_t CT4EUDE : 1; /*!< Timer CT4 External Up/Down Enable */ uint8_t CT4RC : 1; /*!< Timer CT4 Remote Control */ uint8_t CLRCT2EN : 1; /*!< Clear Timer CT2 Enable */ uint8_t CLRCT3EN : 1; /*!< Clear Timer CT3 Enable */ uint8_t CT4IIMIDIS : 1; /*!< Timer CT4 Incrmental Interrupt Disable */ uint8_t CT4EDGE : 1; /*!< Timer CT4 Edge Detection */ uint8_t CT4DIRCH : 1; /*!< Timer CT4 Count Direction Change */ uint8_t CT4DIR : 1; /*!< Timer CT4 Count Direction */ uint8_t CT4PRESHI : 1; /*!< Timer CT4 Prescaler High Bit */ uint8_t : 1; /* (reserved) */ uint8_t CT4EDGEC : 1; /*!< Timer CT4 Edge Detection Clear */ uint8_t : 1; /* (reserved) */ uint8_t CT4DIRCHC : 1; /*!< Timer CT4 Count Direction Change Clear */ uint8_t : 3; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } CT4CTRLR; /* +0x00C */ union { struct { uint8_t CT5I : 3; /*!< Timer CT5 Input Parameter Selection */ uint8_t CT5M : 2; /*!< Timer CT5 Mode Control */ uint8_t : 1; /* (reserved) */ uint8_t CT5R : 1; /*!< Timer CT5 Run Bit */ uint8_t CT5UD : 1; /*!< Timer CT5 Up/Down Control */ uint8_t CT5EUDE : 1; /*!< Timer CT5 External Up/Down Enable */ uint8_t CT5RC : 1; /*!< Timer CT5 Remote Control */ uint8_t CT3CTS : 1; /*!< Capture Trigger Selection */ uint8_t : 1; /* (reserved) */ uint8_t CTS : 2; /*!< Register CAPRLD Capture Trigger Selection */ uint8_t CT5CLRE : 1; /*!< Timer CT5 Clear Enable Bit */ uint8_t CT5DIR : 1; /*!< Timer CT5 Count Direction */ uint8_t CT5PRESHI : 1; /*!< Timer CT5 Prescaler High Bit */ uint8_t CT5CE : 1; /*!< Timer CT5 Capture Mode Enable */ uint8_t : 6; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } CT5CTRLR; /* +0x010 */ union { struct { uint8_t CT6I : 3; /*!< Timer CT6 Input Parameter Selection */ uint8_t CT6M : 2; /*!< Timer CT6 Mode Control */ uint8_t : 1; /* (reserved) */ uint8_t CT6R : 1; /*!< Timer CT6 Run Bit */ uint8_t CT6UD : 1; /*!< Timer CT6 Up/Down Control */ uint8_t CT6EUDE : 1; /*!< Timer CT6 External Up/Down Enable */ uint8_t CT6OE : 1; /*!< Timer CT6 Output Enable */ uint8_t CT6OTL : 1; /*!< Timer CT6 Overflow/underflow Toggle Latch */ uint8_t : 3; /* (reserved) */ uint8_t CT6CLRE : 1; /*!< Timer CT6 Clear Enable Bit */ uint8_t CT6DIR : 1; /*!< Timer CT6 Count Direction */ uint8_t CT6PRESHI : 1; /*!< Timer CT6 Prescaler High Bit */ uint8_t CT6RE : 1; /*!< Timer CT6 Reload Mode Enable */ uint8_t : 6; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } CT6CTRLR; /* +0x014 */ uint16_t CAPRLD; /*Reload value or Captured value +0x018 */ uint8_t _RESERVED_1A[2]; /* +0x01A */ uint16_t CT2CV; /*Timer CT2 Current Value +0x01C */ uint8_t _RESERVED_1E[2]; /* +0x01E */ uint16_t CT3CV; /*Timer CT3 Current Value +0x020 */ uint8_t _RESERVED_22[2]; /* +0x022 */ uint16_t CT4CV; /*Timer CT4 Current Value +0x024 */ uint8_t _RESERVED_26[2]; /* +0x026 */ uint16_t CT5CV; /*Timer CT5 Current Value +0x028 */ uint8_t _RESERVED_2A[2]; /* +0x02A */ uint16_t CT6CV; /*Timer CT6 Current Value +0x02C */ uint8_t _RESERVED_2E[2]; /* +0x02E */ union { struct { uint8_t CT2IE : 1; /*!< CT2 interrupt enable */ uint8_t CT3IE : 1; /*!< CT3 interrupt enable */ uint8_t CT4IE : 1; /*!< CT4 interrupt enable */ uint8_t CT5IE : 1; /*!< CT5 interrupt enable */ uint8_t CT6IE : 1; /*!< CT6 interrupt enable */ uint8_t CRIE : 1; /*!< CAPREL capture interrupt enable */ uint8_t : 2; /* (reserved) */ uint8_t : 8; /* (reserved) */ uint8_t CT2IC : 1; /*!< CT2 interrupt clear */ uint8_t CT3IC : 1; /*!< CT3 interrupt clear */ uint8_t CT4IC : 1; /*!< CT4 interrupt clear */ uint8_t CT5IC : 1; /*!< CT5 interrupt clear */ uint8_t CT6IC : 1; /*!< CT6 interrupt clear */ uint8_t CRIC : 1; /*!< CAPREL capture interrupt clear */ uint8_t : 2; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } INTCTRLR; /* +0x030 */ union { struct { uint8_t CT2IF : 1; /*!< CT2 interrupt flag */ uint8_t CT3IF : 1; /*!< CT3 interrupt flag */ uint8_t CT4IF : 1; /*!< CT4 interrupt flag */ uint8_t CT5IF : 1; /*!< CT5 interrupt flag */ uint8_t CT6IF : 1; /*!< CT6 interrupt flag */ uint8_t CRIF : 1; /*!< CAPREL capture interrupt flag */ uint8_t : 2; /* (reserved) */ uint8_t : 8; /* (reserved) */ uint8_t CT2IRQ : 1; /*!< CT2 interrupt active */ uint8_t CT3IRQ : 1; /*!< CT3 interrupt active */ uint8_t CT4IRQ : 1; /*!< CT4 interrupt active */ uint8_t CT5IRQ : 1; /*!< CT5 interrupt active */ uint8_t CT6IRQ : 1; /*!< CT6 interrupt active */ uint8_t CRIRQ : 1; /*!< CAPREL capture interrupt active */ uint8_t : 2; /* (reserved) */ uint8_t : 8; /* (reserved) */ }; uint32_t WORD; } INTSTATR; /* +0x034 */ } CTT_SFRS_t; /* -------- End of section using anonymous unions and disabling warnings -------- */ #if defined (__CC_ARM) #pragma pop #elif defined (__ICCARM__) /* leave anonymous unions enabled */ #elif (__ARMCC_VERSION >= 6010050) #pragma clang diagnostic pop #elif defined (__GNUC__) /* anonymous unions are enabled by default */ #elif defined (__TMS470__) /* anonymous unions are enabled by default */ #elif defined (__TASKING__) #pragma warning restore #elif defined (__CSMC__) /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif /** * @brief The starting address of CTT SFRS. */ #define CTT_SFRS ((__IO CTT_SFRS_t *)0x40010400) #endif /* end of __CTT_SFR_H__ section */