K74B/app_Indie/drivers/hdf/sfrs/syscfg_sfr.h

/**
 * @copyright 2022 indie Semiconductor
 *
 * This file is proprietary to indie Semiconductor.
 * All rights reserved. Reproduction or distribution, in whole
 * or in part, is forbidden except by express written permission
 * of indie Semiconductor.
 *
 * @file syscfg_sfr.h
 */

#ifndef SYSCFG_SFR_H__
#define SYSCFG_SFR_H__

#include <stdint.h>

/* -------  Start of section using anonymous unions and disabling warnings  ------- */
#if   defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

/**
 * @brief A structure to represent Special Function Registers for SYSCFG.
 */
typedef struct {

  union {
    struct {
      uint8_t  GT1INS                   :  1; /*!< GT1IN Selection */
      uint8_t  GT2INS                   :  1; /*!< GT2IN Selection */
      uint8_t  GT3INS                   :  1; /*!< GT3IN Selection */
      uint8_t  GT4INS                   :  1; /*!< GT4IN Selection */
      uint8_t  GT5INS                   :  1; /*!< GT5IN Selection */
      uint8_t                           :  3; /*   (reserved) */
      uint8_t  GT1EXTS                  :  2; /*!< GT1EXT Selection */
      uint8_t  GT2EXTS                  :  1; /*!< GT2EXT Selection */
      uint8_t  GT3EXTS                  :  1; /*!< GT3EXT Selection */
      uint8_t  GT4EXTS                  :  1; /*!< GT4EXT Selection */
      uint8_t  GT5EXTS                  :  1; /*!< GT5EXT Selection */
      uint8_t                           :  2; /*   (reserved) */
      uint8_t  GT1EXTC                  :  1; /*!< GT1EXT Input Control */
      uint8_t  GT2EXTC                  :  1; /*!< GT2EXT Input Control */
      uint8_t  GT3EXTC                  :  1; /*!< GT3EXT Input Control */
      uint8_t                           :  5; /*   (reserved) */
      uint8_t  GT3TRIGS                 :  8; /*!< GT3 Trigger Select */
    };
    uint32_t WORD;
  } GTINSR; /* +0x000 */

  union {
    struct {
      uint8_t  PT0HRS                   :  1; /*!< PT0HR Selection */
      uint8_t  PT1HRS                   :  1; /*!< PT1HR Selection */
      uint8_t                           :  6; /*   (reserved) */
      uint8_t                           :  8; /*   (reserved) */
      uint8_t  PT0HRC                   :  1; /*!< PT0HR Input Control */
      uint8_t  PT1HRC                   :  1; /*!< PT1HR Input Control */
      uint8_t                           :  6; /*   (reserved) */
      uint8_t                           :  8; /*   (reserved) */
    };
    uint32_t WORD;
  } PWMINSR; /* +0x004 */

  uint8_t  CTINS;                             /*<! CTT Trigger Input Selection +0x008 */
  uint8_t  _RESERVED_09[3];                   /* +0x009 */

  union {
    struct {
      uint16_t SRAMECCADDR              : 16; /*!< SRAM ECC Error Address */
      uint8_t  SRAMECCC                 :  1; /*!< SRAM ECC correction */
      uint8_t  SRAMECCD                 :  1; /*!< SRAM ECC detection */
      uint8_t  FLSECCDNMI               :  1; /*!< Flash ECC detection Indication */
      uint8_t                           :  4; /*   (reserved) */
      uint8_t  SRAMECCCIE               :  1; /*!< SRAM ECC correction interrupt enable */
      uint8_t                           :  7; /*   (reserved) */
      uint8_t  SRAMECCDIS               :  1; /*!< SRAM ECC Disable bit */
    };
    uint32_t WORD;
  } SRAMCFGR; /* +0x00C */

  union {
    struct {
      uint8_t  SRAM_RAWACC_EN           :  8; /*!< SRAM Raw Access Enable */
      uint8_t                           :  8; /*   (reserved) */
      uint8_t  WR_ECC_RAW               :  8; /*!< ECC Raw Value for Write */
      uint8_t  RD_ECC_RAW               :  8; /*!< ECC Raw Value for Read */
    };
    uint32_t WORD;
  } SRAMRACR; /* +0x010 */

  uint16_t SRAMWP;                            /*<! SRAM Write Protection +0x014 */
  uint8_t  _RESERVED_16[2];                   /* +0x016 */

  union {
    struct {
      uint8_t  IVTBADDR                 :  8; /*!< Interrupt Vector Table Base Address */
      uint8_t                           :  8; /*   (reserved) */
      uint8_t  IVTRAMSEL                :  8; /*!< IVT SRAM Selection */
      uint8_t                           :  8; /*   (reserved) */
    };
    uint32_t WORD;
  } M0IVTR; /* +0x018 */

} SYSCFG_SFRS_t;

/* --------  End of section using anonymous unions and disabling warnings  -------- */
#if   defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif

/**
 * @brief The starting address of SYSCFG SFRS.
 */
#define SYSCFG_SFRS ((__IO SYSCFG_SFRS_t *)0x40020000)

#endif /* end of __SYSCFG_SFR_H__ section */