191 lines
6.8 KiB
C
191 lines
6.8 KiB
C
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#include <appConfig.h>
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#if ENABLE_FUNCTION_VALIDATION == 1
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#include <meta.h>
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#include <validation.h>
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#include <gpio_device.h>
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#include <adc_device.h>
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#include <clock_device.h>
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#include <lin_device.h>
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#include <hwProtection.h>
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#include <adc_device.h>
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#include <pwm_aux_device.h>
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SYSCTRLA_SFRS_t sysCtrl;
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void PWM0_0(void);
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void SPI(void);
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void UART0(void);
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void CT3_COUNTER(void);
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uint16_t PT0data=0;
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uint16_t Rdata_SPI=0;
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uint16_t Tdata_UART0=0X55,Rdata_UART0=0;
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uint16_t CT3CV_data=0;
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void PWM0_0(void)
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{
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SYSCTRLA_SFRS->DEBUG_ACCESS_KEY.DEBUG_ACCESS_KEY = 0X05U;
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IOCTRLA_SFRS->PORT_GROUP_MUX[1] |= (uint32_t)0x02<<20; // PB5 0x2: PWM0_0.
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IOCTRLA_SFRS->PORT_GROUP_MUX[1] |= (uint32_t)0x02<<24; //PB6 0x2: PWM0_1.
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PWM_SFRS->CTRL0R.PT0RC = 1U;//0x1: PT0R is cleared, PT0 stops counting
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PWM_SFRS->CTRL1R.CC1CNTS = 0;
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PWM_SFRS->CTRL1R.CC2CNTS = 0;
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PWM_SFRS->CTRL1R.CC3CNTS = 0;
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PWM_SFRS->CTRL1R.PT0PRES = 1;//0x1: Divide by 2 48Mhz/2 = 24Mhz
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PWM_SFRS->CTRL1R.PT0MODE = 0;//0x0: Edge_aligned_mode:
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PWM_SFRS->PT0PERIOD = 100U*48U; //100us*2 = 5Khz
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PWM_SFRS->DTCR.CCXDTE = 0;//0x0: DISABLED: Dead-time generation is disabled.
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PWM_SFRS->DTCR.PT1DT = 0;
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PWM_SFRS->DTCR.PT0DT = 0;
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PWM_SFRS->CHREMAPR.PWM0RMP = 0;//0x0: Select CC0
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PWM_SFRS->CHREMAPR.PWM1RMP = 0;//0x0: Select CC0
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PWM_SFRS->CHREMAPR.PWM2RMP = 0;//0x0: Select CC0
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PWM_SFRS->CHREMAPR.PWM3RMP = 0;//0x0: Select CC0
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PWM_SFRS->CMPSTATR.CC00PS = 0;//0x0: CC0_0 drives passive level while CC0CS is 0, i.e. driven by CC0CS
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PWM_SFRS->CMPSTATR.CC01PS = 0;
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PWM_SFRS->CMPSTATR.CC10PS = 0;//0x0: CC1_0 drives passive level while CC0CS is 0, i.e. driven by CC0CS
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PWM_SFRS->CMPSTATR.CC11PS = 0;
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PWM_SFRS->CMPSTATR.CC20PS = 0;//0x0: CC2_0 drives passive level while CC0CS is 0, i.e. driven by CC0CS
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PWM_SFRS->CMPSTATR.CC21PS = 0;
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PWM_SFRS->CMPSTATR.CC30PS = 0;//0x0: CC3_0 drives passive level while CC0CS is 0, i.e. driven by CC0CS
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PWM_SFRS->CMPSTATR.CC31PS = 0;
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PWM_SFRS->PSL = 0X0;//0x0: Level_0: The passive level is 0
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PWM_SFRS->MODCTRLR.MCEN = 0;//0x1: ENABLED: The modulation of the corresponding output signal by the multi-channel pattern according to bit field MCPTN is enabled
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PWM_SFRS->MODCTRLR.CCXMODEN = 0XFF;//0x1: ENABLED: The modulation of the corresponding output signal by CC0~3 pattern is enabled
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PWM_SFRS->MCOUTR.MCUPR= 1;//0x1: By_software: Bit field MCPTN is updated by MCPTNS immediately
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PWM_SFRS->MCOUTR.MCPTNS = 0XFF;
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PWM_SFRS->PULSE0R.PRISE0 = 0U;
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PWM_SFRS->PULSE0R.PFALL0 = 2000U;
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PWM_SFRS->CTRL0R.PT0UPES = 1;//0x1: PT0UPE is set, enabling update
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PWM_SFRS->CTRL0R.PT0RS = 1;//0x1: PT0R is set, PT0 start counting
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while(1){
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PT0data = PWM_SFRS->PT0CV;
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}
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}
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void SPI(void)
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{
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SYSCTRLA_SFRS->DEBUG_ACCESS_KEY.DEBUG_ACCESS_KEY = 0X05U;
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IOCTRLA_SFRS->PORT_GROUP_MUX[0] |= (uint32_t)0x03<<20; //PA5 0x3: SCK.
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IOCTRLA_SFRS->PORT_GROUP_MUX[0] |= (uint32_t)0x03<<16; //PA4 0x3: MOSI.
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IOCTRLA_SFRS->PORT_GROUP_MUX[0] |= (uint32_t)0x03<<12; //PA3 0x3: MISO
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SPI_SFRS->SPICTRL.FIFOSOFTRESET = 1;
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while(SPI_SFRS->SPICTRL.FIFOSOFTRESET == 1);
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SPI_SFRS->SPICTRL.SCKEXT = 2;
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SPI_SFRS->SPICTRL.SPR = 3;//{10, 11}: System Clock / 4096 11.718KHZ
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SPI_SFRS->SPICTRL.LPBK = 1;//0x1: Loopback enable. Set to enable loopback
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SPI_SFRS->SPICTRL.ICNT = 0;//0x0: Interrupt is set after every completed transfer
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SPI_SFRS->SPICTRL.CPOL = 0;//
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SPI_SFRS->SPICTRL.CPHA = 0;//CPHA
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SPI_SFRS->SPICTRL.ENA_REQ = 1;
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while(SPI_SFRS->SPISTATUS.TXFIFOEMPTY == 1)
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{
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SPI_SFRS->TXDATA = 0x55;
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}
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if(SPI_SFRS->SPISTATUS.RXFIFOEMPTY == 0){
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Rdata_SPI = SPI_SFRS->RXDATA;
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}
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}
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void UART0(void)//<2F><>loop<6F><70><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>TX<54><58><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>źţ<C5BA><C5A3>ر<EFBFBD>ʱ<EFBFBD><CAB1>
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{
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SYSCTRLA_SFRS->DEBUG_ACCESS_KEY.DEBUG_ACCESS_KEY = 0X05U;
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IOCTRLA_SFRS->PORT_GROUP_MUX[1] |= (uint32_t)0x02U; //PB0 0x2: TXD.
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IOCTRLA_SFRS->PORT_GROUP_MUX[1] |= (uint32_t)0x03U<<12; //PB3 0x3: RXD.
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UART0_SFRS->MSGCTRL.ENABLE = 0U;//0:Disable UART0
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UART0_SFRS->MSGCTRL.LOOPENA = 0U;//Loopback enable. Set to enable loopback
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UART0_SFRS->MSGCTRL.BREAKENA = 0U;
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UART0_SFRS->MSGCTRL.STICKENA = 0U;
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UART0_SFRS->MSGCTRL.PARODD = 0U;//0x0: ODD Parity
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UART0_SFRS->MSGCTRL.PARENA = 1U;//Parity enable.
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UART0_SFRS->MSGCTRL.STOP = 0U;//0x0: One stop bit
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UART0_SFRS->MSGCTRL.SIZE = 3U;//Transmission word size.0x3: 8-bit
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UART0_SFRS->MSGCTRL.TXXFERCNTCLR = 1U;//
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UART0_SFRS->MSGCTRL.RXXFERCNTCLR = 1U;
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UART0_SFRS->MSGCTRL.UFIFOSOFTRESET = 1U;
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//Baud_rate = Fclk/OSR/(BAUDDIV+1+FDIV/8)
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//48000000/16/(311+1+4/8)= 9600
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UART0_SFRS->UARTBAUD.URETARD = 1;
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UART0_SFRS->UARTBAUD.UADVANCE = 1;
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UART0_SFRS->UARTBAUD.OSR = 16;//Over-sampling ratio. Valid OSR Range: 6 to 16.
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UART0_SFRS->UARTBAUD.BAUDDIV = 311;//Baud rate divider.16bits
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UART0_SFRS->UARTBAUD.FDIV = 4;//Fractional divider.3bits
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UART0_SFRS->UARTFIFO.TXMULTIPLEXFERDONECNT = 4;//Transmit Data Count Interrupt. Valid Range: 1 to 16
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UART0_SFRS->MSGCTRL.ENABLE = 1U;
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while(UART0_SFRS->MSGCTRL.ENABLE_STS == 0);
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Tdata_UART0 = 0X55;
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UART0_SFRS->DATA.BYTE = Tdata_UART0;
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while(UART0_SFRS->UARTINT.STATUS.TXDONE == 0U){}
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UART0_SFRS->UARTINT.CLEAR.TXDONE = 1U;
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// Tdata_UART0 = 0X56;
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// UART0_SFRS->DATA.BYTE = Tdata_UART0;
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if(UART0_SFRS->UARTINT.STATUS.RXDONE == 1)
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{
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Rdata_UART0 = UART0_SFRS->DATA.BYTE;
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}
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}
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void CT3_COUNTER(void)
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{
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SYSCTRLA_SFRS->DEBUG_ACCESS_KEY.DEBUG_ACCESS_KEY = 0X05U;
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IOCTRLA_SFRS->PORT_GROUP_MUX[2] |= (uint32_t)0x07U << 12; //PC3 0x7: PAUX[1]
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IOCTRLA_SFRS->PORT_GROUP_MUX[2] |= (uint32_t)0x04U << 16; //PC4 0x4: CT3EUDB
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CTT_SFRS->CTTINSR.SELCT3EUD = 1U;//0x1: Signal CT3EUDB is selected
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CTT_SFRS->CT3CTRLR.CT3R = 0;//0x0: Timer CT3 stops
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CTT_SFRS->CT3CTRLR.CT3EUDE = 0U;//0x0: Count direction is controlled by bit CT3UD; input CT3EUD is ignored
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CTT_SFRS->CT3CTRLR.CT3UD = 0U;//0x0: Up: Timer CT3 counts up
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CTT_SFRS->CT3CTRLR.CT3M = 7U;//0x7: Incremental Interface Mode (Edge Detection Mode)
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CTT_SFRS->CT3CTRLR.CT3I = 2U;//Any transition (rising or falling edge) on CT3EUD
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PWMAUX_Init(GROUP_GPIOC,GPIO_PORT_3,PWMAUX_CH1,PWMAUX_BASE_0,PWMAUX_CLK_DIV_1,1000*48);//1ms
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PWMAUX_SetMatchValue(PWMAUX_CH1, 0, 1000*48/2);//PWMAUX1:PC3
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CTT_SFRS->CT3CTRLR.CT3R = 1;//0x0: Timer CT3 stops
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while(1)
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{
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CT3CV_data = CTT_SFRS->CT3CV;
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}
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}
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void validation_main(void)
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{
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SYSCTRLA_SFRS->DEBUG_ACCESS_KEY.DEBUG_ACCESS_KEY = 0X05U;
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//SYSCTRLA_REG_TRIM_ACCESS_KEY.TRIM_ACCESS_KEY = 0x0EU;
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SYSCTRLA_SFRS->TRIM_ACCESS_KEY.TRIM_ACCESS_KEY = 0x0EU;
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Clock_SystemMainClockInit(SYS_MAIN_CLOCK_DIV);
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while(1);
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}
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#endif
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