移植自K53
This commit is contained in:
commit
28c5f3cf08
4
.gitignore
vendored
Normal file
4
.gitignore
vendored
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@ -0,0 +1,4 @@
|
||||
DefaultBuild
|
||||
/SmartManual Docs
|
||||
/*.mtud
|
||||
/QualityReport(K80,DefaultBuild).txt
|
||||
22
.vscode/c_cpp_properties.json
vendored
Normal file
22
.vscode/c_cpp_properties.json
vendored
Normal file
@ -0,0 +1,22 @@
|
||||
{
|
||||
"configurations": [
|
||||
{
|
||||
"name": "Win32",
|
||||
"includePath": [
|
||||
"${workspaceFolder}/**"
|
||||
],
|
||||
"defines": [
|
||||
"_DEBUG",
|
||||
"UNICODE",
|
||||
"_UNICODE",
|
||||
"__near= "
|
||||
],
|
||||
"windowsSdkVersion": "10.0.18362.0",
|
||||
"compilerPath": "C:\\Program Files (x86)\\Microsoft Visual Studio\\2019\\Community\\VC\\Tools\\MSVC\\14.28.29333\\bin\\Hostx64\\x64\\cl.exe",
|
||||
"cStandard": "c17",
|
||||
"cppStandard": "c++17",
|
||||
"intelliSenseMode": "windows-msvc-x64"
|
||||
}
|
||||
],
|
||||
"version": 4
|
||||
}
|
||||
13
.vscode/settings.json
vendored
Normal file
13
.vscode/settings.json
vendored
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|
||||
{
|
||||
"files.associations": {
|
||||
"r_cg_macrodriver.h": "c",
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||||
"r_cg_userdefine.h": "c",
|
||||
"r_cg_timer.h": "c",
|
||||
"r_cg_port.h": "c",
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||||
"event.h": "c",
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||||
"r_cg_wdt.h": "c",
|
||||
"hwctrl.h": "c",
|
||||
"apptask.h": "c",
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||||
"r_cg_serial.h": "c"
|
||||
}
|
||||
}
|
||||
1
OUTPUT/更改履历.txt
Normal file
1
OUTPUT/更改履历.txt
Normal file
@ -0,0 +1 @@
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||||
SW0101 初版
|
||||
413
appTask.c
Normal file
413
appTask.c
Normal file
@ -0,0 +1,413 @@
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||||
#include "r_cg_macrodriver.h"
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#include "appTask.h"
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#include "event.h"
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||||
#include "r_cg_port.h"
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||||
#include "r_cg_timer.h"
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||||
//#include "r_cg_wdt.h"
|
||||
#include "hwCtrl.h"
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||||
#include "r_cg_adc.h"
|
||||
#include "r_cg_serial.h"
|
||||
|
||||
uint8_t g_rx_buf[3];
|
||||
|
||||
extern uint16_t g_AdVal[3];
|
||||
uint16_t am_counter,fan_counter,heat_counter;
|
||||
|
||||
void HardWare_Init(void)
|
||||
{
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||||
//时基初始化
|
||||
R_TAU0_Channel0_Start();
|
||||
|
||||
//LED初始化
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||||
FanLED_Ctrl(0);
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||||
HeatLED_Ctrl(0);
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//AnmoLED_Ctrl(0);
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||||
|
||||
//AD 初始化
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||||
//R_ADC_Start();
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||||
//R_ADC_Set_OperationOn();
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||||
//R_TAU0_Channel1_Start();
|
||||
|
||||
//UART初始化
|
||||
R_UART0_Start();
|
||||
R_UART0_Receive(g_rx_buf,1);
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||||
}
|
||||
uint8_t uart_sendend;
|
||||
void Variable_Init(void)
|
||||
{
|
||||
uart_sendend = 1;
|
||||
}
|
||||
static uint8_t heat_txstate=0,fan_txstate=0,motor_txstate=0,heat_state=0,fan_state=0,motor_state=0;
|
||||
uint8_t g_tx_buf[7] = {0};
|
||||
|
||||
void UART_Tx_Pro(uint8_t keyid)
|
||||
{
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||||
uint8_t uart_buf[7] = {0x5a,0xa5,0x04,0x00,0x00,0x00,0x00};
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||||
uint8_t i;
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||||
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||||
switch (keyid)
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||||
{
|
||||
case KEY_JR:
|
||||
uart_buf[3] = (0x03 + heat_txstate)<<4;
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||||
break;
|
||||
case KEY_FAN:
|
||||
uart_buf[3] = 0x03 + fan_txstate;
|
||||
break;
|
||||
case KEY_AM:
|
||||
if (motor_txstate == 0)
|
||||
{
|
||||
uart_buf[4] = 0x0d;
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||||
}
|
||||
else
|
||||
{
|
||||
uart_buf[4] = 0x09 + motor_txstate;
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||||
}
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||||
break;
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||||
default:
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||||
return;
|
||||
}
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||||
//checksum
|
||||
uart_buf[6] = uart_buf[3] + uart_buf[5] + uart_buf[4];
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||||
for ( i = 0; i < 7; i++)
|
||||
{
|
||||
g_tx_buf[i] = uart_buf[i];
|
||||
}
|
||||
if (uart_sendend == 1)
|
||||
{
|
||||
uart_sendend = 0;
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||||
R_UART0_Send(g_tx_buf,7);
|
||||
}
|
||||
}
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||||
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||||
uint8_t datacount=0;
|
||||
uint8_t RxTimeoutCount=0;
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||||
static uint8_t Rxdata[10];
|
||||
uint8_t RxFlag=0;
|
||||
void UART_Rx_Pro(uint8_t data)
|
||||
{
|
||||
static uint8_t last_data=0,datalen=0;
|
||||
if (last_data == 0x5A && data == 0xA5)
|
||||
{
|
||||
RxFlag = 1;
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||||
datacount = 0;
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||||
datalen=0;
|
||||
g_tx_buf[0] = 1;
|
||||
//R_UART0_Send(g_tx_buf,1);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (RxFlag == 1)
|
||||
{
|
||||
datalen = data;
|
||||
RxFlag = 2;
|
||||
g_tx_buf[0] = 2;
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||||
//R_UART0_Send(g_tx_buf,1);
|
||||
}
|
||||
else if (RxFlag == 2)
|
||||
{
|
||||
Rxdata[datacount++] = data;
|
||||
if (datacount >= datalen)
|
||||
{
|
||||
MsgPro(datalen);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
last_data = data;
|
||||
RxTimeoutCount = 0;
|
||||
|
||||
}
|
||||
void MsgPro(uint8_t len)
|
||||
{
|
||||
uint8_t i;
|
||||
//不用大屏协议
|
||||
uint8_t crc,crcRx;
|
||||
if (len <= 3)
|
||||
{
|
||||
return;
|
||||
}
|
||||
crc = 0;
|
||||
for(i=0;i<3;i++)
|
||||
{
|
||||
crc += Rxdata[i];
|
||||
}
|
||||
crcRx = Rxdata[3];
|
||||
|
||||
if (crc == crcRx)
|
||||
{
|
||||
switch (Rxdata[0])
|
||||
{
|
||||
case 0x10:
|
||||
heat_state = 0;
|
||||
//fan_state = 0;
|
||||
break;
|
||||
case 0x20:
|
||||
heat_state = 3;
|
||||
fan_state = 0;
|
||||
break;
|
||||
case 0x70:
|
||||
heat_state = 2;
|
||||
fan_state = 0;
|
||||
break;
|
||||
case 0x80:
|
||||
heat_state = 1;
|
||||
fan_state = 0;
|
||||
break;
|
||||
case 0x01:
|
||||
fan_state = 0;
|
||||
//heat_state = 0;
|
||||
break;
|
||||
case 0x02:
|
||||
fan_state = 3;
|
||||
heat_state = 0;
|
||||
break;
|
||||
case 0x07:
|
||||
fan_state = 2;
|
||||
heat_state = 0;
|
||||
break;
|
||||
case 0x08:
|
||||
fan_state = 1;
|
||||
heat_state = 0;
|
||||
break;
|
||||
case 0x11:
|
||||
fan_state = 0;
|
||||
heat_state = 0;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (Rxdata[1])
|
||||
{
|
||||
case 0x1a:
|
||||
motor_state = 1;
|
||||
break;
|
||||
case 0x1b:
|
||||
motor_state = 2;
|
||||
break;
|
||||
case 0x1c:
|
||||
motor_state = 3;
|
||||
break;
|
||||
case 0x1d:
|
||||
motor_state = 0;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
RxFlag = 0;
|
||||
RxTimeoutCount = 0;
|
||||
datacount = 0;
|
||||
}
|
||||
void keyLogic(uint8_t keyno)
|
||||
{
|
||||
|
||||
switch (keyno)
|
||||
{
|
||||
case KEY_JR:
|
||||
heat_txstate = heat_state + 1;
|
||||
if (heat_txstate > 3)
|
||||
{
|
||||
heat_txstate = 0;
|
||||
}
|
||||
heat_state = heat_txstate;
|
||||
fan_state = 0;
|
||||
|
||||
break;
|
||||
case KEY_FAN:
|
||||
fan_txstate = fan_state + 1;
|
||||
if (fan_txstate > 3)
|
||||
{
|
||||
fan_txstate = 0;
|
||||
}
|
||||
fan_state = fan_txstate;
|
||||
heat_state = 0;
|
||||
|
||||
break;
|
||||
case KEY_AM:
|
||||
motor_txstate = motor_state + 1;
|
||||
if (motor_txstate > 3)
|
||||
{
|
||||
motor_txstate = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
am_counter = 0;
|
||||
}
|
||||
motor_state = motor_txstate;
|
||||
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
UART_Tx_Pro(keyno);
|
||||
}
|
||||
|
||||
#define KEY_DELAY_TIME 6
|
||||
void keyScan(void)//5ms
|
||||
{
|
||||
static uint16_t keydelay[KEY_NUM]={0};
|
||||
static uint8_t keyflag[KEY_NUM]={0};
|
||||
static uint8_t keep_count[KEY_NUM]={0};
|
||||
uint8_t keyval,i;
|
||||
for (i = 0; i < KEY_NUM; i++)
|
||||
{
|
||||
keyval = GetKeyState(i);
|
||||
if (keyval == 1 && keyflag[i] == 0)
|
||||
{
|
||||
keydelay[i]++;
|
||||
if (keydelay[i] > KEY_DELAY_TIME)//30ms
|
||||
{
|
||||
keyflag[i] = 1;
|
||||
keydelay[i] = KEY_DELAY_TIME;
|
||||
keyLogic(i);
|
||||
keep_count[i] = 0;
|
||||
}
|
||||
|
||||
}
|
||||
else if (keyval == 0)
|
||||
{
|
||||
keyflag[i] = 0;
|
||||
keydelay[i] = 0;
|
||||
}
|
||||
|
||||
}
|
||||
//持续发送
|
||||
|
||||
}
|
||||
|
||||
void LED_Ctrl(void)
|
||||
{
|
||||
FanLED_Ctrl(fan_state);
|
||||
HeatLED_Ctrl(heat_state);
|
||||
AnmoLED_Ctrl(motor_state);
|
||||
}
|
||||
|
||||
void AppTask(void)
|
||||
{
|
||||
static uint8_t ledno = 1,last = 0;
|
||||
if (TimeBase5msFlag == 1)
|
||||
{
|
||||
TimeBase5msFlag = 0;
|
||||
keyScan();
|
||||
if (RxFlag)
|
||||
{
|
||||
RxTimeoutCount++;
|
||||
if (RxTimeoutCount > 6)
|
||||
{
|
||||
RxFlag = 0;
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
RxTimeoutCount = 0;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
if (TimeBase10msFlag == 1)
|
||||
{
|
||||
TimeBase10msFlag = 0;
|
||||
LED_Ctrl();
|
||||
}
|
||||
|
||||
if (TimeBase100msFlag == 1)
|
||||
{
|
||||
TimeBase100msFlag = 0;
|
||||
|
||||
R_WDT_Restart();
|
||||
|
||||
}
|
||||
|
||||
if (TimeBase1000msFlag == 1)
|
||||
{
|
||||
TimeBase1000msFlag = 0;
|
||||
//UART_Tx_Pro(1);
|
||||
if (motor_state != 0)
|
||||
{
|
||||
am_counter++;
|
||||
if (am_counter >= 900)//15min
|
||||
{
|
||||
am_counter = 0;
|
||||
motor_state = 0;
|
||||
motor_txstate = 0;
|
||||
UART_Tx_Pro(KEY_AM);
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
am_counter = 0;
|
||||
}
|
||||
|
||||
if (fan_state != 0)
|
||||
{
|
||||
fan_counter++;
|
||||
if (fan_counter >= 1500)//25min
|
||||
{
|
||||
fan_counter = 0;
|
||||
fan_state = 0;
|
||||
fan_txstate = 0;
|
||||
UART_Tx_Pro(KEY_FAN);
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
fan_counter = 0;
|
||||
}
|
||||
|
||||
if (heat_state != 0)
|
||||
{
|
||||
heat_counter++;
|
||||
if (heat_counter >= 1500)//25min
|
||||
{
|
||||
heat_counter = 0;
|
||||
heat_state = 0;
|
||||
heat_txstate = 0;
|
||||
UART_Tx_Pro(KEY_JR);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
heat_counter = 0;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#define POLYNOMINAL 0xA001
|
||||
#define PRESET_VALUE 0xFFFF
|
||||
|
||||
unsigned int crc16_make(unsigned char *Buffer, unsigned char size)
|
||||
{
|
||||
unsigned int Cur_CRC_Value;
|
||||
unsigned char i,j;
|
||||
|
||||
Cur_CRC_Value = PRESET_VALUE;
|
||||
|
||||
for(i = 0x00; i < size; i++)
|
||||
{
|
||||
Cur_CRC_Value ^= *Buffer++;
|
||||
|
||||
for(j = 0x00; j < 8; j++)
|
||||
{
|
||||
if(Cur_CRC_Value & 0x0001)
|
||||
{
|
||||
Cur_CRC_Value = (Cur_CRC_Value >> 1) ^ POLYNOMINAL;
|
||||
}
|
||||
else
|
||||
{
|
||||
Cur_CRC_Value = (Cur_CRC_Value >> 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return Cur_CRC_Value;
|
||||
|
||||
}
|
||||
18
appTask.h
Normal file
18
appTask.h
Normal file
@ -0,0 +1,18 @@
|
||||
#ifndef __APPTASK_H__
|
||||
#define __APPTASK_H__
|
||||
|
||||
#define KEY_NUM 3
|
||||
|
||||
#define KEY_JR 0
|
||||
#define KEY_FAN 1
|
||||
#define KEY_AM 2
|
||||
|
||||
|
||||
void HardWare_Init(void);
|
||||
void Variable_Init(void);
|
||||
void AppTask(void);
|
||||
void UART_Rx_Pro(uint8_t data);
|
||||
void MsgPro(uint8_t len);
|
||||
unsigned int crc16_make(unsigned char *Buffer, unsigned char size);
|
||||
|
||||
#endif
|
||||
229
cstart.asm
Normal file
229
cstart.asm
Normal file
@ -0,0 +1,229 @@
|
||||
;/**********************************************************************************************************************
|
||||
; * DISCLAIMER
|
||||
; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
|
||||
; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
; * applicable laws, including copyright laws.
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
|
||||
; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
|
||||
; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
|
||||
; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
|
||||
; * this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
; * following link:
|
||||
; * http://www.renesas.com/disclaimer
|
||||
; *
|
||||
; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
|
||||
; *********************************************************************************************************************/
|
||||
; NOTE : THIS IS A TYPICAL EXAMPLE.
|
||||
|
||||
$IFNDEF __RENESAS_VERSION__
|
||||
__RENESAS_VERSION__ .EQU 0x01000000
|
||||
$ENDIF
|
||||
|
||||
.public _start
|
||||
.public _exit
|
||||
|
||||
;-----------------------------------------------------------------------------
|
||||
; RAM section
|
||||
;-----------------------------------------------------------------------------
|
||||
.SECTION .dataR, DATA
|
||||
.SECTION .sdataR, DATA
|
||||
; .SECTION .datafR, DATAF
|
||||
; .SECTION .textfR, TEXTF
|
||||
|
||||
$IF (__RENESAS_VERSION__ < 0x01010000) ; for CC-RL V1.00
|
||||
;-----------------------------------------------------------------------------
|
||||
; stack area
|
||||
;-----------------------------------------------------------------------------
|
||||
; !!! [CAUTION] !!!
|
||||
; Set up stack size suitable for a project.
|
||||
.SECTION .stack_bss, BSS
|
||||
_stackend:
|
||||
.DS 0x200
|
||||
_stacktop:
|
||||
$ENDIF
|
||||
|
||||
;-----------------------------------------------------------------------------
|
||||
; RESET vector
|
||||
;-----------------------------------------------------------------------------
|
||||
_start .VECTOR 0
|
||||
|
||||
;-----------------------------------------------------------------------------
|
||||
; startup
|
||||
;-----------------------------------------------------------------------------
|
||||
.SECTION .text, TEXT
|
||||
_start:
|
||||
;--------------------------------------------------
|
||||
; setting register bank
|
||||
;--------------------------------------------------
|
||||
; SEL RB0
|
||||
|
||||
;--------------------------------------------------
|
||||
; setting mirror area
|
||||
;--------------------------------------------------
|
||||
; ONEB !PMC ; mirror area = 10000-1FFFFH
|
||||
|
||||
;--------------------------------------------------
|
||||
; setting the stack pointer
|
||||
;--------------------------------------------------
|
||||
$IF (__RENESAS_VERSION__ >= 0x01010000)
|
||||
MOVW SP,#LOWW(__STACK_ADDR_START)
|
||||
$ELSE ; for CC-RL V1.00
|
||||
MOVW SP,#LOWW(_stacktop)
|
||||
$ENDIF
|
||||
|
||||
;--------------------------------------------------
|
||||
; initializing stack area
|
||||
;--------------------------------------------------
|
||||
$IF (__RENESAS_VERSION__ >= 0x01010000)
|
||||
MOVW AX,#LOWW(__STACK_ADDR_END)
|
||||
$ELSE ; for CC-RL V1.00
|
||||
MOVW AX,#LOWW(_stackend)
|
||||
$ENDIF
|
||||
CALL !!_stkinit
|
||||
|
||||
;--------------------------------------------------
|
||||
; hardware initialization
|
||||
;--------------------------------------------------
|
||||
CALL !!_hdwinit
|
||||
|
||||
;--------------------------------------------------
|
||||
; initializing BSS
|
||||
;--------------------------------------------------
|
||||
; clear external variables which doesn't have initial value (near)
|
||||
MOVW HL,#LOWW(STARTOF(.bss))
|
||||
MOVW AX,#LOWW(STARTOF(.bss) + SIZEOF(.bss))
|
||||
BR $.L2_BSS
|
||||
.L1_BSS:
|
||||
MOV [HL+0],#0
|
||||
INCW HL
|
||||
.L2_BSS:
|
||||
CMPW AX,HL
|
||||
BNZ $.L1_BSS
|
||||
|
||||
; clear saddr variables which doesn't have initial value
|
||||
MOVW HL,#LOWW(STARTOF(.sbss))
|
||||
MOVW AX,#LOWW(STARTOF(.sbss) + SIZEOF(.sbss))
|
||||
BR $.L2_SBSS
|
||||
.L1_SBSS:
|
||||
MOV [HL+0],#0
|
||||
INCW HL
|
||||
.L2_SBSS:
|
||||
CMPW AX,HL
|
||||
BNZ $.L1_SBSS
|
||||
|
||||
; clear external variables which doesn't have initial value (far)
|
||||
; MOV ES,#HIGHW(STARTOF(.bssf))
|
||||
; MOVW HL,#LOWW(STARTOF(.bssf))
|
||||
; MOVW AX,#LOWW(STARTOF(.bssf) + SIZEOF(.bssf))
|
||||
; BR $.L2_BSSF
|
||||
;.L1_BSSF:
|
||||
; MOV ES:[HL+0],#0
|
||||
; INCW HL
|
||||
;.L2_BSSF:
|
||||
; CMPW AX,HL
|
||||
; BNZ $.L1_BSSF
|
||||
|
||||
;--------------------------------------------------
|
||||
; ROM data copy
|
||||
;--------------------------------------------------
|
||||
; copy external variables having initial value (near)
|
||||
MOV ES,#HIGHW(STARTOF(.data))
|
||||
MOVW BC,#LOWW(SIZEOF(.data))
|
||||
BR $.L2_DATA
|
||||
.L1_DATA:
|
||||
DECW BC
|
||||
MOV A,ES:LOWW(STARTOF(.data))[BC]
|
||||
MOV LOWW(STARTOF(.dataR))[BC],A
|
||||
.L2_DATA:
|
||||
CLRW AX
|
||||
CMPW AX,BC
|
||||
BNZ $.L1_DATA
|
||||
|
||||
; copy saddr variables having initial value
|
||||
MOV ES,#HIGHW(STARTOF(.sdata))
|
||||
MOVW BC,#LOWW(SIZEOF(.sdata))
|
||||
BR $.L2_SDATA
|
||||
.L1_SDATA:
|
||||
DECW BC
|
||||
MOV A,ES:LOWW(STARTOF(.sdata))[BC]
|
||||
MOV LOWW(STARTOF(.sdataR))[BC],A
|
||||
.L2_SDATA:
|
||||
CLRW AX
|
||||
CMPW AX,BC
|
||||
BNZ $.L1_SDATA
|
||||
|
||||
; copy external variables having initial value (far)
|
||||
; MOVW BC,#LOWW(SIZEOF(.dataf))
|
||||
; BR $.L2_DATAF
|
||||
;.L1_DATAF:
|
||||
; DECW BC
|
||||
; MOV ES,#HIGHW(STARTOF(.dataf))
|
||||
; MOV A,ES:LOWW(STARTOF(.dataf))[BC]
|
||||
; MOV ES,#HIGHW(STARTOF(.datafR))
|
||||
; MOV ES:LOWW(STARTOF(.datafR))[BC],A
|
||||
;.L2_DATAF:
|
||||
; CLRW AX
|
||||
; CMPW AX,BC
|
||||
; BNZ $.L1_DATAF
|
||||
|
||||
; copy .text to RAM
|
||||
; MOV C,#HIGHW(STARTOF(.textf))
|
||||
; MOVW HL,#LOWW(STARTOF(.textf))
|
||||
; MOVW DE,#LOWW(STARTOF(.textfR))
|
||||
; BR $.L2_TEXT
|
||||
;.L1_TEXT:
|
||||
; MOV A,C
|
||||
; MOV ES,A
|
||||
; MOV A,ES:[HL]
|
||||
; MOV [DE],A
|
||||
; INCW DE
|
||||
; INCW HL
|
||||
; CLRW AX
|
||||
; CMPW AX,HL
|
||||
; SKNZ
|
||||
; INC C
|
||||
;.L2_TEXT:
|
||||
; MOVW AX,HL
|
||||
; CMPW AX,#LOWW(STARTOF(.text) + SIZEOF(.text))
|
||||
; BNZ $.L1_TEXT
|
||||
|
||||
;--------------------------------------------------
|
||||
; call main function
|
||||
;--------------------------------------------------
|
||||
CALL !!_main ; main();
|
||||
|
||||
;--------------------------------------------------
|
||||
; call exit function
|
||||
;--------------------------------------------------
|
||||
CLRW AX ; exit(0)
|
||||
_exit:
|
||||
BR $_exit
|
||||
|
||||
;-----------------------------------------------------------------------------
|
||||
; section
|
||||
;-----------------------------------------------------------------------------
|
||||
$IF (__RENESAS_VERSION__ >= 0x01010000)
|
||||
.SECTION .RLIB, TEXTF
|
||||
.L_section_RLIB:
|
||||
.SECTION .SLIB, TEXTF
|
||||
.L_section_SLIB:
|
||||
$ENDIF
|
||||
.SECTION .textf, TEXTF
|
||||
.L_section_textf:
|
||||
.SECTION .constf, CONSTF
|
||||
.L_section_constf:
|
||||
.SECTION .data, DATA
|
||||
.L_section_data:
|
||||
;.SECTION .dataf, DATAF
|
||||
;.L_section_dataf:
|
||||
.SECTION .sdata, SDATA
|
||||
.L_section_sdata:
|
||||
.SECTION .bss, BSS
|
||||
.L_section_bss:
|
||||
;.SECTION .bssf, BSSF
|
||||
;.L_section_bssf:
|
||||
.SECTION .sbss, SBSS
|
||||
.L_section_sbss:
|
||||
46
event.c
Normal file
46
event.c
Normal file
@ -0,0 +1,46 @@
|
||||
|
||||
#include "event.h"
|
||||
|
||||
static volatile uint16_t TimeBaseCounter;
|
||||
volatile uint8_t TimeBase1msFlag;
|
||||
volatile uint8_t TimeBase5msFlag;
|
||||
volatile uint8_t TimeBase10msFlag;
|
||||
volatile uint8_t TimeBase20msFlag;
|
||||
volatile uint8_t TimeBase50msFlag;
|
||||
volatile uint8_t TimeBase100msFlag;
|
||||
volatile uint8_t TimeBase1000msFlag;
|
||||
|
||||
|
||||
void TimeBaseCount(void)
|
||||
{
|
||||
TimeBaseCounter++;
|
||||
TimeBase1msFlag = 1;
|
||||
if(TimeBaseCounter % 5 == 0)
|
||||
{
|
||||
TimeBase5msFlag = 1;
|
||||
}
|
||||
if(TimeBaseCounter % 10 == 0)
|
||||
{
|
||||
TimeBase10msFlag = 1;
|
||||
}
|
||||
if(TimeBaseCounter % 20 == 0)
|
||||
{
|
||||
TimeBase20msFlag = 1;
|
||||
}
|
||||
if(TimeBaseCounter % 50 == 0)
|
||||
{
|
||||
TimeBase50msFlag = 1;
|
||||
}
|
||||
if(TimeBaseCounter % 100 == 0)
|
||||
{
|
||||
TimeBase100msFlag = 1;
|
||||
}
|
||||
if(TimeBaseCounter % 1000 == 0)
|
||||
{
|
||||
TimeBase1000msFlag = 1;
|
||||
}
|
||||
if(TimeBaseCounter >= 60000)
|
||||
{
|
||||
TimeBaseCounter = 0;
|
||||
}
|
||||
}
|
||||
18
event.h
Normal file
18
event.h
Normal file
@ -0,0 +1,18 @@
|
||||
|
||||
|
||||
#ifndef __EVENT_H__
|
||||
#define __EVENT_H__
|
||||
#include "r_cg_macrodriver.h"
|
||||
|
||||
extern volatile uint8_t TimeBase1msFlag;
|
||||
extern volatile uint8_t TimeBase5msFlag;
|
||||
extern volatile uint8_t TimeBase10msFlag;
|
||||
extern volatile uint8_t TimeBase20msFlag;
|
||||
extern volatile uint8_t TimeBase50msFlag;
|
||||
extern volatile uint8_t TimeBase100msFlag;
|
||||
extern volatile uint8_t TimeBase1000msFlag;
|
||||
|
||||
|
||||
extern void TimeBaseCount(void);
|
||||
|
||||
#endif
|
||||
35
hdwinit.asm
Normal file
35
hdwinit.asm
Normal file
@ -0,0 +1,35 @@
|
||||
;/**********************************************************************************************************************
|
||||
; * DISCLAIMER
|
||||
; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
|
||||
; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
; * applicable laws, including copyright laws.
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
|
||||
; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
|
||||
; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
|
||||
; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
|
||||
; * this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
; * following link:
|
||||
; * http://www.renesas.com/disclaimer
|
||||
; *
|
||||
; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
|
||||
; *********************************************************************************************************************/;---------------------------------------------------------------------
|
||||
; _hdwinit
|
||||
;
|
||||
; void _hdwinit(void);
|
||||
;
|
||||
; input:
|
||||
; NONE
|
||||
; output:
|
||||
; NONE
|
||||
;---------------------------------------------------------------------
|
||||
|
||||
; NOTE : THIS IS A TYPICAL EXAMPLE.
|
||||
|
||||
.PUBLIC _hdwinit
|
||||
|
||||
.textf .CSEG TEXTF
|
||||
_hdwinit:
|
||||
RET
|
||||
241
hwCtrl.c
Normal file
241
hwCtrl.c
Normal file
@ -0,0 +1,241 @@
|
||||
|
||||
#include "hwCtrl.h"
|
||||
#include "r_cg_port.h"
|
||||
#include "iodefine.h"
|
||||
#include "appTask.h"
|
||||
|
||||
#define K74L 1
|
||||
#define K74R 2
|
||||
#define BOARD K74L
|
||||
|
||||
|
||||
|
||||
#if BOARD == K74R
|
||||
//RIGHT
|
||||
#define LEDH1 P4_bit.no2
|
||||
#define LEDH2 P1_bit.no0
|
||||
#define LEDH3 P1_bit.no1
|
||||
|
||||
#define LEDM1 P1_bit.no2
|
||||
#define LEDM2 P1_bit.no3
|
||||
#define LEDM3 P1_bit.no4
|
||||
|
||||
#define LEDF1 P4_bit.no1
|
||||
#define LEDF2 P2_bit.no3
|
||||
#define LEDF3 P2_bit.no2
|
||||
|
||||
#else
|
||||
//LEFT
|
||||
#define LEDH1 P4_bit.no2
|
||||
#define LEDH2 P1_bit.no0
|
||||
#define LEDH3 P1_bit.no1
|
||||
|
||||
#define LEDF1 P1_bit.no2
|
||||
#define LEDF2 P1_bit.no3
|
||||
#define LEDF3 P1_bit.no4
|
||||
|
||||
#define LEDM1 P4_bit.no1
|
||||
#define LEDM2 P2_bit.no3
|
||||
#define LEDM3 P2_bit.no2
|
||||
|
||||
#endif
|
||||
|
||||
#define IO_KEY1 P2_bit.no0
|
||||
#define IO_KEY2 P2_bit.no1
|
||||
#define IO_KEY5 P12_bit.no2
|
||||
#define IO_KEY6 P13_bit.no7
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern uint16_t g_AdVal[3];
|
||||
|
||||
#if BOARD == K74R
|
||||
void FanLED_Ctrl(uint8_t state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case 0:
|
||||
LEDF1 = LED_OFF;
|
||||
LEDF2 = LED_ON;
|
||||
LEDF3 = LED_ON;
|
||||
break;
|
||||
case 3:
|
||||
LEDF1 = LED_ON;
|
||||
LEDF2 = LED_ON;
|
||||
LEDF3 = LED_ON;
|
||||
break;
|
||||
case 2:
|
||||
LEDF1 = LED_ON;
|
||||
LEDF2 = LED_OFF;
|
||||
LEDF3 = LED_ON;
|
||||
break;
|
||||
case 1:
|
||||
LEDF1 = LED_ON;
|
||||
LEDF2 = LED_OFF;
|
||||
LEDF3 = LED_OFF;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
void AnmoLED_Ctrl(uint8_t state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case 0:
|
||||
LEDM1 = LED_OFF;
|
||||
LEDM2 = LED_OFF;
|
||||
LEDM3 = LED_OFF;
|
||||
break;
|
||||
case 3:
|
||||
LEDM1 = LED_ON;
|
||||
LEDM2 = LED_OFF;
|
||||
LEDM3 = LED_OFF;
|
||||
break;
|
||||
case 2:
|
||||
LEDM1 = LED_ON;
|
||||
LEDM2 = LED_ON;
|
||||
LEDM3 = LED_OFF;
|
||||
break;
|
||||
case 1:
|
||||
LEDM1 = LED_ON;
|
||||
LEDM2 = LED_ON;
|
||||
LEDM3 = LED_ON;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
#else
|
||||
void AnmoLED_Ctrl(uint8_t state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case 0:
|
||||
LEDM1 = LED_OFF;
|
||||
LEDM2 = LED_ON;
|
||||
LEDM3 = LED_ON;
|
||||
break;
|
||||
case 3:
|
||||
LEDM1 = LED_ON;
|
||||
LEDM2 = LED_ON;
|
||||
LEDM3 = LED_ON;
|
||||
break;
|
||||
case 2:
|
||||
LEDM1 = LED_ON;
|
||||
LEDM2 = LED_OFF;
|
||||
LEDM3 = LED_ON;
|
||||
break;
|
||||
case 1:
|
||||
LEDM1 = LED_ON;
|
||||
LEDM2 = LED_OFF;
|
||||
LEDM3 = LED_OFF;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
void FanLED_Ctrl(uint8_t state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case 0:
|
||||
LEDF1 = LED_OFF;
|
||||
LEDF2 = LED_OFF;
|
||||
LEDF3 = LED_OFF;
|
||||
break;
|
||||
case 3:
|
||||
LEDF1 = LED_ON;
|
||||
LEDF2 = LED_OFF;
|
||||
LEDF3 = LED_OFF;
|
||||
break;
|
||||
case 2:
|
||||
LEDF1 = LED_ON;
|
||||
LEDF2 = LED_ON;
|
||||
LEDF3 = LED_OFF;
|
||||
break;
|
||||
case 1:
|
||||
LEDF1 = LED_ON;
|
||||
LEDF2 = LED_ON;
|
||||
LEDF3 = LED_ON;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void HeatLED_Ctrl(uint8_t state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case 0:
|
||||
LEDH1 = LED_OFF;
|
||||
LEDH2 = LED_OFF;
|
||||
LEDH3 = LED_OFF;
|
||||
break;
|
||||
case 3:
|
||||
LEDH1 = LED_ON;
|
||||
LEDH2 = LED_OFF;
|
||||
LEDH3 = LED_OFF;
|
||||
break;
|
||||
case 2:
|
||||
LEDH1 = LED_ON;
|
||||
LEDH2 = LED_ON;
|
||||
LEDH3 = LED_OFF;
|
||||
break;
|
||||
case 1:
|
||||
LEDH1 = LED_ON;
|
||||
LEDH2 = LED_ON;
|
||||
LEDH3 = LED_ON;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
#define KEY_AD_V1 690
|
||||
#define KEY_AD_V2 510
|
||||
#define KEY_AD_TH 50
|
||||
#define KEY5_AD_V1 KEY_AD_TH //0
|
||||
#define KEY5_AD_V2 254
|
||||
#define KEY5_AD_V3 455
|
||||
#define KEY5_AD_V4 658
|
||||
#define KEY5_AD_V5 902
|
||||
uint8_t GetKeyState(uint8_t keyno)
|
||||
{
|
||||
switch (keyno)
|
||||
{
|
||||
#if BOARD == K74R
|
||||
//RIGHT
|
||||
case KEY_FAN:
|
||||
return IO_KEY1==0?1:0;
|
||||
break;
|
||||
case KEY_JR:
|
||||
return IO_KEY2==0?1:0;
|
||||
break;
|
||||
case KEY_AM:
|
||||
return (IO_KEY5==0)?1:0;
|
||||
break;
|
||||
#else
|
||||
//left
|
||||
case KEY_AM:
|
||||
return IO_KEY1==0?1:0;
|
||||
break;
|
||||
case KEY_JR:
|
||||
return IO_KEY2==0?1:0;
|
||||
break;
|
||||
case KEY_FAN:
|
||||
return (IO_KEY5==0)?1:0;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
16
hwCtrl.h
Normal file
16
hwCtrl.h
Normal file
@ -0,0 +1,16 @@
|
||||
|
||||
#ifndef __HWCTRL_H__
|
||||
#define __HWCTRL_H__
|
||||
#include "r_cg_macrodriver.h"
|
||||
|
||||
#define LED_ON 0
|
||||
#define LED_OFF 1
|
||||
|
||||
|
||||
uint8_t GetKeyState(uint8_t keyno);
|
||||
|
||||
void FanLED_Ctrl(uint8_t state);
|
||||
void HeatLED_Ctrl(uint8_t state);
|
||||
void AnmoLED_Ctrl(uint8_t state);
|
||||
|
||||
#endif
|
||||
542
iodefine.h
Normal file
542
iodefine.h
Normal file
@ -0,0 +1,542 @@
|
||||
/******************************************************************************/
|
||||
/* DISCLAIMER */
|
||||
/* This software is supplied by Renesas Electronics Corporation and is only */
|
||||
/* intended for use with Renesas products. No other uses are authorized.This */
|
||||
/* software is owned by Renesas Electronics Corporation and is protected */
|
||||
/* under all applicable laws, including copyright laws. */
|
||||
/* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES */
|
||||
/* REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING */
|
||||
/* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR */
|
||||
/* PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY */
|
||||
/* DISCLAIMED. */
|
||||
/* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS */
|
||||
/* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE */
|
||||
/* LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL */
|
||||
/* DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS */
|
||||
/* AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. */
|
||||
/* Renesas reserves the right, without notice, to make changes to this */
|
||||
/* software and to discontinue the availability of this software. */
|
||||
/* By using this software, you agree to the additional terms and conditions */
|
||||
/* found by accessing the following link: */
|
||||
/* http://www.renesas.com/disclaimer */
|
||||
/* */
|
||||
/* Device : RL78/R5F10268 */
|
||||
/* File Name : iodefine.h */
|
||||
/* Abstract : Definition of Special Function Register (SFR) */
|
||||
/* History : V1.12 [Device File version] */
|
||||
/* Options : -df=E:\Program Files (x86)\renesas\CS+\CC\Device\RL78\Devicef */
|
||||
/* ile\DR5F10268.DVF -o=C:\Users\dm01\Documents\K67L\iodefine.h */
|
||||
/* -f */
|
||||
/* Date : 2022/5/20 */
|
||||
/* Version : V1.15.00.01 [df2iodef.exe version] */
|
||||
/* This is a typical example. */
|
||||
/* */
|
||||
/******************************************************************************/
|
||||
#ifndef __R5F10268IODEFINE_HEADER__
|
||||
#define __R5F10268IODEFINE_HEADER__
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned char no0:1;
|
||||
unsigned char no1:1;
|
||||
unsigned char no2:1;
|
||||
unsigned char no3:1;
|
||||
unsigned char no4:1;
|
||||
unsigned char no5:1;
|
||||
unsigned char no6:1;
|
||||
unsigned char no7:1;
|
||||
} __bitf_T;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned char no0:1;
|
||||
unsigned char no1:1;
|
||||
unsigned char no2:1;
|
||||
unsigned char no3:1;
|
||||
unsigned char no4:1;
|
||||
unsigned char no5:1;
|
||||
unsigned char no6:1;
|
||||
unsigned char no7:1;
|
||||
unsigned char no8:1;
|
||||
unsigned char no9:1;
|
||||
unsigned char no10:1;
|
||||
unsigned char no11:1;
|
||||
unsigned char no12:1;
|
||||
unsigned char no13:1;
|
||||
unsigned char no14:1;
|
||||
unsigned char no15:1;
|
||||
} __bitf_T2;
|
||||
|
||||
|
||||
|
||||
#define ADM2 (*(volatile __near unsigned char *)0x10)
|
||||
#define ADM2_bit (*(volatile __near __bitf_T *)0x10)
|
||||
#define ADTYP (((volatile __near __bitf_T *)0x10)->no0)
|
||||
#define AWC (((volatile __near __bitf_T *)0x10)->no2)
|
||||
#define ADRCK (((volatile __near __bitf_T *)0x10)->no3)
|
||||
#define ADUL (*(volatile __near unsigned char *)0x11)
|
||||
#define ADLL (*(volatile __near unsigned char *)0x12)
|
||||
#define ADTES (*(volatile __near unsigned char *)0x13)
|
||||
#define PU1 (*(volatile __near unsigned char *)0x31)
|
||||
#define PU1_bit (*(volatile __near __bitf_T *)0x31)
|
||||
#define PU4 (*(volatile __near unsigned char *)0x34)
|
||||
#define PU4_bit (*(volatile __near __bitf_T *)0x34)
|
||||
#define PU12 (*(volatile __near unsigned char *)0x3C)
|
||||
#define PU12_bit (*(volatile __near __bitf_T *)0x3C)
|
||||
#define PIM1 (*(volatile __near unsigned char *)0x41)
|
||||
#define PIM1_bit (*(volatile __near __bitf_T *)0x41)
|
||||
#define POM1 (*(volatile __near unsigned char *)0x51)
|
||||
#define POM1_bit (*(volatile __near __bitf_T *)0x51)
|
||||
#define POM4 (*(volatile __near unsigned char *)0x54)
|
||||
#define POM4_bit (*(volatile __near __bitf_T *)0x54)
|
||||
#define PMC1 (*(volatile __near unsigned char *)0x61)
|
||||
#define PMC1_bit (*(volatile __near __bitf_T *)0x61)
|
||||
#define PMC4 (*(volatile __near unsigned char *)0x64)
|
||||
#define PMC4_bit (*(volatile __near __bitf_T *)0x64)
|
||||
#define NFEN0 (*(volatile __near unsigned char *)0x70)
|
||||
#define NFEN0_bit (*(volatile __near __bitf_T *)0x70)
|
||||
#define NFEN1 (*(volatile __near unsigned char *)0x71)
|
||||
#define NFEN1_bit (*(volatile __near __bitf_T *)0x71)
|
||||
#define ISC (*(volatile __near unsigned char *)0x73)
|
||||
#define ISC_bit (*(volatile __near __bitf_T *)0x73)
|
||||
#define TIS0 (*(volatile __near unsigned char *)0x74)
|
||||
#define ADPC (*(volatile __near unsigned char *)0x76)
|
||||
#define PIOR (*(volatile __near unsigned char *)0x77)
|
||||
#define IAWCTL (*(volatile __near unsigned char *)0x78)
|
||||
#define DFLCTL (*(volatile __near unsigned char *)0x90)
|
||||
#define DFLCTL_bit (*(volatile __near __bitf_T *)0x90)
|
||||
#define DFLEN (((volatile __near __bitf_T *)0x90)->no0)
|
||||
#define HIOTRM (*(volatile __near unsigned char *)0xA0)
|
||||
#define HOCODIV (*(volatile __near unsigned char *)0xA8)
|
||||
#define TEMPCAL0 (*(volatile __near unsigned char *)0xAC)
|
||||
#define TEMPCAL1 (*(volatile __near unsigned char *)0xAD)
|
||||
#define TEMPCAL2 (*(volatile __near unsigned char *)0xAE)
|
||||
#define TEMPCAL3 (*(volatile __near unsigned char *)0xAF)
|
||||
#define MDCL (*(volatile __near unsigned short *)0xE0)
|
||||
#define MDCH (*(volatile __near unsigned short *)0xE2)
|
||||
#define MDUC (*(volatile __near unsigned char *)0xE8)
|
||||
#define MDUC_bit (*(volatile __near __bitf_T *)0xE8)
|
||||
#define DIVST (((volatile __near __bitf_T *)0xE8)->no0)
|
||||
#define MACSF (((volatile __near __bitf_T *)0xE8)->no1)
|
||||
#define MACOF (((volatile __near __bitf_T *)0xE8)->no2)
|
||||
#define MDSM (((volatile __near __bitf_T *)0xE8)->no3)
|
||||
#define MACMODE (((volatile __near __bitf_T *)0xE8)->no6)
|
||||
#define DIVMODE (((volatile __near __bitf_T *)0xE8)->no7)
|
||||
#define PER0 (*(volatile __near unsigned char *)0xF0)
|
||||
#define PER0_bit (*(volatile __near __bitf_T *)0xF0)
|
||||
#define TAU0EN (((volatile __near __bitf_T *)0xF0)->no0)
|
||||
#define SAU0EN (((volatile __near __bitf_T *)0xF0)->no2)
|
||||
#define IICA0EN (((volatile __near __bitf_T *)0xF0)->no4)
|
||||
#define ADCEN (((volatile __near __bitf_T *)0xF0)->no5)
|
||||
#define TMKAEN (((volatile __near __bitf_T *)0xF0)->no7)
|
||||
#define OSMC (*(volatile __near unsigned char *)0xF3)
|
||||
#define RMC (*(volatile __near unsigned char *)0xF4)
|
||||
#define RMC_bit (*(volatile __near __bitf_T *)0xF4)
|
||||
#define WDVOL (((volatile __near __bitf_T *)0xF4)->no7)
|
||||
#define RPECTL (*(volatile __near unsigned char *)0xF5)
|
||||
#define RPECTL_bit (*(volatile __near __bitf_T *)0xF5)
|
||||
#define RPEF (((volatile __near __bitf_T *)0xF5)->no0)
|
||||
#define RPERDIS (((volatile __near __bitf_T *)0xF5)->no7)
|
||||
#define BCDADJ (*(volatile __near unsigned char *)0xFE)
|
||||
#define SSR00 (*(volatile __near unsigned short *)0x100)
|
||||
#define SSR00L (*(volatile __near unsigned char *)0x100)
|
||||
#define SSR01 (*(volatile __near unsigned short *)0x102)
|
||||
#define SSR01L (*(volatile __near unsigned char *)0x102)
|
||||
#define SIR00 (*(volatile __near unsigned short *)0x108)
|
||||
#define SIR00L (*(volatile __near unsigned char *)0x108)
|
||||
#define SIR01 (*(volatile __near unsigned short *)0x10A)
|
||||
#define SIR01L (*(volatile __near unsigned char *)0x10A)
|
||||
#define SMR00 (*(volatile __near unsigned short *)0x110)
|
||||
#define SMR01 (*(volatile __near unsigned short *)0x112)
|
||||
#define SCR00 (*(volatile __near unsigned short *)0x118)
|
||||
#define SCR01 (*(volatile __near unsigned short *)0x11A)
|
||||
#define SE0 (*(volatile __near unsigned short *)0x120)
|
||||
#define SE0L (*(volatile __near unsigned char *)0x120)
|
||||
#define SE0L_bit (*(volatile __near __bitf_T *)0x120)
|
||||
#define SS0 (*(volatile __near unsigned short *)0x122)
|
||||
#define SS0L (*(volatile __near unsigned char *)0x122)
|
||||
#define SS0L_bit (*(volatile __near __bitf_T *)0x122)
|
||||
#define ST0 (*(volatile __near unsigned short *)0x124)
|
||||
#define ST0L (*(volatile __near unsigned char *)0x124)
|
||||
#define ST0L_bit (*(volatile __near __bitf_T *)0x124)
|
||||
#define SPS0 (*(volatile __near unsigned short *)0x126)
|
||||
#define SPS0L (*(volatile __near unsigned char *)0x126)
|
||||
#define SO0 (*(volatile __near unsigned short *)0x128)
|
||||
#define SOE0 (*(volatile __near unsigned short *)0x12A)
|
||||
#define SOE0L (*(volatile __near unsigned char *)0x12A)
|
||||
#define SOE0L_bit (*(volatile __near __bitf_T *)0x12A)
|
||||
#define SOL0 (*(volatile __near unsigned short *)0x134)
|
||||
#define SOL0L (*(volatile __near unsigned char *)0x134)
|
||||
#define SSC0 (*(volatile __near unsigned short *)0x138)
|
||||
#define SSC0L (*(volatile __near unsigned char *)0x138)
|
||||
#define TCR00 (*(volatile __near unsigned short *)0x180)
|
||||
#define TCR01 (*(volatile __near unsigned short *)0x182)
|
||||
#define TCR02 (*(volatile __near unsigned short *)0x184)
|
||||
#define TCR03 (*(volatile __near unsigned short *)0x186)
|
||||
#define TMR00 (*(volatile __near unsigned short *)0x190)
|
||||
#define TMR01 (*(volatile __near unsigned short *)0x192)
|
||||
#define TMR02 (*(volatile __near unsigned short *)0x194)
|
||||
#define TMR03 (*(volatile __near unsigned short *)0x196)
|
||||
#define TSR00 (*(volatile __near unsigned short *)0x1A0)
|
||||
#define TSR00L (*(volatile __near unsigned char *)0x1A0)
|
||||
#define TSR01 (*(volatile __near unsigned short *)0x1A2)
|
||||
#define TSR01L (*(volatile __near unsigned char *)0x1A2)
|
||||
#define TSR02 (*(volatile __near unsigned short *)0x1A4)
|
||||
#define TSR02L (*(volatile __near unsigned char *)0x1A4)
|
||||
#define TSR03 (*(volatile __near unsigned short *)0x1A6)
|
||||
#define TSR03L (*(volatile __near unsigned char *)0x1A6)
|
||||
#define TE0 (*(volatile __near unsigned short *)0x1B0)
|
||||
#define TE0L (*(volatile __near unsigned char *)0x1B0)
|
||||
#define TE0L_bit (*(volatile __near __bitf_T *)0x1B0)
|
||||
#define TS0 (*(volatile __near unsigned short *)0x1B2)
|
||||
#define TS0L (*(volatile __near unsigned char *)0x1B2)
|
||||
#define TS0L_bit (*(volatile __near __bitf_T *)0x1B2)
|
||||
#define TT0 (*(volatile __near unsigned short *)0x1B4)
|
||||
#define TT0L (*(volatile __near unsigned char *)0x1B4)
|
||||
#define TT0L_bit (*(volatile __near __bitf_T *)0x1B4)
|
||||
#define TPS0 (*(volatile __near unsigned short *)0x1B6)
|
||||
#define TO0 (*(volatile __near unsigned short *)0x1B8)
|
||||
#define TO0L (*(volatile __near unsigned char *)0x1B8)
|
||||
#define TOE0 (*(volatile __near unsigned short *)0x1BA)
|
||||
#define TOE0L (*(volatile __near unsigned char *)0x1BA)
|
||||
#define TOE0L_bit (*(volatile __near __bitf_T *)0x1BA)
|
||||
#define TOL0 (*(volatile __near unsigned short *)0x1BC)
|
||||
#define TOL0L (*(volatile __near unsigned char *)0x1BC)
|
||||
#define TOM0 (*(volatile __near unsigned short *)0x1BE)
|
||||
#define TOM0L (*(volatile __near unsigned char *)0x1BE)
|
||||
#define IICCTL00 (*(volatile __near unsigned char *)0x230)
|
||||
#define IICCTL00_bit (*(volatile __near __bitf_T *)0x230)
|
||||
#define SPT0 (((volatile __near __bitf_T *)0x230)->no0)
|
||||
#define STT0 (((volatile __near __bitf_T *)0x230)->no1)
|
||||
#define ACKE0 (((volatile __near __bitf_T *)0x230)->no2)
|
||||
#define WTIM0 (((volatile __near __bitf_T *)0x230)->no3)
|
||||
#define SPIE0 (((volatile __near __bitf_T *)0x230)->no4)
|
||||
#define WREL0 (((volatile __near __bitf_T *)0x230)->no5)
|
||||
#define LREL0 (((volatile __near __bitf_T *)0x230)->no6)
|
||||
#define IICE0 (((volatile __near __bitf_T *)0x230)->no7)
|
||||
#define IICCTL01 (*(volatile __near unsigned char *)0x231)
|
||||
#define IICCTL01_bit (*(volatile __near __bitf_T *)0x231)
|
||||
#define PRS0 (((volatile __near __bitf_T *)0x231)->no0)
|
||||
#define DFC0 (((volatile __near __bitf_T *)0x231)->no2)
|
||||
#define SMC0 (((volatile __near __bitf_T *)0x231)->no3)
|
||||
#define DAD0 (((volatile __near __bitf_T *)0x231)->no4)
|
||||
#define CLD0 (((volatile __near __bitf_T *)0x231)->no5)
|
||||
#define WUP0 (((volatile __near __bitf_T *)0x231)->no7)
|
||||
#define IICWL0 (*(volatile __near unsigned char *)0x232)
|
||||
#define IICWH0 (*(volatile __near unsigned char *)0x233)
|
||||
#define SVA0 (*(volatile __near unsigned char *)0x234)
|
||||
#define CRCD (*(volatile __near unsigned short *)0x2FA)
|
||||
#define P1 (*(volatile __near unsigned char *)0xFF01)
|
||||
#define P1_bit (*(volatile __near __bitf_T *)0xFF01)
|
||||
#define P2 (*(volatile __near unsigned char *)0xFF02)
|
||||
#define P2_bit (*(volatile __near __bitf_T *)0xFF02)
|
||||
#define P4 (*(volatile __near unsigned char *)0xFF04)
|
||||
#define P4_bit (*(volatile __near __bitf_T *)0xFF04)
|
||||
#define P6 (*(volatile __near unsigned char *)0xFF06)
|
||||
#define P6_bit (*(volatile __near __bitf_T *)0xFF06)
|
||||
#define P12 (*(volatile __near unsigned char *)0xFF0C)
|
||||
#define P12_bit (*(volatile __near __bitf_T *)0xFF0C)
|
||||
#define P13 (*(volatile __near unsigned char *)0xFF0D)
|
||||
#define P13_bit (*(volatile __near __bitf_T *)0xFF0D)
|
||||
#define SDR00 (*(volatile __near unsigned short *)0xFF10)
|
||||
#define SIO00 (*(volatile __near unsigned char *)0xFF10)
|
||||
#define TXD0 (*(volatile __near unsigned char *)0xFF10)
|
||||
#define SDR01 (*(volatile __near unsigned short *)0xFF12)
|
||||
#define RXD0 (*(volatile __near unsigned char *)0xFF12)
|
||||
#define SIO01 (*(volatile __near unsigned char *)0xFF12)
|
||||
#define TDR00 (*(volatile __near unsigned short *)0xFF18)
|
||||
#define TDR01 (*(volatile __near unsigned short *)0xFF1A)
|
||||
#define TDR01L (*(volatile __near unsigned char *)0xFF1A)
|
||||
#define TDR01H (*(volatile __near unsigned char *)0xFF1B)
|
||||
#define ADCR (*(volatile __near unsigned short *)0xFF1E)
|
||||
#define ADCRH (*(volatile __near unsigned char *)0xFF1F)
|
||||
#define PM1 (*(volatile __near unsigned char *)0xFF21)
|
||||
#define PM1_bit (*(volatile __near __bitf_T *)0xFF21)
|
||||
#define PM2 (*(volatile __near unsigned char *)0xFF22)
|
||||
#define PM2_bit (*(volatile __near __bitf_T *)0xFF22)
|
||||
#define PM4 (*(volatile __near unsigned char *)0xFF24)
|
||||
#define PM4_bit (*(volatile __near __bitf_T *)0xFF24)
|
||||
#define PM6 (*(volatile __near unsigned char *)0xFF26)
|
||||
#define PM6_bit (*(volatile __near __bitf_T *)0xFF26)
|
||||
#define ADM0 (*(volatile __near unsigned char *)0xFF30)
|
||||
#define ADM0_bit (*(volatile __near __bitf_T *)0xFF30)
|
||||
#define ADCE (((volatile __near __bitf_T *)0xFF30)->no0)
|
||||
#define ADCS (((volatile __near __bitf_T *)0xFF30)->no7)
|
||||
#define ADS (*(volatile __near unsigned char *)0xFF31)
|
||||
#define ADS_bit (*(volatile __near __bitf_T *)0xFF31)
|
||||
#define ADM1 (*(volatile __near unsigned char *)0xFF32)
|
||||
#define ADM1_bit (*(volatile __near __bitf_T *)0xFF32)
|
||||
#define KRCTL (*(volatile __near unsigned char *)0xFF34)
|
||||
#define KRCTL_bit (*(volatile __near __bitf_T *)0xFF34)
|
||||
#define KRF (*(volatile __near unsigned char *)0xFF35)
|
||||
#define KRM0 (*(volatile __near unsigned char *)0xFF37)
|
||||
#define KRM0_bit (*(volatile __near __bitf_T *)0xFF37)
|
||||
#define EGP0 (*(volatile __near unsigned char *)0xFF38)
|
||||
#define EGP0_bit (*(volatile __near __bitf_T *)0xFF38)
|
||||
#define EGN0 (*(volatile __near unsigned char *)0xFF39)
|
||||
#define EGN0_bit (*(volatile __near __bitf_T *)0xFF39)
|
||||
#define IICA0 (*(volatile __near unsigned char *)0xFF50)
|
||||
#define IICS0 (*(volatile __near unsigned char *)0xFF51)
|
||||
#define IICS0_bit (*(volatile __near __bitf_T *)0xFF51)
|
||||
#define SPD0 (((volatile __near __bitf_T *)0xFF51)->no0)
|
||||
#define STD0 (((volatile __near __bitf_T *)0xFF51)->no1)
|
||||
#define ACKD0 (((volatile __near __bitf_T *)0xFF51)->no2)
|
||||
#define TRC0 (((volatile __near __bitf_T *)0xFF51)->no3)
|
||||
#define COI0 (((volatile __near __bitf_T *)0xFF51)->no4)
|
||||
#define EXC0 (((volatile __near __bitf_T *)0xFF51)->no5)
|
||||
#define ALD0 (((volatile __near __bitf_T *)0xFF51)->no6)
|
||||
#define MSTS0 (((volatile __near __bitf_T *)0xFF51)->no7)
|
||||
#define IICF0 (*(volatile __near unsigned char *)0xFF52)
|
||||
#define IICF0_bit (*(volatile __near __bitf_T *)0xFF52)
|
||||
#define IICRSV0 (((volatile __near __bitf_T *)0xFF52)->no0)
|
||||
#define STCEN0 (((volatile __near __bitf_T *)0xFF52)->no1)
|
||||
#define IICBSY0 (((volatile __near __bitf_T *)0xFF52)->no6)
|
||||
#define STCF0 (((volatile __near __bitf_T *)0xFF52)->no7)
|
||||
#define TDR02 (*(volatile __near unsigned short *)0xFF64)
|
||||
#define TDR03 (*(volatile __near unsigned short *)0xFF66)
|
||||
#define TDR03L (*(volatile __near unsigned char *)0xFF66)
|
||||
#define TDR03H (*(volatile __near unsigned char *)0xFF67)
|
||||
#define ITMC (*(volatile __near unsigned short *)0xFF90)
|
||||
#define CMC (*(volatile __near unsigned char *)0xFFA0)
|
||||
#define CSC (*(volatile __near unsigned char *)0xFFA1)
|
||||
#define CSC_bit (*(volatile __near __bitf_T *)0xFFA1)
|
||||
#define HIOSTOP (((volatile __near __bitf_T *)0xFFA1)->no0)
|
||||
#define MSTOP (((volatile __near __bitf_T *)0xFFA1)->no7)
|
||||
#define OSTC (*(volatile __near unsigned char *)0xFFA2)
|
||||
#define OSTC_bit (*(volatile __near __bitf_T *)0xFFA2)
|
||||
#define OSTS (*(volatile __near unsigned char *)0xFFA3)
|
||||
#define CKC (*(volatile __near unsigned char *)0xFFA4)
|
||||
#define CKC_bit (*(volatile __near __bitf_T *)0xFFA4)
|
||||
#define MCM0 (((volatile __near __bitf_T *)0xFFA4)->no4)
|
||||
#define MCS (((volatile __near __bitf_T *)0xFFA4)->no5)
|
||||
#define CKS0 (*(volatile __near unsigned char *)0xFFA5)
|
||||
#define CKS0_bit (*(volatile __near __bitf_T *)0xFFA5)
|
||||
#define PCLOE0 (((volatile __near __bitf_T *)0xFFA5)->no7)
|
||||
#define RESF (*(volatile __near unsigned char *)0xFFA8)
|
||||
#define LVIM (*(volatile __near unsigned char *)0xFFA9)
|
||||
#define LVIM_bit (*(volatile __near __bitf_T *)0xFFA9)
|
||||
#define LVIF (((volatile __near __bitf_T *)0xFFA9)->no0)
|
||||
#define LVIOMSK (((volatile __near __bitf_T *)0xFFA9)->no1)
|
||||
#define LVISEN (((volatile __near __bitf_T *)0xFFA9)->no7)
|
||||
#define LVIS (*(volatile __near unsigned char *)0xFFAA)
|
||||
#define LVIS_bit (*(volatile __near __bitf_T *)0xFFAA)
|
||||
#define LVILV (((volatile __near __bitf_T *)0xFFAA)->no0)
|
||||
#define LVIMD (((volatile __near __bitf_T *)0xFFAA)->no7)
|
||||
#define WDTE (*(volatile __near unsigned char *)0xFFAB)
|
||||
#define CRCIN (*(volatile __near unsigned char *)0xFFAC)
|
||||
#define DSA0 (*(volatile __near unsigned char *)0xFFB0)
|
||||
#define DSA1 (*(volatile __near unsigned char *)0xFFB1)
|
||||
#define DRA0 (*(volatile __near unsigned short *)0xFFB2)
|
||||
#define DRA0L (*(volatile __near unsigned char *)0xFFB2)
|
||||
#define DRA0H (*(volatile __near unsigned char *)0xFFB3)
|
||||
#define DRA1 (*(volatile __near unsigned short *)0xFFB4)
|
||||
#define DRA1L (*(volatile __near unsigned char *)0xFFB4)
|
||||
#define DRA1H (*(volatile __near unsigned char *)0xFFB5)
|
||||
#define DBC0 (*(volatile __near unsigned short *)0xFFB6)
|
||||
#define DBC0L (*(volatile __near unsigned char *)0xFFB6)
|
||||
#define DBC0H (*(volatile __near unsigned char *)0xFFB7)
|
||||
#define DBC1 (*(volatile __near unsigned short *)0xFFB8)
|
||||
#define DBC1L (*(volatile __near unsigned char *)0xFFB8)
|
||||
#define DBC1H (*(volatile __near unsigned char *)0xFFB9)
|
||||
#define DMC0 (*(volatile __near unsigned char *)0xFFBA)
|
||||
#define DMC0_bit (*(volatile __near __bitf_T *)0xFFBA)
|
||||
#define DWAIT0 (((volatile __near __bitf_T *)0xFFBA)->no4)
|
||||
#define DS0 (((volatile __near __bitf_T *)0xFFBA)->no5)
|
||||
#define DRS0 (((volatile __near __bitf_T *)0xFFBA)->no6)
|
||||
#define STG0 (((volatile __near __bitf_T *)0xFFBA)->no7)
|
||||
#define DMC1 (*(volatile __near unsigned char *)0xFFBB)
|
||||
#define DMC1_bit (*(volatile __near __bitf_T *)0xFFBB)
|
||||
#define DWAIT1 (((volatile __near __bitf_T *)0xFFBB)->no4)
|
||||
#define DS1 (((volatile __near __bitf_T *)0xFFBB)->no5)
|
||||
#define DRS1 (((volatile __near __bitf_T *)0xFFBB)->no6)
|
||||
#define STG1 (((volatile __near __bitf_T *)0xFFBB)->no7)
|
||||
#define DRC0 (*(volatile __near unsigned char *)0xFFBC)
|
||||
#define DRC0_bit (*(volatile __near __bitf_T *)0xFFBC)
|
||||
#define DST0 (((volatile __near __bitf_T *)0xFFBC)->no0)
|
||||
#define DEN0 (((volatile __near __bitf_T *)0xFFBC)->no7)
|
||||
#define DRC1 (*(volatile __near unsigned char *)0xFFBD)
|
||||
#define DRC1_bit (*(volatile __near __bitf_T *)0xFFBD)
|
||||
#define DST1 (((volatile __near __bitf_T *)0xFFBD)->no0)
|
||||
#define DEN1 (((volatile __near __bitf_T *)0xFFBD)->no7)
|
||||
#define IF0 (*(volatile __near unsigned short *)0xFFE0)
|
||||
#define IF0L (*(volatile __near unsigned char *)0xFFE0)
|
||||
#define IF0L_bit (*(volatile __near __bitf_T *)0xFFE0)
|
||||
#define IF0H (*(volatile __near unsigned char *)0xFFE1)
|
||||
#define IF0H_bit (*(volatile __near __bitf_T *)0xFFE1)
|
||||
#define WDTIIF (((volatile __near __bitf_T *)0xFFE0)->no0)
|
||||
#define LVIIF (((volatile __near __bitf_T *)0xFFE0)->no1)
|
||||
#define PIF0 (((volatile __near __bitf_T *)0xFFE0)->no2)
|
||||
#define PIF1 (((volatile __near __bitf_T *)0xFFE0)->no3)
|
||||
#define PIF2 (((volatile __near __bitf_T *)0xFFE0)->no4)
|
||||
#define PIF3 (((volatile __near __bitf_T *)0xFFE0)->no5)
|
||||
#define DMAIF0 (((volatile __near __bitf_T *)0xFFE0)->no6)
|
||||
#define DMAIF1 (((volatile __near __bitf_T *)0xFFE0)->no7)
|
||||
#define CSIIF00 (((volatile __near __bitf_T *)0xFFE1)->no0)
|
||||
#define IICIF00 (((volatile __near __bitf_T *)0xFFE1)->no0)
|
||||
#define STIF0 (((volatile __near __bitf_T *)0xFFE1)->no0)
|
||||
#define CSIIF01 (((volatile __near __bitf_T *)0xFFE1)->no1)
|
||||
#define IICIF01 (((volatile __near __bitf_T *)0xFFE1)->no1)
|
||||
#define SRIF0 (((volatile __near __bitf_T *)0xFFE1)->no1)
|
||||
#define SREIF0 (((volatile __near __bitf_T *)0xFFE1)->no2)
|
||||
#define TMIF01H (((volatile __near __bitf_T *)0xFFE1)->no3)
|
||||
#define TMIF03H (((volatile __near __bitf_T *)0xFFE1)->no4)
|
||||
#define IICAIF0 (((volatile __near __bitf_T *)0xFFE1)->no5)
|
||||
#define TMIF00 (((volatile __near __bitf_T *)0xFFE1)->no6)
|
||||
#define TMIF01 (((volatile __near __bitf_T *)0xFFE1)->no7)
|
||||
#define IF1 (*(volatile __near unsigned short *)0xFFE2)
|
||||
#define IF1L (*(volatile __near unsigned char *)0xFFE2)
|
||||
#define IF1L_bit (*(volatile __near __bitf_T *)0xFFE2)
|
||||
#define TMIF02 (((volatile __near __bitf_T *)0xFFE2)->no0)
|
||||
#define TMIF03 (((volatile __near __bitf_T *)0xFFE2)->no1)
|
||||
#define ADIF (((volatile __near __bitf_T *)0xFFE2)->no2)
|
||||
#define TMKAIF (((volatile __near __bitf_T *)0xFFE2)->no3)
|
||||
#define KRIF (((volatile __near __bitf_T *)0xFFE2)->no4)
|
||||
#define MDIF (((volatile __near __bitf_T *)0xFFE2)->no5)
|
||||
#define FLIF (((volatile __near __bitf_T *)0xFFE2)->no6)
|
||||
#define MK0 (*(volatile __near unsigned short *)0xFFE4)
|
||||
#define MK0L (*(volatile __near unsigned char *)0xFFE4)
|
||||
#define MK0L_bit (*(volatile __near __bitf_T *)0xFFE4)
|
||||
#define MK0H (*(volatile __near unsigned char *)0xFFE5)
|
||||
#define MK0H_bit (*(volatile __near __bitf_T *)0xFFE5)
|
||||
#define WDTIMK (((volatile __near __bitf_T *)0xFFE4)->no0)
|
||||
#define LVIMK (((volatile __near __bitf_T *)0xFFE4)->no1)
|
||||
#define PMK0 (((volatile __near __bitf_T *)0xFFE4)->no2)
|
||||
#define PMK1 (((volatile __near __bitf_T *)0xFFE4)->no3)
|
||||
#define PMK2 (((volatile __near __bitf_T *)0xFFE4)->no4)
|
||||
#define PMK3 (((volatile __near __bitf_T *)0xFFE4)->no5)
|
||||
#define DMAMK0 (((volatile __near __bitf_T *)0xFFE4)->no6)
|
||||
#define DMAMK1 (((volatile __near __bitf_T *)0xFFE4)->no7)
|
||||
#define CSIMK00 (((volatile __near __bitf_T *)0xFFE5)->no0)
|
||||
#define IICMK00 (((volatile __near __bitf_T *)0xFFE5)->no0)
|
||||
#define STMK0 (((volatile __near __bitf_T *)0xFFE5)->no0)
|
||||
#define CSIMK01 (((volatile __near __bitf_T *)0xFFE5)->no1)
|
||||
#define IICMK01 (((volatile __near __bitf_T *)0xFFE5)->no1)
|
||||
#define SRMK0 (((volatile __near __bitf_T *)0xFFE5)->no1)
|
||||
#define SREMK0 (((volatile __near __bitf_T *)0xFFE5)->no2)
|
||||
#define TMMK01H (((volatile __near __bitf_T *)0xFFE5)->no3)
|
||||
#define TMMK03H (((volatile __near __bitf_T *)0xFFE5)->no4)
|
||||
#define IICAMK0 (((volatile __near __bitf_T *)0xFFE5)->no5)
|
||||
#define TMMK00 (((volatile __near __bitf_T *)0xFFE5)->no6)
|
||||
#define TMMK01 (((volatile __near __bitf_T *)0xFFE5)->no7)
|
||||
#define MK1 (*(volatile __near unsigned short *)0xFFE6)
|
||||
#define MK1L (*(volatile __near unsigned char *)0xFFE6)
|
||||
#define MK1L_bit (*(volatile __near __bitf_T *)0xFFE6)
|
||||
#define TMMK02 (((volatile __near __bitf_T *)0xFFE6)->no0)
|
||||
#define TMMK03 (((volatile __near __bitf_T *)0xFFE6)->no1)
|
||||
#define ADMK (((volatile __near __bitf_T *)0xFFE6)->no2)
|
||||
#define TMKAMK (((volatile __near __bitf_T *)0xFFE6)->no3)
|
||||
#define KRMK (((volatile __near __bitf_T *)0xFFE6)->no4)
|
||||
#define MDMK (((volatile __near __bitf_T *)0xFFE6)->no5)
|
||||
#define FLMK (((volatile __near __bitf_T *)0xFFE6)->no6)
|
||||
#define PR00 (*(volatile __near unsigned short *)0xFFE8)
|
||||
#define PR00L (*(volatile __near unsigned char *)0xFFE8)
|
||||
#define PR00L_bit (*(volatile __near __bitf_T *)0xFFE8)
|
||||
#define PR00H (*(volatile __near unsigned char *)0xFFE9)
|
||||
#define PR00H_bit (*(volatile __near __bitf_T *)0xFFE9)
|
||||
#define WDTIPR0 (((volatile __near __bitf_T *)0xFFE8)->no0)
|
||||
#define LVIPR0 (((volatile __near __bitf_T *)0xFFE8)->no1)
|
||||
#define PPR00 (((volatile __near __bitf_T *)0xFFE8)->no2)
|
||||
#define PPR01 (((volatile __near __bitf_T *)0xFFE8)->no3)
|
||||
#define PPR02 (((volatile __near __bitf_T *)0xFFE8)->no4)
|
||||
#define PPR03 (((volatile __near __bitf_T *)0xFFE8)->no5)
|
||||
#define DMAPR00 (((volatile __near __bitf_T *)0xFFE8)->no6)
|
||||
#define DMAPR01 (((volatile __near __bitf_T *)0xFFE8)->no7)
|
||||
#define CSIPR000 (((volatile __near __bitf_T *)0xFFE9)->no0)
|
||||
#define IICPR000 (((volatile __near __bitf_T *)0xFFE9)->no0)
|
||||
#define STPR00 (((volatile __near __bitf_T *)0xFFE9)->no0)
|
||||
#define CSIPR001 (((volatile __near __bitf_T *)0xFFE9)->no1)
|
||||
#define IICPR001 (((volatile __near __bitf_T *)0xFFE9)->no1)
|
||||
#define SRPR00 (((volatile __near __bitf_T *)0xFFE9)->no1)
|
||||
#define SREPR00 (((volatile __near __bitf_T *)0xFFE9)->no2)
|
||||
#define TMPR001H (((volatile __near __bitf_T *)0xFFE9)->no3)
|
||||
#define TMPR003H (((volatile __near __bitf_T *)0xFFE9)->no4)
|
||||
#define IICAPR00 (((volatile __near __bitf_T *)0xFFE9)->no5)
|
||||
#define TMPR000 (((volatile __near __bitf_T *)0xFFE9)->no6)
|
||||
#define TMPR001 (((volatile __near __bitf_T *)0xFFE9)->no7)
|
||||
#define PR01 (*(volatile __near unsigned short *)0xFFEA)
|
||||
#define PR01L (*(volatile __near unsigned char *)0xFFEA)
|
||||
#define PR01L_bit (*(volatile __near __bitf_T *)0xFFEA)
|
||||
#define TMPR002 (((volatile __near __bitf_T *)0xFFEA)->no0)
|
||||
#define TMPR003 (((volatile __near __bitf_T *)0xFFEA)->no1)
|
||||
#define ADPR0 (((volatile __near __bitf_T *)0xFFEA)->no2)
|
||||
#define TMKAPR0 (((volatile __near __bitf_T *)0xFFEA)->no3)
|
||||
#define KRPR0 (((volatile __near __bitf_T *)0xFFEA)->no4)
|
||||
#define MDPR0 (((volatile __near __bitf_T *)0xFFEA)->no5)
|
||||
#define FLPR0 (((volatile __near __bitf_T *)0xFFEA)->no6)
|
||||
#define PR10 (*(volatile __near unsigned short *)0xFFEC)
|
||||
#define PR10L (*(volatile __near unsigned char *)0xFFEC)
|
||||
#define PR10L_bit (*(volatile __near __bitf_T *)0xFFEC)
|
||||
#define PR10H (*(volatile __near unsigned char *)0xFFED)
|
||||
#define PR10H_bit (*(volatile __near __bitf_T *)0xFFED)
|
||||
#define WDTIPR1 (((volatile __near __bitf_T *)0xFFEC)->no0)
|
||||
#define LVIPR1 (((volatile __near __bitf_T *)0xFFEC)->no1)
|
||||
#define PPR10 (((volatile __near __bitf_T *)0xFFEC)->no2)
|
||||
#define PPR11 (((volatile __near __bitf_T *)0xFFEC)->no3)
|
||||
#define PPR12 (((volatile __near __bitf_T *)0xFFEC)->no4)
|
||||
#define PPR13 (((volatile __near __bitf_T *)0xFFEC)->no5)
|
||||
#define DMAPR10 (((volatile __near __bitf_T *)0xFFEC)->no6)
|
||||
#define DMAPR11 (((volatile __near __bitf_T *)0xFFEC)->no7)
|
||||
#define CSIPR100 (((volatile __near __bitf_T *)0xFFED)->no0)
|
||||
#define IICPR100 (((volatile __near __bitf_T *)0xFFED)->no0)
|
||||
#define STPR10 (((volatile __near __bitf_T *)0xFFED)->no0)
|
||||
#define CSIPR101 (((volatile __near __bitf_T *)0xFFED)->no1)
|
||||
#define IICPR101 (((volatile __near __bitf_T *)0xFFED)->no1)
|
||||
#define SRPR10 (((volatile __near __bitf_T *)0xFFED)->no1)
|
||||
#define SREPR10 (((volatile __near __bitf_T *)0xFFED)->no2)
|
||||
#define TMPR101H (((volatile __near __bitf_T *)0xFFED)->no3)
|
||||
#define TMPR103H (((volatile __near __bitf_T *)0xFFED)->no4)
|
||||
#define IICAPR10 (((volatile __near __bitf_T *)0xFFED)->no5)
|
||||
#define TMPR100 (((volatile __near __bitf_T *)0xFFED)->no6)
|
||||
#define TMPR101 (((volatile __near __bitf_T *)0xFFED)->no7)
|
||||
#define PR11 (*(volatile __near unsigned short *)0xFFEE)
|
||||
#define PR11L (*(volatile __near unsigned char *)0xFFEE)
|
||||
#define PR11L_bit (*(volatile __near __bitf_T *)0xFFEE)
|
||||
#define TMPR102 (((volatile __near __bitf_T *)0xFFEE)->no0)
|
||||
#define TMPR103 (((volatile __near __bitf_T *)0xFFEE)->no1)
|
||||
#define ADPR1 (((volatile __near __bitf_T *)0xFFEE)->no2)
|
||||
#define TMKAPR1 (((volatile __near __bitf_T *)0xFFEE)->no3)
|
||||
#define KRPR1 (((volatile __near __bitf_T *)0xFFEE)->no4)
|
||||
#define MDPR1 (((volatile __near __bitf_T *)0xFFEE)->no5)
|
||||
#define FLPR1 (((volatile __near __bitf_T *)0xFFEE)->no6)
|
||||
#define MDAL (*(volatile __near unsigned short *)0xFFF0)
|
||||
#define MULA (*(volatile __near unsigned short *)0xFFF0)
|
||||
#define MDAH (*(volatile __near unsigned short *)0xFFF2)
|
||||
#define MULB (*(volatile __near unsigned short *)0xFFF2)
|
||||
#define MDBH (*(volatile __near unsigned short *)0xFFF4)
|
||||
#define MULOH (*(volatile __near unsigned short *)0xFFF4)
|
||||
#define MDBL (*(volatile __near unsigned short *)0xFFF6)
|
||||
#define MULOL (*(volatile __near unsigned short *)0xFFF6)
|
||||
#define PMC (*(volatile __near unsigned char *)0xFFFE)
|
||||
#define PMC_bit (*(volatile __near __bitf_T *)0xFFFE)
|
||||
#define MAA (((volatile __near __bitf_T *)0xFFFE)->no0)
|
||||
|
||||
|
||||
#define INTWDTI 0x0004
|
||||
#define INTLVI 0x0006
|
||||
#define INTP0 0x0008
|
||||
#define INTP1 0x000A
|
||||
#define INTP2 0x000C
|
||||
#define INTP3 0x000E
|
||||
#define INTDMA0 0x0010
|
||||
#define INTDMA1 0x0012
|
||||
#define INTCSI00 0x0014
|
||||
#define INTIIC00 0x0014
|
||||
#define INTST0 0x0014
|
||||
#define INTCSI01 0x0016
|
||||
#define INTIIC01 0x0016
|
||||
#define INTSR0 0x0016
|
||||
#define INTSRE0 0x0018
|
||||
#define INTTM01H 0x001A
|
||||
#define INTTM03H 0x001C
|
||||
#define INTIICA0 0x001E
|
||||
#define INTTM00 0x0020
|
||||
#define INTTM01 0x0022
|
||||
#define INTTM02 0x0024
|
||||
#define INTTM03 0x0026
|
||||
#define INTAD 0x0028
|
||||
#define INTIT 0x002A
|
||||
#define INTKR 0x002C
|
||||
#define INTMD 0x002E
|
||||
#define INTFL 0x0030
|
||||
|
||||
#endif
|
||||
138
r_cg_adc.c
Normal file
138
r_cg_adc.c
Normal file
@ -0,0 +1,138 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_adc.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for ADC module.
|
||||
* Creation Date: 2023-10-05
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_adc.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_ADC_Create
|
||||
* Description : This function initializes the AD converter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_ADC_Create(void)
|
||||
{
|
||||
ADCEN = 1U; /* supply AD clock */
|
||||
ADM0 = _00_AD_ADM0_INITIALVALUE; /* disable AD conversion and clear ADM0 register */
|
||||
ADMK = 1U; /* disable INTAD interrupt */
|
||||
ADIF = 0U; /* clear INTAD interrupt flag */
|
||||
/* Set INTAD low priority */
|
||||
ADPR1 = 1U;
|
||||
ADPR0 = 1U;
|
||||
/* The reset status of ADPC is analog input, so it's unnecessary to set. */
|
||||
/* Set ANI0 - ANI1 pin as analog input */
|
||||
PM2 |= 0x03U;
|
||||
ADM0 = _08_AD_CONVERSION_CLOCK_32 | _00_AD_TIME_MODE_NORMAL_1 | _00_AD_OPERMODE_SELECT;
|
||||
ADM1 = _80_AD_TRIGGER_HARDWARE_NOWAIT | _20_AD_CONVMODE_ONESELECT | _00_AD_TRIGGER_INTTM01;
|
||||
ADM2 = _00_AD_POSITIVE_VDD | _00_AD_NEGATIVE_VSS | _00_AD_AREA_MODE_1 | _00_AD_RESOLUTION_10BIT;
|
||||
ADUL = _FF_AD_ADUL_VALUE;
|
||||
ADLL = _00_AD_ADLL_VALUE;
|
||||
ADS = _00_AD_INPUT_CHANNEL_0;
|
||||
ADCE = 1U; /* enable AD comparator */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_ADC_Start
|
||||
* Description : This function starts the AD converter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_ADC_Start(void)
|
||||
{
|
||||
ADIF = 0U; /* clear INTAD interrupt flag */
|
||||
ADMK = 0U; /* enable INTAD interrupt */
|
||||
ADCS = 1U; /* enable AD conversion */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_ADC_Stop
|
||||
* Description : This function stops the AD converter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_ADC_Stop(void)
|
||||
{
|
||||
ADCS = 0U; /* disable AD conversion */
|
||||
ADMK = 1U; /* disable INTAD interrupt */
|
||||
ADIF = 0U; /* clear INTAD interrupt flag */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_ADC_Set_OperationOn
|
||||
* Description : This function enables comparator operation.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_ADC_Set_OperationOn(void)
|
||||
{
|
||||
ADCE = 1U; /* enable AD comparator */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_ADC_Set_OperationOff
|
||||
* Description : This function stops comparator operation.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_ADC_Set_OperationOff(void)
|
||||
{
|
||||
ADCE = 0U; /* disable AD comparator */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_ADC_Get_Result
|
||||
* Description : This function returns the conversion result in the buffer.
|
||||
* Arguments : buffer -
|
||||
* the address where to write the conversion result
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_ADC_Get_Result(uint16_t * const buffer)
|
||||
{
|
||||
*buffer = (uint16_t)(ADCR >> 6U);
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
179
r_cg_adc.h
Normal file
179
r_cg_adc.h
Normal file
@ -0,0 +1,179 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_adc.h
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for ADC module.
|
||||
* Creation Date: 2023-10-05
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef ADC_H
|
||||
#define ADC_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
/*
|
||||
Peripheral enable register 0 (PER0)
|
||||
*/
|
||||
/* Control of AD converter input clock (ADCEN) */
|
||||
#define _00_AD_CLOCK_STOP (0x00U) /* stop supply of input clock */
|
||||
#define _20_AD_CLOCK_SUPPLY (0x20U) /* supply input clock */
|
||||
|
||||
/*
|
||||
AD converter mode register 0 (ADM0)
|
||||
*/
|
||||
#define _00_AD_ADM0_INITIALVALUE (0x00U)
|
||||
/* AD conversion operation control (ADCS) */
|
||||
#define _80_AD_CONVERSION_ENABLE (0x80U) /* enable AD conversion operation control */
|
||||
#define _00_AD_CONVERSION_DISABLE (0x00U) /* disable AD conversion operation control */
|
||||
/* Specification of AD conversion operation mode (ADMD) */
|
||||
#define _00_AD_OPERMODE_SELECT (0x00U) /* select operation mode */
|
||||
#define _40_AD_OPERMODE_SCAN (0x40U) /* scan operation mode */
|
||||
/* AD conversion clock selection (FR2 - FR0) */
|
||||
#define _00_AD_CONVERSION_CLOCK_64 (0x00U) /* fCLK/64 */
|
||||
#define _08_AD_CONVERSION_CLOCK_32 (0x08U) /* fCLK/32 */
|
||||
#define _10_AD_CONVERSION_CLOCK_16 (0x10U) /* fCLK/16 */
|
||||
#define _18_AD_CONVERSION_CLOCK_8 (0x18U) /* fCLK/8 */
|
||||
#define _20_AD_CONVERSION_CLOCK_6 (0x20U) /* fCLK/6 */
|
||||
#define _28_AD_CONVERSION_CLOCK_5 (0x28U) /* fCLK/5 */
|
||||
#define _30_AD_CONVERSION_CLOCK_4 (0x30U) /* fCLK/4 */
|
||||
#define _38_AD_CONVERSION_CLOCK_2 (0x38U) /* fCLK/2 */
|
||||
/* Specification AD conversion time mode (LV1, LV0) */
|
||||
#define _00_AD_TIME_MODE_NORMAL_1 (0x00U) /* normal 1 mode */
|
||||
#define _02_AD_TIME_MODE_NORMAL_2 (0x02U) /* normal 2 mode */
|
||||
#define _04_AD_TIME_MODE_LOWVOLTAGE_1 (0x04U) /* low-voltage 1 mode */
|
||||
#define _06_AD_TIME_MODE_LOWVOLTAGE_2 (0x06U) /* low-voltage 2 mode */
|
||||
/* AD comparator operation control (ADCE) */
|
||||
#define _01_AD_COMPARATOR_ENABLE (0x01U) /* enable comparator operation control */
|
||||
#define _00_AD_COMPARATOR_DISABLE (0x00U) /* disable comparator operation control */
|
||||
|
||||
/*
|
||||
Analog input channel specification register (ADS)
|
||||
*/
|
||||
/* Specification of analog input channel (ADISS, ADS4 - ADS0) */
|
||||
/* Select mode */
|
||||
#define _00_AD_INPUT_CHANNEL_0 (0x00U) /* ANI0 */
|
||||
#define _01_AD_INPUT_CHANNEL_1 (0x01U) /* ANI1 */
|
||||
#define _02_AD_INPUT_CHANNEL_2 (0x02U) /* ANI2 */
|
||||
#define _03_AD_INPUT_CHANNEL_3 (0x03U) /* ANI3 */
|
||||
#define _10_AD_INPUT_CHANNEL_16 (0x10U) /* ANI16 */
|
||||
#define _11_AD_INPUT_CHANNEL_17 (0x11U) /* ANI17 */
|
||||
#define _12_AD_INPUT_CHANNEL_18 (0x12U) /* ANI18 */
|
||||
#define _13_AD_INPUT_CHANNEL_19 (0x13U) /* ANI19 */
|
||||
#define _14_AD_INPUT_CHANNEL_20 (0x14U) /* ANI20 */
|
||||
#define _15_AD_INPUT_CHANNEL_21 (0x15U) /* ANI21 */
|
||||
#define _16_AD_INPUT_CHANNEL_22 (0x16U) /* ANI22 */
|
||||
#define _80_AD_INPUT_TEMPERSENSOR_0 (0x80U) /* temperature sensor 0 output is used to be the input channel */
|
||||
#define _81_AD_INPUT_INTERREFVOLT (0x81U) /* internal reference voltage output is used to be the input channel */
|
||||
/* Scan mode */
|
||||
#define _00_AD_INPUT_CHANNEL_0_3 (0x00U) /* ANI0 - ANI3 */
|
||||
|
||||
/*
|
||||
AD converter mode register 1 (ADM1)
|
||||
*/
|
||||
/* AD trigger mode selection (ADTMD1, ADTMD0) */
|
||||
#define _00_AD_TRIGGER_SOFTWARE (0x00U) /* software trigger mode */
|
||||
#define _80_AD_TRIGGER_HARDWARE_NOWAIT (0x80U) /* hardware trigger mode (no wait) */
|
||||
#define _C0_AD_TRIGGER_HARDWARE_WAIT (0xC0U) /* hardware trigger mode (wait) */
|
||||
/* AD convertion mode selection (ADSCM) */
|
||||
#define _00_AD_CONVMODE_CONSELECT (0x00U) /* continuous convertion mode */
|
||||
#define _20_AD_CONVMODE_ONESELECT (0x20U) /* oneshot convertion mode */
|
||||
/* Trigger signal selection (ADTRS1, ADTRS0) */
|
||||
#define _00_AD_TRIGGER_INTTM01 (0x00U) /* INTTM01 */
|
||||
#define _03_AD_TRIGGER_INTIT (0x03U) /* INTIT */
|
||||
|
||||
/*
|
||||
AD converter mode register 2 (ADM2)
|
||||
*/
|
||||
/* AD VREF(+) selection (ADREFP1, ADREFP0) */
|
||||
#define _00_AD_POSITIVE_VDD (0x00U) /* use VDD as VREF(+) */
|
||||
#define _40_AD_POSITIVE_AVREFP (0x40U) /* use AVREFP as VREF(+) */
|
||||
#define _80_AD_POSITIVE_INTERVOLT (0x80U) /* use internal voltage as VREF(+) */
|
||||
/* AD VREF(-) selection (ADREFM) */
|
||||
#define _00_AD_NEGATIVE_VSS (0x00U) /* use VSS as VREF(-) */
|
||||
#define _20_AD_NEGATIVE_AVREFM (0x20U) /* use AVREFM as VREF(-) */
|
||||
/* AD conversion result upper/lower bound value selection (ADRCK) */
|
||||
#define _00_AD_AREA_MODE_1 (0x00U) /* generates INTAD when ADLL <= ADCRH <= ADUL */
|
||||
#define _08_AD_AREA_MODE_2_3 (0x08U) /* generates INTAD when ADUL < ADCRH or ADLL > ADCRH */
|
||||
/* AD wakeup function selection (AWC) */
|
||||
#define _00_AD_WAKEUP_OFF (0x00U) /* stop wakeup function */
|
||||
#define _04_AD_WAKEUP_ON (0x04U) /* use wakeup function */
|
||||
/* AD resolution selection (ADTYP) */
|
||||
#define _00_AD_RESOLUTION_10BIT (0x00U) /* 10 bits */
|
||||
#define _01_AD_RESOLUTION_8BIT (0x01U) /* 8 bits */
|
||||
|
||||
/*
|
||||
AD test function register (ADTES)
|
||||
*/
|
||||
/* AD test mode signal (ADTES1, ADTES0) */
|
||||
#define _00_AD_NORMAL_INPUT (0x00U) /* normal mode */
|
||||
#define _02_AD_TEST_AVREFM (0x02U) /* use AVREFM as test signal */
|
||||
#define _03_AD_TEST_AVREFP (0x03U) /* use AVREFP as test signal */
|
||||
|
||||
/*
|
||||
AD port configuration register (ADPC)
|
||||
*/
|
||||
/* Analog input/digital input switching (ADPC3 - ADPC0) */
|
||||
#define _00_AD_ADPC_4ANALOG (0x00U) /* ANI0 - ANI3 */
|
||||
#define _04_AD_ADPC_3ANALOG (0x04U) /* ANI0 - ANI2 */
|
||||
#define _03_AD_ADPC_2ANALOG (0x03U) /* ANI0 - ANI1 */
|
||||
#define _02_AD_ADPC_1ANALOG (0x02U) /* ANI0 */
|
||||
#define _01_AD_ADPC_0ANALOG (0x01U) /* ANI0 - ANI4 (all digital) */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
/* Upper bound (ADUL) value */
|
||||
#define _FF_AD_ADUL_VALUE (0xFFU)
|
||||
/* Upper bound (ADLL) value */
|
||||
#define _00_AD_ADLL_VALUE (0x00U)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
ADCHANNEL0, ADCHANNEL1, ADCHANNEL2, ADCHANNEL3, ADCHANNEL16 = 16U,
|
||||
ADCHANNEL17, ADCHANNEL18, ADCHANNEL19, ADCHANNEL20, ADCHANNEL21,
|
||||
ADCHANNEL22, ADTEMPERSENSOR0 = 128U, ADINTERREFVOLT
|
||||
} ad_channel_t;
|
||||
typedef enum
|
||||
{
|
||||
ADNORMALINPUT,
|
||||
ADAVREFM = 2U,
|
||||
ADAVREFP
|
||||
} test_channel_t;
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_ADC_Create(void);
|
||||
void R_ADC_Start(void);
|
||||
void R_ADC_Stop(void);
|
||||
void R_ADC_Set_OperationOn(void);
|
||||
void R_ADC_Set_OperationOff(void);
|
||||
void R_ADC_Get_Result(uint16_t * const buffer);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
79
r_cg_adc_user.c
Normal file
79
r_cg_adc_user.c
Normal file
@ -0,0 +1,79 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_adc_user.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for ADC module.
|
||||
* Creation Date: 2023-10-05
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_adc.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
#pragma interrupt r_adc_interrupt(vect=INTAD)
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
uint16_t g_AdVal[3];
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_adc_interrupt
|
||||
* Description : This function is INTAD interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
static void __near r_adc_interrupt(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
switch (ADS)
|
||||
{
|
||||
case _00_AD_INPUT_CHANNEL_0:
|
||||
R_ADC_Get_Result(g_AdVal);
|
||||
ADS = _01_AD_INPUT_CHANNEL_1;
|
||||
break;
|
||||
case _01_AD_INPUT_CHANNEL_1:
|
||||
R_ADC_Get_Result(g_AdVal+1);
|
||||
ADS = _00_AD_INPUT_CHANNEL_0;
|
||||
break;
|
||||
default:
|
||||
ADS = _00_AD_INPUT_CHANNEL_0;
|
||||
break;
|
||||
}
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
69
r_cg_cgc.c
Normal file
69
r_cg_cgc.c
Normal file
@ -0,0 +1,69 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_cgc.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for CGC module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_cgc.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_CGC_Create
|
||||
* Description : This function initializes the clock generator.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_CGC_Create(void)
|
||||
{
|
||||
/* Set fMX */
|
||||
CMC = _00_CGC_HISYS_PORT | _00_CGC_SYSOSC_DEFAULT;
|
||||
MSTOP = 1U;
|
||||
/* Set fMAIN */
|
||||
MCM0 = 0U;
|
||||
OSMC = _00_CGC_IT_CLK_NO;
|
||||
/* Set fIH */
|
||||
HIOSTOP = 0U;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
146
r_cg_cgc.h
Normal file
146
r_cg_cgc.h
Normal file
@ -0,0 +1,146 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_cgc.h
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for CGC module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef CGC_H
|
||||
#define CGC_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
/*
|
||||
Clock operation mode control register (CMC)
|
||||
*/
|
||||
/* High-speed system clock pin operation mode (EXCLK, OSCSEL) */
|
||||
#define _C0_CGC_HISYS_PIN (0xC0U)
|
||||
#define _00_CGC_HISYS_PORT (0x00U) /* X1, X2 as I/O port */
|
||||
#define _40_CGC_HISYS_OSC (0x40U) /* X1, X2 as crystal/ceramic resonator connection */
|
||||
#define _80_CGC_HISYS_PORT1 (0x80U) /* X1, X2 as I/O port */
|
||||
#define _C0_CGC_HISYS_EXT (0xC0U) /* X1 as I/O port, X2 as external clock input */
|
||||
/* Control of X1 high-speed system clock oscillation frequency (AMPH) */
|
||||
#define _00_CGC_SYSOSC_DEFAULT (0x00U)
|
||||
#define _00_CGC_SYSOSC_UNDER10M (0x00U) /* fX <= 10MHz */
|
||||
#define _01_CGC_SYSOSC_OVER10M (0x01U) /* fX > 10MHz */
|
||||
|
||||
/*
|
||||
Clock operation status control register (CSC)
|
||||
*/
|
||||
/* Control of high-speed system clock operation (MSTOP) */
|
||||
#define _00_CGC_HISYS_OPER (0x00U) /* X1 oscillator/external clock operating */
|
||||
#define _80_CGC_HISYS_STOP (0x80U) /* X1 oscillator/external clock stopped */
|
||||
/* High-speed OCO operation (HIOSTOP) */
|
||||
#define _00_CGC_HIO_OPER (0x00U) /* high-speed OCO operating */
|
||||
#define _01_CGC_HIO_STOP (0x01U) /* high-speed OCO stopped */
|
||||
|
||||
/*
|
||||
Oscillation stabilization time counter status register (OSTC)
|
||||
*/
|
||||
/* Oscillation stabilization time status (MOST18 - MOST8) */
|
||||
#define _00_CGC_OSCSTAB_STA0 (0x00U) /* < 2^8/fX */
|
||||
#define _80_CGC_OSCSTAB_STA8 (0x80U) /* 2^8/fX */
|
||||
#define _C0_CGC_OSCSTAB_STA9 (0xC0U) /* 2^9/fX */
|
||||
#define _E0_CGC_OSCSTAB_STA10 (0xE0U) /* 2^10/fX */
|
||||
#define _F0_CGC_OSCSTAB_STA11 (0xF0U) /* 2^11/fX */
|
||||
#define _F8_CGC_OSCSTAB_STA13 (0xF8U) /* 2^13/fX */
|
||||
#define _FC_CGC_OSCSTAB_STA15 (0xFCU) /* 2^15/fX */
|
||||
#define _FE_CGC_OSCSTAB_STA17 (0xFEU) /* 2^17/fX */
|
||||
#define _FF_CGC_OSCSTAB_STA18 (0xFFU) /* 2^18/fX */
|
||||
|
||||
/*
|
||||
Oscillation stabilization time select register (OSTS)
|
||||
*/
|
||||
/* Oscillation stabilization time selection (OSTS2 - OSTS0) */
|
||||
#define _00_CGC_OSCSTAB_SEL8 (0x00U) /* 2^8/fX */
|
||||
#define _01_CGC_OSCSTAB_SEL9 (0x01U) /* 2^9/fX */
|
||||
#define _02_CGC_OSCSTAB_SEL10 (0x02U) /* 2^10/fX */
|
||||
#define _03_CGC_OSCSTAB_SEL11 (0x03U) /* 2^11/fX */
|
||||
#define _04_CGC_OSCSTAB_SEL13 (0x04U) /* 2^13/fX */
|
||||
#define _05_CGC_OSCSTAB_SEL15 (0x05U) /* 2^15/fX */
|
||||
#define _06_CGC_OSCSTAB_SEL17 (0x06U) /* 2^17/fX */
|
||||
#define _07_CGC_OSCSTAB_SEL18 (0x07U) /* 2^18/fX */
|
||||
|
||||
/*
|
||||
System clock control register (CKC)
|
||||
*/
|
||||
/* Status of Main system clock fMAIN (MCS) */
|
||||
#define _00_CGC_MAINCLK_HIO (0x00U) /* high-speed OCO clock (fIH) */
|
||||
#define _20_CGC_MAINCLK_HISYS (0x20U) /* high-speed system clock (fMX) */
|
||||
/* Selection of Main system clock fMAIN (MCM0) */
|
||||
#define _00_CGC_MAINCLK_SELHIO (0x00U) /* high-speed OCO clock (fIH) */
|
||||
#define _10_CGC_MAINCLK_SELHISYS (0x10U) /* high-speed system clock (fMX) */
|
||||
|
||||
/*
|
||||
Operation speed mode control register (OSMC)
|
||||
*/
|
||||
/* Interval timer unit input clock supply (WUTMMCK0) */
|
||||
#define _00_CGC_IT_CLK_NO (0x00U) /* stop */
|
||||
#define _10_CGC_IT_CLK_FIL (0x10U) /* use fIL clcok */
|
||||
|
||||
/*
|
||||
Illegal memory access detection control register (IAWCTL)
|
||||
*/
|
||||
/* Illegal memory access detection control (IAWEN) */
|
||||
#define _00_CGC_ILLEGAL_ACCESS_OFF (0x00U) /* disables illegal memory access detection */
|
||||
#define _80_CGC_ILLEGAL_ACCESS_ON (0x80U) /* enables illegal memory access detection */
|
||||
/* RAM guard area (GRAM1, GRAM0) */
|
||||
#define _00_CGC_RAM_GUARD_OFF (0x00U) /* invalid, it is possible to write RAM */
|
||||
#define _10_CGC_RAM_GUARD_ARAE0 (0x10U) /* 128 bytes from RAM bottom address */
|
||||
#define _20_CGC_RAM_GUARD_ARAE1 (0x20U) /* 256 bytes from RAM bottom address */
|
||||
#define _30_CGC_RAM_GUARD_ARAE2 (0x30U) /* 512 bytes from RAM bottom address */
|
||||
/* PORT register guard (GPORT) */
|
||||
#define _00_CGC_PORT_GUARD_OFF (0x00U) /* invalid, it is possible to write PORT register */
|
||||
#define _04_CGC_PORT_GUARD_ON (0x04U) /* valid, it is impossible to write PORT register, but possible for read */
|
||||
/* Interrupt register guard (GINT) */
|
||||
#define _00_CGC_INT_GUARD_OFF (0x00U) /* invalid, it is possible to write interrupt register */
|
||||
#define _02_CGC_INT_GUARD_ON (0x02U) /* valid, impossible to write interrupt register, but possible for read */
|
||||
/* CSC register guard (GCSC) */
|
||||
#define _00_CGC_CSC_GUARD_OFF (0x00U) /* invalid, it is possible to write CSC register */
|
||||
#define _01_CGC_CSC_GUARD_ON (0x01U) /* valid, it is impossible to write CSC register, but possible for read */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
typedef enum
|
||||
{
|
||||
HIOCLK,
|
||||
SYSX1CLK,
|
||||
SYSEXTCLK
|
||||
} clock_mode_t;
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_CGC_Create(void);
|
||||
void R_CGC_Get_ResetSource(void);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
64
r_cg_cgc_user.c
Normal file
64
r_cg_cgc_user.c
Normal file
@ -0,0 +1,64 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_cgc_user.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for CGC module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_cgc.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_CGC_Get_ResetSource
|
||||
* Description : This function process of Reset.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_CGC_Get_ResetSource(void)
|
||||
{
|
||||
uint8_t reset_flag = RESF;
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
88
r_cg_macrodriver.h
Normal file
88
r_cg_macrodriver.h
Normal file
@ -0,0 +1,88 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_macrodriver.h
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements general head file.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef STATUS_H
|
||||
#define STATUS_H
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "iodefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#ifndef __TYPEDEF__
|
||||
#define DI __DI
|
||||
#define EI __EI
|
||||
#define HALT __halt
|
||||
#define NOP __nop
|
||||
#define STOP __stop
|
||||
#define BRK __brk
|
||||
|
||||
/* Status list definition */
|
||||
#define MD_STATUSBASE (0x00U)
|
||||
#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */
|
||||
#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */
|
||||
#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */
|
||||
#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */
|
||||
#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */
|
||||
#define MD_OVERRUN (MD_STATUSBASE + 0x05U) /* IIC OVERRUN occur */
|
||||
|
||||
/* Error list definition */
|
||||
#define MD_ERRORBASE (0x80U)
|
||||
#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */
|
||||
#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error agrument input error */
|
||||
#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */
|
||||
#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */
|
||||
#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */
|
||||
#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */
|
||||
#endif
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
#ifndef __TYPEDEF__
|
||||
typedef signed char int8_t;
|
||||
typedef unsigned char uint8_t;
|
||||
typedef signed short int16_t;
|
||||
typedef unsigned short uint16_t;
|
||||
typedef signed long int32_t;
|
||||
typedef unsigned long uint32_t;
|
||||
typedef unsigned short MD_STATUS;
|
||||
#define __TYPEDEF__
|
||||
#endif
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#endif
|
||||
71
r_cg_port.c
Normal file
71
r_cg_port.c
Normal file
@ -0,0 +1,71 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_port.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for PORT module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_port.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_PORT_Create
|
||||
* Description : This function initializes the Port I/O.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_PORT_Create(void)
|
||||
{
|
||||
P1 = _01_Pn0_OUTPUT_1 | _02_Pn1_OUTPUT_1 | _04_Pn2_OUTPUT_1 | _08_Pn3_OUTPUT_1 | _10_Pn4_OUTPUT_1;
|
||||
P2 = _00_Pn2_OUTPUT_0 | _00_Pn3_OUTPUT_0;
|
||||
P4 = _02_Pn1_OUTPUT_1 | _04_Pn2_OUTPUT_1;
|
||||
PMC1 = _00_PMCn0_DI_ON | _00_PMCn1_DI_ON | _00_PMCn2_DI_ON | _00_PMCn3_DI_ON | _00_PMCn4_DI_ON | _E0_PMC1_DEFAULT;
|
||||
PMC4 = _00_PMCn1_DI_ON | _00_PMCn2_DI_ON | _F9_PMC4_DEFAULT;
|
||||
ADPC = _01_ADPC_DI_ON;
|
||||
PM1 = _00_PMn0_MODE_OUTPUT | _00_PMn1_MODE_OUTPUT | _00_PMn2_MODE_OUTPUT | _00_PMn3_MODE_OUTPUT |
|
||||
_00_PMn4_MODE_OUTPUT | _E0_PM1_DEFAULT;
|
||||
PM2 = _01_PMn0_MODE_INPUT | _02_PMn1_MODE_INPUT | _00_PMn2_MODE_OUTPUT | _00_PMn3_MODE_OUTPUT | _F0_PM2_DEFAULT;
|
||||
PM4 = _01_PMn0_NOT_USE | _00_PMn1_MODE_OUTPUT | _00_PMn2_MODE_OUTPUT | _F8_PM4_DEFAULT;
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
200
r_cg_port.h
Normal file
200
r_cg_port.h
Normal file
@ -0,0 +1,200 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_port.h
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for PORT module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef PORT_H
|
||||
#define PORT_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
/*
|
||||
Port Mode Register (PMm)
|
||||
*/
|
||||
/* Pmn pin I/O mode selection (PMm7 - PMm0) */
|
||||
#define _01_PMn0_NOT_USE (0x01U) /* not use Pn0 as digital I/O */
|
||||
#define _01_PMn0_MODE_INPUT (0x01U) /* use Pn0 as input mode */
|
||||
#define _00_PMn0_MODE_OUTPUT (0x00U) /* use Pn0 as output mode */
|
||||
#define _02_PMn1_NOT_USE (0x02U) /* not use Pn1 as digital I/O */
|
||||
#define _02_PMn1_MODE_INPUT (0x02U) /* use Pn1 as input mode */
|
||||
#define _00_PMn1_MODE_OUTPUT (0x00U) /* use Pn1 as output mode */
|
||||
#define _04_PMn2_NOT_USE (0x04U) /* not use Pn2 as digital I/O */
|
||||
#define _04_PMn2_MODE_INPUT (0x04U) /* use Pn2 as input mode */
|
||||
#define _00_PMn2_MODE_OUTPUT (0x00U) /* use Pn2 as output mode */
|
||||
#define _08_PMn3_NOT_USE (0x08U) /* not use Pn3 as digital I/O */
|
||||
#define _08_PMn3_MODE_INPUT (0x08U) /* use Pn3 as input mode */
|
||||
#define _00_PMn3_MODE_OUTPUT (0x00U) /* use Pn3 as output mode */
|
||||
#define _10_PMn4_NOT_USE (0x10U) /* not use Pn4 as digital I/O */
|
||||
#define _10_PMn4_MODE_INPUT (0x10U) /* use Pn4 as input mode */
|
||||
#define _00_PMn4_MODE_OUTPUT (0x00U) /* use Pn4 as output mode */
|
||||
#define _20_PMn5_NOT_USE (0x20U) /* not use Pn5 as digital I/O */
|
||||
#define _20_PMn5_MODE_INPUT (0x20U) /* use Pn5 as input mode */
|
||||
#define _00_PMn5_MODE_OUTPUT (0x00U) /* use Pn5 as output mode */
|
||||
#define _40_PMn6_NOT_USE (0x40U) /* not use Pn6 as digital I/O */
|
||||
#define _40_PMn6_MODE_INPUT (0x40U) /* use Pn6 as input mode */
|
||||
#define _00_PMn6_MODE_OUTPUT (0x00U) /* use Pn6 as output mode */
|
||||
#define _80_PMn7_NOT_USE (0x80U) /* not use Pn7 as digital I/O */
|
||||
#define _80_PMn7_MODE_INPUT (0x80U) /* use Pn7 as input mode */
|
||||
#define _00_PMn7_MODE_OUTPUT (0x00U) /* use Pn7 as output mode */
|
||||
|
||||
/*
|
||||
Port Register (Pm)
|
||||
*/
|
||||
/* Pmn pin data (Pm0 to Pm7) */
|
||||
#define _00_Pn0_OUTPUT_0 (0x00U) /* Pn0 output 0 */
|
||||
#define _01_Pn0_OUTPUT_1 (0x01U) /* Pn0 output 1 */
|
||||
#define _00_Pn1_OUTPUT_0 (0x00U) /* Pn1 output 0 */
|
||||
#define _02_Pn1_OUTPUT_1 (0x02U) /* Pn1 output 1 */
|
||||
#define _00_Pn2_OUTPUT_0 (0x00U) /* Pn2 output 0 */
|
||||
#define _04_Pn2_OUTPUT_1 (0x04U) /* Pn2 output 1 */
|
||||
#define _00_Pn3_OUTPUT_0 (0x00U) /* Pn3 output 0 */
|
||||
#define _08_Pn3_OUTPUT_1 (0x08U) /* Pn3 output 1 */
|
||||
#define _00_Pn4_OUTPUT_0 (0x00U) /* Pn4 output 0 */
|
||||
#define _10_Pn4_OUTPUT_1 (0x10U) /* Pn4 output 1 */
|
||||
#define _00_Pn5_OUTPUT_0 (0x00U) /* Pn5 output 0 */
|
||||
#define _20_Pn5_OUTPUT_1 (0x20U) /* Pn5 output 1 */
|
||||
#define _00_Pn6_OUTPUT_0 (0x00U) /* Pn6 output 0 */
|
||||
#define _40_Pn6_OUTPUT_1 (0x40U) /* Pn6 output 1 */
|
||||
#define _00_Pn7_OUTPUT_0 (0x00U) /* Pn7 output 0 */
|
||||
#define _80_Pn7_OUTPUT_1 (0x80U) /* Pn7 output 1 */
|
||||
|
||||
/*
|
||||
Pull-up Resistor Option Register (PUm)
|
||||
*/
|
||||
/* Pmn pin on-chip pull-up resistor selection (PUmn) */
|
||||
#define _00_PUn0_PULLUP_OFF (0x00U) /* Pn0 pull-up resistor not connected */
|
||||
#define _01_PUn0_PULLUP_ON (0x01U) /* Pn0 pull-up resistor connected */
|
||||
#define _00_PUn1_PULLUP_OFF (0x00U) /* Pn1 pull-up resistor not connected */
|
||||
#define _02_PUn1_PULLUP_ON (0x02U) /* Pn1 pull-up resistor connected */
|
||||
#define _00_PUn2_PULLUP_OFF (0x00U) /* Pn2 Pull-up resistor not connected */
|
||||
#define _04_PUn2_PULLUP_ON (0x04U) /* Pn2 pull-up resistor connected */
|
||||
#define _00_PUn3_PULLUP_OFF (0x00U) /* Pn3 pull-up resistor not connected */
|
||||
#define _08_PUn3_PULLUP_ON (0x08U) /* Pn3 pull-up resistor connected */
|
||||
#define _00_PUn4_PULLUP_OFF (0x00U) /* Pn4 pull-up resistor not connected */
|
||||
#define _10_PUn4_PULLUP_ON (0x10U) /* Pn4 pull-up resistor connected */
|
||||
#define _00_PUn5_PULLUP_OFF (0x00U) /* Pn5 pull-up resistor not connected */
|
||||
#define _20_PUn5_PULLUP_ON (0x20U) /* Pn5 pull-up resistor connected */
|
||||
#define _00_PUn6_PULLUP_OFF (0x00U) /* Pn6 pull-up resistor not connected */
|
||||
#define _40_PUn6_PULLUP_ON (0x40U) /* Pn6 pull-up resistor connected */
|
||||
#define _00_PUn7_PULLUP_OFF (0x00U) /* Pn7 pull-up resistor not connected */
|
||||
#define _80_PUn7_PULLUP_ON (0x80U) /* Pn7 pull-up resistor connected */
|
||||
|
||||
/*
|
||||
Port Input Mode Register (PIMm)
|
||||
*/
|
||||
/* Pmn pin input buffer selection (PIMmn) */
|
||||
#define _00_PIMn0_TTL_OFF (0x00U) /* set Pn0 normal input buffer */
|
||||
#define _01_PIMn0_TTL_ON (0x01U) /* set Pn0 TTL input buffer */
|
||||
#define _00_PIMn1_TTL_OFF (0x00U) /* set Pn1 normal input buffer */
|
||||
#define _02_PIMn1_TTL_ON (0x02U) /* set Pn1 TTL input buffer */
|
||||
#define _00_PIMn2_TTL_OFF (0x00U) /* set Pn2 normal input buffer */
|
||||
#define _04_PIMn2_TTL_ON (0x04U) /* set Pn2 TTL input buffer */
|
||||
#define _00_PIMn3_TTL_OFF (0x00U) /* set Pn3 normal input buffer */
|
||||
#define _08_PIMn3_TTL_ON (0x08U) /* set Pn3 TTL input buffer */
|
||||
#define _00_PIMn4_TTL_OFF (0x00U) /* set Pn4 normal input buffer */
|
||||
#define _10_PIMn4_TTL_ON (0x10U) /* set Pn4 TTL input buffer */
|
||||
#define _00_PIMn5_TTL_OFF (0x00U) /* set Pn5 normal input buffer */
|
||||
#define _20_PIMn5_TTL_ON (0x20U) /* set Pn5 TTL input buffer */
|
||||
#define _00_PIMn6_TTL_OFF (0x00U) /* set Pn6 normal input buffer */
|
||||
#define _40_PIMn6_TTL_ON (0x40U) /* set Pn6 TTL input buffer */
|
||||
#define _00_PIMn7_TTL_OFF (0x00U) /* set Pn7 normal input buffer */
|
||||
#define _80_PIMn7_TTL_ON (0x80U) /* set Pn7 TTL input buffer */
|
||||
|
||||
/*
|
||||
Port Output Mode Register (POMm)
|
||||
*/
|
||||
/* Pmn pin output mode selection (POMmn) */
|
||||
#define _00_POMn0_NCH_OFF (0x00U) /* set Pn0 output normal mode */
|
||||
#define _01_POMn0_NCH_ON (0x01U) /* set Pn0 output N-ch open-drain mode */
|
||||
#define _00_POMn1_NCH_OFF (0x00U) /* set Pn1 output normal mode */
|
||||
#define _02_POMn1_NCH_ON (0x02U) /* set Pn1 output N-ch open-drain mode */
|
||||
#define _00_POMn2_NCH_OFF (0x00U) /* set Pn2 output normal mode */
|
||||
#define _04_POMn2_NCH_ON (0x04U) /* set Pn2 output N-ch open-drain mode */
|
||||
#define _00_POMn3_NCH_OFF (0x00U) /* set Pn3 output normal mode */
|
||||
#define _08_POMn3_NCH_ON (0x08U) /* set Pn3 output N-ch open-drain mode */
|
||||
#define _00_POMn4_NCH_OFF (0x00U) /* set Pn4 output normal mode */
|
||||
#define _10_POMn4_NCH_ON (0x10U) /* set Pn4 output N-ch open-drain mode */
|
||||
#define _00_POMn5_NCH_OFF (0x00U) /* set Pn5 output normal mode */
|
||||
#define _20_POMn5_NCH_ON (0x20U) /* set Pn5 output N-ch open-drain mode */
|
||||
#define _00_POMn6_NCH_OFF (0x00U) /* set Pn6 output normal mode */
|
||||
#define _40_POMn6_NCH_ON (0x40U) /* set Pn6 output N-ch open-drain mode */
|
||||
#define _00_POMn7_NCH_OFF (0x00U) /* set Pn7 output normal mode */
|
||||
#define _80_POMn7_NCH_ON (0x80U) /* set Pn7 output N-ch open-drain mode */
|
||||
|
||||
/*
|
||||
Port Operation Mode Register (PMCm)
|
||||
*/
|
||||
/* Pmn pin digital input buffer selection (PMCmn) */
|
||||
#define _01_PMCn0_NOT_USE (0x01U) /* not use Pn0 digital input */
|
||||
#define _00_PMCn0_DI_ON (0x00U) /* enable Pn0 digital input */
|
||||
#define _02_PMCn1_NOT_USE (0x02U) /* not use Pn1 digital input */
|
||||
#define _00_PMCn1_DI_ON (0x00U) /* enable Pn1 digital input */
|
||||
#define _04_PMCn2_NOT_USE (0x04U) /* not use Pn2 digital input */
|
||||
#define _00_PMCn2_DI_ON (0x00U) /* enable Pn2 digital input */
|
||||
#define _08_PMCn3_NOT_USE (0x08U) /* not use Pn3 digital input */
|
||||
#define _00_PMCn3_DI_ON (0x00U) /* enable Pn3 digital input */
|
||||
#define _10_PMCn4_NOT_USE (0x10U) /* not use Pn4 digital input */
|
||||
#define _00_PMCn4_DI_ON (0x00U) /* enable Pn4 digital input */
|
||||
#define _20_PMCn5_NOT_USE (0x20U) /* not use Pn5 digital input */
|
||||
#define _00_PMCn5_DI_ON (0x00U) /* enable Pn5 digital input */
|
||||
#define _40_PMCn6_NOT_USE (0x40U) /* not use Pn6 digital input */
|
||||
#define _00_PMCn6_DI_ON (0x00U) /* enable Pn6 digital input */
|
||||
#define _80_PMCn7_NOT_USE (0x80U) /* not use Pn7 digital input */
|
||||
#define _00_PMCn7_DI_ON (0x00U) /* enable Pn7 digital input */
|
||||
|
||||
/*
|
||||
AD port configuration register (ADPC)
|
||||
*/
|
||||
/* Analog input/digital input switching (ADPC3 - ADPC0) */
|
||||
#define _00_ADPC_DI_OFF (0x00U) /* use P20 - P23 as analog input */
|
||||
#define _04_ADPC_DI_ON (0x04U) /* use P23 as digital input */
|
||||
#define _03_ADPC_DI_ON (0x03U) /* use P22 - P23 as digital input */
|
||||
#define _02_ADPC_DI_ON (0x02U) /* use P21 - P23 as digital input */
|
||||
#define _01_ADPC_DI_ON (0x01U) /* use P20 - P23 as digital input */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define _E0_PM1_DEFAULT (0xE0U) /* PM1 default value */
|
||||
#define _F0_PM2_DEFAULT (0xF0U) /* PM2 default value */
|
||||
#define _F8_PM4_DEFAULT (0xF8U) /* PM4 default value */
|
||||
#define _FC_PM6_DEFAULT (0xFCU) /* PM6 default value */
|
||||
#define _E0_PMC1_DEFAULT (0xE0U) /* PMC1 default value */
|
||||
#define _F9_PMC4_DEFAULT (0xF9U) /* PMC4 default value */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_PORT_Create(void);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
51
r_cg_port_user.c
Normal file
51
r_cg_port_user.c
Normal file
@ -0,0 +1,51 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_port_user.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for PORT module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_port.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
210
r_cg_serial.c
Normal file
210
r_cg_serial.c
Normal file
@ -0,0 +1,210 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_serial.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for Serial module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_serial.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
volatile uint8_t * gp_uart0_tx_address; /* uart0 transmit buffer address */
|
||||
volatile uint16_t g_uart0_tx_count; /* uart0 transmit data number */
|
||||
volatile uint8_t * gp_uart0_rx_address; /* uart0 receive buffer address */
|
||||
volatile uint16_t g_uart0_rx_count; /* uart0 receive data number */
|
||||
volatile uint16_t g_uart0_rx_length; /* uart0 receive data length */
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_SAU0_Create
|
||||
* Description : This function initializes the SAU0 module.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_SAU0_Create(void)
|
||||
{
|
||||
SAU0EN = 1U; /* supply SAU0 clock */
|
||||
NOP();
|
||||
NOP();
|
||||
NOP();
|
||||
NOP();
|
||||
SPS0 = _0004_SAU_CK00_FCLK_4 | _0040_SAU_CK01_FCLK_4;
|
||||
R_UART0_Create();
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_UART0_Create
|
||||
* Description : This function initializes the UART0 module.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_UART0_Create(void)
|
||||
{
|
||||
ST0 |= _0002_SAU_CH1_STOP_TRG_ON | _0001_SAU_CH0_STOP_TRG_ON; /* disable UART0 receive and transmit */
|
||||
STMK0 = 1U; /* disable INTST0 interrupt */
|
||||
STIF0 = 0U; /* clear INTST0 interrupt flag */
|
||||
SRMK0 = 1U; /* disable INTSR0 interrupt */
|
||||
SRIF0 = 0U; /* clear INTSR0 interrupt flag */
|
||||
SREMK0 = 1U; /* disable INTSRE0 interrupt */
|
||||
SREIF0 = 0U; /* clear INTSRE0 interrupt flag */
|
||||
/* Set INTST0 low priority */
|
||||
STPR10 = 1U;
|
||||
STPR00 = 1U;
|
||||
/* Set INTSR0 low priority */
|
||||
SRPR10 = 1U;
|
||||
SRPR00 = 1U;
|
||||
SMR00 = _0020_SAU_SMRMN_INITIALVALUE | _0000_SAU_CLOCK_SELECT_CK00 | _0000_SAU_TRIGGER_SOFTWARE |
|
||||
_0002_SAU_MODE_UART | _0000_SAU_TRANSFER_END;
|
||||
SCR00 = _8000_SAU_TRANSMISSION | _0000_SAU_INTSRE_MASK | _0300_SAU_PARITY_ODD | _0080_SAU_LSB | _0020_SAU_STOP_2 |
|
||||
_0007_SAU_LENGTH_8;
|
||||
SDR00 = _9A00_UART0_TRANSMIT_DIVISOR;
|
||||
NFEN0 |= _01_SAU_RXD0_FILTER_ON;
|
||||
SIR01 = _0004_SAU_SIRMN_FECTMN | _0002_SAU_SIRMN_PECTMN | _0001_SAU_SIRMN_OVCTMN; /* clear error flag */
|
||||
SMR01 = _0020_SAU_SMRMN_INITIALVALUE | _0000_SAU_CLOCK_SELECT_CK00 | _0100_SAU_TRIGGER_RXD | _0000_SAU_EDGE_FALL |
|
||||
_0002_SAU_MODE_UART | _0000_SAU_TRANSFER_END;
|
||||
SCR01 = _4000_SAU_RECEPTION | _0000_SAU_INTSRE_MASK | _0300_SAU_PARITY_ODD | _0080_SAU_LSB | _0010_SAU_STOP_1 |
|
||||
_0007_SAU_LENGTH_8;
|
||||
SDR01 = _9A00_UART0_RECEIVE_DIVISOR;
|
||||
SO0 |= _0001_SAU_CH0_DATA_OUTPUT_1;
|
||||
SOL0 |= _0000_SAU_CHANNEL0_NORMAL; /* output level normal */
|
||||
SOE0 |= _0001_SAU_CH0_OUTPUT_ENABLE; /* enable UART0 output */
|
||||
/* Set RxD0 pin */
|
||||
PM6 |= 0x02U;
|
||||
/* Set TxD0 pin */
|
||||
P6 |= 0x01U;
|
||||
PM6 &= 0xFEU;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_UART0_Start
|
||||
* Description : This function starts the UART0 module operation.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_UART0_Start(void)
|
||||
{
|
||||
SO0 |= _0001_SAU_CH0_DATA_OUTPUT_1; /* output level normal */
|
||||
SOE0 |= _0001_SAU_CH0_OUTPUT_ENABLE; /* enable UART0 output */
|
||||
SS0 |= _0002_SAU_CH1_START_TRG_ON | _0001_SAU_CH0_START_TRG_ON; /* enable UART0 receive and transmit */
|
||||
STIF0 = 0U; /* clear INTST0 interrupt flag */
|
||||
SRIF0 = 0U; /* clear INTSR0 interrupt flag */
|
||||
STMK0 = 0U; /* enable INTST0 interrupt */
|
||||
SRMK0 = 0U; /* enable INTSR0 interrupt */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_UART0_Stop
|
||||
* Description : This function stops the UART0 module operation.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_UART0_Stop(void)
|
||||
{
|
||||
STMK0 = 1U; /* disable INTST0 interrupt */
|
||||
SRMK0 = 1U; /* disable INTSR0 interrupt */
|
||||
ST0 |= _0002_SAU_CH1_STOP_TRG_ON | _0001_SAU_CH0_STOP_TRG_ON; /* disable UART0 receive and transmit */
|
||||
SOE0 &= ~_0001_SAU_CH0_OUTPUT_ENABLE; /* disable UART0 output */
|
||||
STIF0 = 0U; /* clear INTST0 interrupt flag */
|
||||
SRIF0 = 0U; /* clear INTSR0 interrupt flag */
|
||||
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_UART0_Receive
|
||||
* Description : This function receives UART0 data.
|
||||
* Arguments : rx_buf -
|
||||
* receive buffer pointer
|
||||
* rx_num -
|
||||
* buffer size
|
||||
* Return Value : status -
|
||||
* MD_OK or MD_ARGERROR
|
||||
***********************************************************************************************************************/
|
||||
MD_STATUS R_UART0_Receive(uint8_t * const rx_buf, uint16_t rx_num)
|
||||
{
|
||||
MD_STATUS status = MD_OK;
|
||||
|
||||
if (rx_num < 1U)
|
||||
{
|
||||
status = MD_ARGERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
g_uart0_rx_count = 0U;
|
||||
g_uart0_rx_length = rx_num;
|
||||
gp_uart0_rx_address = rx_buf;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_UART0_Send
|
||||
* Description : This function sends UART0 data.
|
||||
* Arguments : tx_buf -
|
||||
* transfer buffer pointer
|
||||
* tx_num -
|
||||
* buffer size
|
||||
* Return Value : status -
|
||||
* MD_OK or MD_ARGERROR
|
||||
***********************************************************************************************************************/
|
||||
MD_STATUS R_UART0_Send(uint8_t * const tx_buf, uint16_t tx_num)
|
||||
{
|
||||
MD_STATUS status = MD_OK;
|
||||
|
||||
if (tx_num < 1U)
|
||||
{
|
||||
status = MD_ARGERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
gp_uart0_tx_address = tx_buf;
|
||||
g_uart0_tx_count = tx_num;
|
||||
STMK0 = 1U; /* disable INTST0 interrupt */
|
||||
TXD0 = *gp_uart0_tx_address;
|
||||
gp_uart0_tx_address++;
|
||||
g_uart0_tx_count--;
|
||||
STMK0 = 0U; /* enable INTST0 interrupt */
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
399
r_cg_serial.h
Normal file
399
r_cg_serial.h
Normal file
@ -0,0 +1,399 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_serial.h
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for Serial module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef SERIAL_H
|
||||
#define SERIAL_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
/*
|
||||
Serial Clock Select Register m (SPSm)
|
||||
*/
|
||||
/* Section of operation clock (CKm0) (PRSm03 - PRSm00) */
|
||||
#define _0000_SAU_CK00_FCLK_0 (0x0000U) /* ck00 - fCLK */
|
||||
#define _0001_SAU_CK00_FCLK_1 (0x0001U) /* ck00 - fCLK/2^1 */
|
||||
#define _0002_SAU_CK00_FCLK_2 (0x0002U) /* ck00 - fCLK/2^2 */
|
||||
#define _0003_SAU_CK00_FCLK_3 (0x0003U) /* ck00 - fCLK/2^3 */
|
||||
#define _0004_SAU_CK00_FCLK_4 (0x0004U) /* ck00 - fCLK/2^4 */
|
||||
#define _0005_SAU_CK00_FCLK_5 (0x0005U) /* ck00 - fCLK/2^5 */
|
||||
#define _0006_SAU_CK00_FCLK_6 (0x0006U) /* ck00 - fCLK/2^6 */
|
||||
#define _0007_SAU_CK00_FCLK_7 (0x0007U) /* ck00 - fCLK/2^7 */
|
||||
#define _0008_SAU_CK00_FCLK_8 (0x0008U) /* ck00 - fCLK/2^8 */
|
||||
#define _0009_SAU_CK00_FCLK_9 (0x0009U) /* ck00 - fCLK/2^9 */
|
||||
#define _000A_SAU_CK00_FCLK_10 (0x000AU) /* ck00 - fCLK/2^10 */
|
||||
#define _000B_SAU_CK00_FCLK_11 (0x000BU) /* ck00 - fCLK/2^11 */
|
||||
#define _000C_SAU_CK00_FCLK_12 (0x000CU) /* ck00 - fCLK/2^12 */
|
||||
#define _000D_SAU_CK00_FCLK_13 (0x000DU) /* ck00 - fCLK/2^13 */
|
||||
#define _000E_SAU_CK00_FCLK_14 (0x000EU) /* ck00 - fCLK/2^14 */
|
||||
#define _000F_SAU_CK00_FCLK_15 (0x000FU) /* ck00 - fCLK/2^15 */
|
||||
/* Section of operation clock (CKm1) (PRSm13 - PRSm10) */
|
||||
#define _0000_SAU_CK01_FCLK_0 (0x0000U) /* ck01 - fCLK */
|
||||
#define _0010_SAU_CK01_FCLK_1 (0x0010U) /* ck01 - fCLK/2^1 */
|
||||
#define _0020_SAU_CK01_FCLK_2 (0x0020U) /* ck01 - fCLK/2^2 */
|
||||
#define _0030_SAU_CK01_FCLK_3 (0x0030U) /* ck01 - fCLK/2^3 */
|
||||
#define _0040_SAU_CK01_FCLK_4 (0x0040U) /* ck01 - fCLK/2^4 */
|
||||
#define _0050_SAU_CK01_FCLK_5 (0x0050U) /* ck01 - fCLK/2^5 */
|
||||
#define _0060_SAU_CK01_FCLK_6 (0x0060U) /* ck01 - fCLK/2^6 */
|
||||
#define _0070_SAU_CK01_FCLK_7 (0x0070U) /* ck01 - fCLK/2^7 */
|
||||
#define _0080_SAU_CK01_FCLK_8 (0x0080U) /* ck01 - fCLK/2^8 */
|
||||
#define _0090_SAU_CK01_FCLK_9 (0x0090U) /* ck01 - fCLK/2^9 */
|
||||
#define _00A0_SAU_CK01_FCLK_10 (0x00A0U) /* ck01 - fCLK/2^10 */
|
||||
#define _00B0_SAU_CK01_FCLK_11 (0x00B0U) /* ck01 - fCLK/2^11 */
|
||||
#define _00C0_SAU_CK01_FCLK_12 (0x00C0U) /* ck01 - fCLK/2^12 */
|
||||
#define _00D0_SAU_CK01_FCLK_13 (0x00D0U) /* ck01 - fCLK/2^13 */
|
||||
#define _00E0_SAU_CK01_FCLK_14 (0x00E0U) /* ck01 - fCLK/2^14 */
|
||||
#define _00F0_SAU_CK01_FCLK_15 (0x00F0U) /* ck01 - fCLK/2^15 */
|
||||
|
||||
/*
|
||||
Serial Mode Register mn (SMRmn)
|
||||
*/
|
||||
#define _0020_SAU_SMRMN_INITIALVALUE (0x0020U)
|
||||
/* Selection of macro clock (MCK) of channel n (CKSmn) */
|
||||
#define _0000_SAU_CLOCK_SELECT_CK00 (0x0000U) /* operation clock CK0 set by PRS register */
|
||||
#define _8000_SAU_CLOCK_SELECT_CK01 (0x8000U) /* operation clock CK1 set by PRS register */
|
||||
/* Selection of transfer clock (TCLK) of channel n (CCSmn) */
|
||||
#define _0000_SAU_CLOCK_MODE_CKS (0x0000U) /* divided operation clock MCK specified by CKSmn bit */
|
||||
#define _4000_SAU_CLOCK_MODE_TI0N (0x4000U) /* clock input from SCK pin (slave transfer in CSI mode) */
|
||||
/* Selection of start trigger source (STSmn) */
|
||||
#define _0000_SAU_TRIGGER_SOFTWARE (0x0000U) /* only software trigger is valid */
|
||||
#define _0100_SAU_TRIGGER_RXD (0x0100U) /* valid edge of RXD pin */
|
||||
/* Controls inversion of level of receive data of channel n in UART mode (SISmn0) */
|
||||
#define _0000_SAU_EDGE_FALL (0x0000U) /* falling edge is detected as the start bit */
|
||||
#define _0040_SAU_EDGE_RISING (0x0040U) /* rising edge is detected as the start bit */
|
||||
/* Setting of operation mode of channel n (MDmn2, MDmn1) */
|
||||
#define _0000_SAU_MODE_CSI (0x0000U) /* CSI mode */
|
||||
#define _0002_SAU_MODE_UART (0x0002U) /* UART mode */
|
||||
#define _0004_SAU_MODE_IIC (0x0004U) /* simplified IIC mode */
|
||||
/* Selection of interrupt source of channel n (MDmn0) */
|
||||
#define _0000_SAU_TRANSFER_END (0x0000U) /* transfer end interrupt */
|
||||
#define _0001_SAU_BUFFER_EMPTY (0x0001U) /* buffer empty interrupt */
|
||||
|
||||
/*
|
||||
Serial Communication Operation Setting Register mn (SCRmn)
|
||||
*/
|
||||
/* Setting of operation mode of channel n (TXEmn, RXEmn) */
|
||||
#define _0000_SAU_NOT_COMMUNICATION (0x0000U) /* does not start communication */
|
||||
#define _4000_SAU_RECEPTION (0x4000U) /* reception only */
|
||||
#define _8000_SAU_TRANSMISSION (0x8000U) /* transmission only */
|
||||
#define _C000_SAU_RECEPTION_TRANSMISSION (0xC000U) /* reception and transmission */
|
||||
/* Selection of data and clock phase in CSI mode (DAPmn, CKPmn) */
|
||||
#define _0000_SAU_TIMING_1 (0x0000U) /* type 1 */
|
||||
#define _1000_SAU_TIMING_2 (0x1000U) /* type 2 */
|
||||
#define _2000_SAU_TIMING_3 (0x2000U) /* type 3 */
|
||||
#define _3000_SAU_TIMING_4 (0x3000U) /* type 4 */
|
||||
/* Selection of masking of error interrupt signal (EOCmn) */
|
||||
#define _0000_SAU_INTSRE_MASK (0x0000U) /* masks error interrupt INTSREx */
|
||||
#define _0400_SAU_INTSRE_ENABLE (0x0400U) /* enables generation of error interrupt INTSREx */
|
||||
/* Setting of parity bit in UART mode (PTCmn1 - PTCmn0) */
|
||||
#define _0000_SAU_PARITY_NONE (0x0000U) /* none parity */
|
||||
#define _0100_SAU_PARITY_ZERO (0x0100U) /* zero parity */
|
||||
#define _0200_SAU_PARITY_EVEN (0x0200U) /* even parity */
|
||||
#define _0300_SAU_PARITY_ODD (0x0300U) /* odd parity */
|
||||
/* Selection of data transfer sequence in CSI and UART modes (DIRmn) */
|
||||
#define _0000_SAU_MSB (0x0000U) /* MSB */
|
||||
#define _0080_SAU_LSB (0x0080U) /* LSB */
|
||||
/* Setting of stop bit in UART mode (SLCmn1, SLCmn0) */
|
||||
#define _0000_SAU_STOP_NONE (0x0000U) /* none stop bit */
|
||||
#define _0010_SAU_STOP_1 (0x0010U) /* 1 stop bit */
|
||||
#define _0020_SAU_STOP_2 (0x0020U) /* 2 stop bits */
|
||||
/* Setting of data length in CSI and UART modes (DLSmn2 - DLSmn0) */
|
||||
#define _0005_SAU_LENGTH_9 (0x0005U) /* 9-bit data length */
|
||||
#define _0006_SAU_LENGTH_7 (0x0006U) /* 7-bit data length */
|
||||
#define _0007_SAU_LENGTH_8 (0x0007U) /* 8-bit data length */
|
||||
|
||||
/*
|
||||
Serial Output Level Register m (SOLm)
|
||||
*/
|
||||
/* Selects inversion of the level of the transmit data of channel n in UART mode */
|
||||
#define _0000_SAU_CHANNEL0_NORMAL (0x0000U) /* normal bit level */
|
||||
#define _0001_SAU_CHANNEL0_INVERTED (0x0001U) /* inverted bit level */
|
||||
#define _0000_SAU_CHANNEL1_NORMAL (0x0000U) /* normal bit level */
|
||||
#define _0002_SAU_CHANNEL1_INVERTED (0x0002U) /* inverted bit level */
|
||||
#define _0000_SAU_CHANNEL2_NORMAL (0x0000U) /* normal bit level */
|
||||
#define _0004_SAU_CHANNEL2_INVERTED (0x0004U) /* inverted bit level */
|
||||
#define _0000_SAU_CHANNEL3_NORMAL (0x0000U) /* normal bit level */
|
||||
#define _0008_SAU_CHANNEL3_INVERTED (0x0008U) /* inverted bit level */
|
||||
|
||||
/*
|
||||
Noise Filter Enable Register 0 (NFEN0)
|
||||
*/
|
||||
/* Use of noise filter */
|
||||
#define _00_SAU_RXD3_FILTER_OFF (0x00U) /* noise filter off */
|
||||
#define _40_SAU_RXD3_FILTER_ON (0x40U) /* noise filter on */
|
||||
#define _00_SAU_RXD2_FILTER_OFF (0x00U) /* noise filter off */
|
||||
#define _10_SAU_RXD2_FILTER_ON (0x10U) /* noise filter on */
|
||||
#define _00_SAU_RXD1_FILTER_OFF (0x00U) /* noise filter off */
|
||||
#define _04_SAU_RXD1_FILTER_ON (0x04U) /* noise filter on */
|
||||
#define _00_SAU_RXD0_FILTER_OFF (0x00U) /* noise filter off */
|
||||
#define _01_SAU_RXD0_FILTER_ON (0x01U) /* noise filter on */
|
||||
|
||||
/*
|
||||
Format of Serial Status Register mn (SSRmn)
|
||||
*/
|
||||
/* Communication status indication flag of channel n (TSFmn) */
|
||||
#define _0040_SAU_UNDER_EXECUTE (0x0040U) /* communication is under execution */
|
||||
/* Buffer register status indication flag of channel n (BFFmn) */
|
||||
#define _0020_SAU_VALID_STORED (0x0020U) /* valid data is stored in the SDRmn register */
|
||||
/* Framing error detection flag of channel n (FEFmn) */
|
||||
#define _0004_SAU_FRAM_ERROR (0x0004U) /* a framing error occurs during UART reception */
|
||||
/* Parity error detection flag of channel n (PEFmn) */
|
||||
#define _0002_SAU_PARITY_ERROR (0x0002U) /* a parity error occurs or ACK is not detected */
|
||||
/* Overrun error detection flag of channel n (OVFmn) */
|
||||
#define _0001_SAU_OVERRUN_ERROR (0x0001U) /* an overrun error occurs */
|
||||
|
||||
/*
|
||||
Serial Channel Start Register m (SSm)
|
||||
*/
|
||||
/* Operation start trigger of channel 0 (SSm0) */
|
||||
#define _0000_SAU_CH0_START_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0001_SAU_CH0_START_TRG_ON (0x0001U) /* sets SEm0 to 1 and enters the communication wait status */
|
||||
/* Operation start trigger of channel 1 (SSm1) */
|
||||
#define _0000_SAU_CH1_START_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0002_SAU_CH1_START_TRG_ON (0x0002U) /* sets SEm1 to 1 and enters the communication wait status */
|
||||
/* Operation start trigger of channel 2 (SSm2) */
|
||||
#define _0000_SAU_CH2_START_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0004_SAU_CH2_START_TRG_ON (0x0004U) /* sets SEm2 to 1 and enters the communication wait status */
|
||||
/* Operation start trigger of channel 3 (SSm3) */
|
||||
#define _0000_SAU_CH3_START_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0008_SAU_CH3_START_TRG_ON (0x0008U) /* sets SEm3 to 1 and enters the communication wait status */
|
||||
|
||||
/*
|
||||
Serial Channel Stop Register m (STm)
|
||||
*/
|
||||
/* Operation stop trigger of channel 0 (STm0) */
|
||||
#define _0000_SAU_CH0_STOP_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0001_SAU_CH0_STOP_TRG_ON (0x0001U) /* operation is stopped (stop trigger is generated) */
|
||||
/* Operation stop trigger of channel 1 (STm1) */
|
||||
#define _0000_SAU_CH1_STOP_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0002_SAU_CH1_STOP_TRG_ON (0x0002U) /* operation is stopped (stop trigger is generated) */
|
||||
/* Operation stop trigger of channel 2 (STm2) */
|
||||
#define _0000_SAU_CH2_STOP_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0004_SAU_CH2_STOP_TRG_ON (0x0004U) /* operation is stopped (stop trigger is generated) */
|
||||
/* Operation stop trigger of channel 3 (STm3) */
|
||||
#define _0000_SAU_CH3_STOP_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0008_SAU_CH3_STOP_TRG_ON (0x0008U) /* operation is stopped (stop trigger is generated) */
|
||||
|
||||
/*
|
||||
Format of Serial Flag Clear Trigger Register mn (SIRmn)
|
||||
*/
|
||||
/* Clear trigger of overrun error flag of channel n (OVCTmn) */
|
||||
#define _0001_SAU_SIRMN_OVCTMN (0x0001U)
|
||||
/* Clear trigger of parity error flag of channel n (PECTmn) */
|
||||
#define _0002_SAU_SIRMN_PECTMN (0x0002U)
|
||||
/* Clear trigger of framing error of channel n (FECTMN) */
|
||||
#define _0004_SAU_SIRMN_FECTMN (0x0004U)
|
||||
|
||||
/*
|
||||
Serial Output Enable Register m (SOEm)
|
||||
*/
|
||||
/* Serial output enable/disable of channel 0 (SOEm0) */
|
||||
#define _0001_SAU_CH0_OUTPUT_ENABLE (0x0001U) /* enables output by serial communication operation */
|
||||
#define _0000_SAU_CH0_OUTPUT_DISABLE (0x0000U) /* stops output by serial communication operation */
|
||||
/* Serial output enable/disable of channel 1 (SOEm1) */
|
||||
#define _0002_SAU_CH1_OUTPUT_ENABLE (0x0002U) /* enables output by serial communication operation */
|
||||
#define _0000_SAU_CH1_OUTPUT_DISABLE (0x0000U) /* stops output by serial communication operation */
|
||||
/* Serial output enable/disable of channel 2 (SOEm2) */
|
||||
#define _0004_SAU_CH2_OUTPUT_ENABLE (0x0004U) /* enables output by serial communication operation */
|
||||
#define _0000_SAU_CH2_OUTPUT_DISABLE (0x0000U) /* stops output by serial communication operation */
|
||||
/* Serial output enable/disable of channel 3 (SOEm3) */
|
||||
#define _0008_SAU_CH3_OUTPUT_ENABLE (0x0008U) /* enables output by serial communication operation */
|
||||
#define _0000_SAU_CH3_OUTPUT_DISABLE (0x0000U) /* stops output by serial communication operation */
|
||||
|
||||
/*
|
||||
Serial Output Register m (SOm)
|
||||
*/
|
||||
/* Serial data output of channel 0 (SOm0) */
|
||||
#define _0000_SAU_CH0_DATA_OUTPUT_0 (0x0000U) /* Serial data output value is "0" */
|
||||
#define _0001_SAU_CH0_DATA_OUTPUT_1 (0x0001U) /* Serial data output value is "1" */
|
||||
/* Serial data output of channel 1 (SOm1) */
|
||||
#define _0000_SAU_CH1_DATA_OUTPUT_0 (0x0000U) /* Serial data output value is "0" */
|
||||
#define _0002_SAU_CH1_DATA_OUTPUT_1 (0x0002U) /* Serial data output value is "1" */
|
||||
/* Serial data output of channel 2 (SOm2) */
|
||||
#define _0000_SAU_CH2_DATA_OUTPUT_0 (0x0000U) /* Serial data output value is "0" */
|
||||
#define _0004_SAU_CH2_DATA_OUTPUT_1 (0x0004U) /* Serial data output value is "1" */
|
||||
/* Serial data output of channel 3 (SOm3) */
|
||||
#define _0000_SAU_CH3_DATA_OUTPUT_0 (0x0000U) /* Serial data output value is "0" */
|
||||
#define _0008_SAU_CH3_DATA_OUTPUT_1 (0x0008U) /* Serial data output value is "1" */
|
||||
/* Serial clock output of channel 0 (CKOm0) */
|
||||
#define _0000_SAU_CH0_CLOCK_OUTPUT_0 (0x0000U) /* Serial clock output value is "0" */
|
||||
#define _0100_SAU_CH0_CLOCK_OUTPUT_1 (0x0100U) /* Serial clock output value is "1" */
|
||||
/* Serial clock output of channel 1 (CKOm1) */
|
||||
#define _0000_SAU_CH1_CLOCK_OUTPUT_0 (0x0000U) /* Serial clock output value is "0" */
|
||||
#define _0200_SAU_CH1_CLOCK_OUTPUT_1 (0x0200U) /* Serial clock output value is "1" */
|
||||
/* Serial clock output of channel 2 (CKOm2) */
|
||||
#define _0000_SAU_CH2_CLOCK_OUTPUT_0 (0x0000U) /* Serial clock output value is "0" */
|
||||
#define _0400_SAU_CH2_CLOCK_OUTPUT_1 (0x0400U) /* Serial clock output value is "1" */
|
||||
/* Serial clock output of channel 3 (CKOm3) */
|
||||
#define _0000_SAU_CH3_CLOCK_OUTPUT_0 (0x0000U) /* Serial clock output value is "0" */
|
||||
#define _0800_SAU_CH3_CLOCK_OUTPUT_1 (0x0800U) /* Serial clock output value is "1" */
|
||||
|
||||
/*
|
||||
SAU Standby Control Register m (SSCm)
|
||||
*/
|
||||
/* SAU Standby Wakeup Control Bit (SWC) */
|
||||
#define _0000_SAU_CH0_SNOOZE_OFF (0x0000U) /* disable start function from STOP state of chip */
|
||||
#define _0001_SAU_CH0_SNOOZE_ON (0x0001U) /* enable start function from STOP state of chip */
|
||||
|
||||
/* SAU used flag */
|
||||
#define _00_SAU_IIC_MASTER_FLAG_CLEAR (0x00U)
|
||||
#define _01_SAU_IIC_SEND_FLAG (0x01U)
|
||||
#define _02_SAU_IIC_RECEIVE_FLAG (0x02U)
|
||||
#define _04_SAU_IIC_SENDED_ADDRESS_FLAG (0x04U)
|
||||
|
||||
/*
|
||||
Input switch control register (ISC)
|
||||
*/
|
||||
/* Channel 0 SSI00 input setting in CSI communication and slave mode (SSIE00) */
|
||||
#define _00_SAU_SSI00_UNUSED (0x00U) /* disables SSI00 pin input */
|
||||
#define _80_SAU_SSI00_USED (0x80U) /* enables SSI00 pin input */
|
||||
|
||||
/*
|
||||
IICA Control Register (IICCTLn0)
|
||||
*/
|
||||
/* IIC operation enable (IICEn) */
|
||||
#define _00_IICA_OPERATION_DISABLE (0x00U) /* stop operation */
|
||||
#define _80_IICA_OPERATION_ENABLE (0x80U) /* enable operation */
|
||||
/* Exit from communications (LRELn) */
|
||||
#define _00_IICA_COMMUNICATION_NORMAL (0x00U) /* normal operation */
|
||||
#define _40_IICA_COMMUNICATION_EXIT (0x40U) /* exit from current communication */
|
||||
/* Wait cancellation (WRELn) */
|
||||
#define _00_IICA_WAIT_NOTCANCEL (0x00U) /* do not cancel wait */
|
||||
#define _20_IICA_WAIT_CANCEL (0x20U) /* cancel wait */
|
||||
/* Generation of interrupt when stop condition (SPIEn) */
|
||||
#define _00_IICA_STOPINT_DISABLE (0x00U) /* disable */
|
||||
#define _10_IICA_STOPINT_ENABLE (0x10U) /* enable */
|
||||
/* Wait and interrupt generation (WTIMn) */
|
||||
#define _00_IICA_WAITINT_CLK8FALLING (0x00U) /* generated at the eighth clock's falling edge */
|
||||
#define _08_IICA_WAITINT_CLK9FALLING (0x08U) /* generated at the ninth clock's falling edge */
|
||||
/* Acknowledgement control (ACKEn) */
|
||||
#define _00_IICA_ACK_DISABLE (0x00U) /* disable acknowledgement */
|
||||
#define _04_IICA_ACK_ENABLE (0x04U) /* enable acknowledgement */
|
||||
/* Start condition trigger (STTn) */
|
||||
#define _00_IICA_START_NOTGENERATE (0x00U) /* do not generate start condition */
|
||||
#define _02_IICA_START_GENERATE (0x02U) /* generate start condition */
|
||||
/* Stop condition trigger (SPTn) */
|
||||
#define _00_IICA_STOP_NOTGENERATE (0x00U) /* do not generate stop condition */
|
||||
#define _01_IICA_STOP_GENERATE (0x01U) /* generate stop condition */
|
||||
|
||||
/*
|
||||
IICA Status Register (IICSn)
|
||||
*/
|
||||
/* Master device status (MSTSn) */
|
||||
#define _00_IICA_STATUS_NOTMASTER (0x00U) /* slave device status or communication standby status */
|
||||
#define _80_IICA_STATUS_MASTER (0x80U) /* master device communication status */
|
||||
/* Detection of arbitration loss (ALDn) */
|
||||
#define _00_IICA_ARBITRATION_NO (0x00U) /* arbitration win or no arbitration */
|
||||
#define _40_IICA_ARBITRATION_LOSS (0x40U) /* arbitration loss */
|
||||
/* Detection of extension code reception (EXCn) */
|
||||
#define _00_IICA_EXTCODE_NOT (0x00U) /* extension code not received */
|
||||
#define _20_IICA_EXTCODE_RECEIVED (0x20U) /* extension code received */
|
||||
/* Detection of matching addresses (COIn) */
|
||||
#define _00_IICA_ADDRESS_NOTMATCH (0x00U) /* addresses do not match */
|
||||
#define _10_IICA_ADDRESS_MATCH (0x10U) /* addresses match */
|
||||
/* Detection of transmit/receive status (TRCn) */
|
||||
#define _00_IICA_STATUS_RECEIVE (0x00U) /* receive status */
|
||||
#define _08_IICA_STATUS_TRANSMIT (0x08U) /* transmit status */
|
||||
/* Detection of acknowledge signal (ACKDn) */
|
||||
#define _00_IICA_ACK_NOTDETECTED (0x00U) /* ACK signal was not detected */
|
||||
#define _04_IICA_ACK_DETECTED (0x04U) /* ACK signal was detected */
|
||||
/* Detection of start condition (STDn) */
|
||||
#define _00_IICA_START_NOTDETECTED (0x00U) /* start condition not detected */
|
||||
#define _02_IICA_START_DETECTED (0x02U) /* start condition detected */
|
||||
/* Detection of stop condition (SPDn) */
|
||||
#define _00_IICA_STOP_NOTDETECTED (0x00U) /* stop condition not detected */
|
||||
#define _01_IICA_STOP_DETECTED (0x01U) /* stop condition detected */
|
||||
|
||||
/*
|
||||
IICA Flag Register (IICFn)
|
||||
*/
|
||||
/* STT clear flag (STCFn) */
|
||||
#define _00_IICA_STARTFLAG_GENERATE (0x00U) /* generate start condition */
|
||||
#define _80_IICA_STARTFLAG_UNSUCCESSFUL (0x80U) /* start condition generation unsuccessful */
|
||||
/* IIC bus status flag (IICBSYn) */
|
||||
#define _00_IICA_BUS_RELEASE (0x00U) /* bus release status */
|
||||
#define _40_IICA_BUS_COMMUNICATION (0x40U) /* bus communication status */
|
||||
/* Initial start enable trigger (STCENn) */
|
||||
#define _00_IICA_START_WITHSTOP (0x00U) /* generate start condition upon detecting a stop condition */
|
||||
#define _02_IICA_START_WITHOUTSTOP (0x02U) /* generate start condition without detection of a stop condition */
|
||||
/* Communication reservation function disable bit (IICRSVn) */
|
||||
#define _00_IICA_RESERVATION_ENABLE (0x00U) /* enable communication reservation */
|
||||
#define _01_IICA_RESERVATION_DISABLE (0x01U) /* disable communication reservation */
|
||||
|
||||
/*
|
||||
IICA Control Register 1 (IICCTLn1)
|
||||
*/
|
||||
/* Control of address match wakeup (WUPn) */
|
||||
#define _00_IICA_WAKEUP_STOP (0x00U) /* stop address match wakeup function in STOP mode */
|
||||
#define _80_IICA_WAKEUP_ENABLE (0x80U) /* enable address match wakeup function in STOP mode */
|
||||
/* Detection of SCL0 pin level (CLDn) */
|
||||
#define _00_IICA_SCL_LOW (0x00U) /* detect clock line at low level */
|
||||
#define _20_IICA_SCL_HIGH (0x20U) /* detect clock line at high level */
|
||||
/* Detection of SDA0 pin level (DADn) */
|
||||
#define _00_IICA_SDA_LOW (0x00U) /* detect data line at low level */
|
||||
#define _10_IICA_SDA_HIGH (0x10U) /* detect data line at high level */
|
||||
/* Operation mode switching (SMCn) */
|
||||
#define _00_IICA_MODE_STANDARD (0x00U) /* operates in standard mode */
|
||||
#define _08_IICA_MODE_HIGHSPEED (0x08U) /* operates in high-speed mode */
|
||||
/* Digital filter operation control (DFCn) */
|
||||
#define _00_IICA_FILTER_OFF (0x00U) /* digital filter off */
|
||||
#define _04_IICA_FILTER_ON (0x04U) /* digital filter on */
|
||||
/* Operation of clock dividing frequency permission (PRSn) */
|
||||
#define _00_IICA_fCLK (0x00U) /* clock of dividing frequency operation (fCLK) */
|
||||
#define _01_IICA_fCLK_HALF (0x01U) /* 2 clock of dividing frequency operation (fCLK/2) */
|
||||
/* IICA used flag */
|
||||
#define _80_IICA_ADDRESS_COMPLETE (0x80U)
|
||||
#define _00_IICA_MASTER_FLAG_CLEAR (0x00U)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
#define _9A00_UART0_RECEIVE_DIVISOR (0x9A00U)
|
||||
#define _9A00_UART0_TRANSMIT_DIVISOR (0x9A00U)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_SAU0_Create(void);
|
||||
void R_UART0_Create(void);
|
||||
void R_UART0_Start(void);
|
||||
void R_UART0_Stop(void);
|
||||
MD_STATUS R_UART0_Send(uint8_t * const tx_buf, uint16_t tx_num);
|
||||
MD_STATUS R_UART0_Receive(uint8_t * const rx_buf, uint16_t rx_num);
|
||||
static void r_uart0_callback_error(uint8_t err_type);
|
||||
static void r_uart0_callback_receiveend(void);
|
||||
static void r_uart0_callback_sendend(void);
|
||||
static void r_uart0_callback_softwareoverrun(uint16_t rx_data);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
172
r_cg_serial_user.c
Normal file
172
r_cg_serial_user.c
Normal file
@ -0,0 +1,172 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_serial_user.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for Serial module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_serial.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
#include "appTask.h"
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
#pragma interrupt r_uart0_interrupt_send(vect=INTST0)
|
||||
#pragma interrupt r_uart0_interrupt_receive(vect=INTSR0)
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
extern volatile uint8_t * gp_uart0_tx_address; /* uart0 send buffer address */
|
||||
extern volatile uint16_t g_uart0_tx_count; /* uart0 send data number */
|
||||
extern volatile uint8_t * gp_uart0_rx_address; /* uart0 receive buffer address */
|
||||
extern volatile uint16_t g_uart0_rx_count; /* uart0 receive data number */
|
||||
extern volatile uint16_t g_uart0_rx_length; /* uart0 receive data length */
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
extern uint8_t g_rx_buf[3];
|
||||
extern uint8_t uart_sendend;
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_uart0_interrupt_receive
|
||||
* Description : This function is INTSR0 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
static void __near r_uart0_interrupt_receive(void)
|
||||
{
|
||||
volatile uint8_t rx_data;
|
||||
volatile uint8_t err_type;
|
||||
|
||||
err_type = (uint8_t)(SSR01 & 0x0007U);
|
||||
SIR01 = (uint16_t)err_type;
|
||||
|
||||
if (err_type != 0U)
|
||||
{
|
||||
r_uart0_callback_error(err_type);
|
||||
}
|
||||
|
||||
rx_data = RXD0;
|
||||
|
||||
if (g_uart0_rx_length > g_uart0_rx_count)
|
||||
{
|
||||
*gp_uart0_rx_address = rx_data;
|
||||
gp_uart0_rx_address++;
|
||||
g_uart0_rx_count++;
|
||||
|
||||
if (g_uart0_rx_length == g_uart0_rx_count)
|
||||
{
|
||||
r_uart0_callback_receiveend();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
r_uart0_callback_softwareoverrun(rx_data);
|
||||
}
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_uart0_interrupt_send
|
||||
* Description : This function is INTST0 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
static void __near r_uart0_interrupt_send(void)
|
||||
{
|
||||
if (g_uart0_tx_count > 0U)
|
||||
{
|
||||
TXD0 = *gp_uart0_tx_address;
|
||||
gp_uart0_tx_address++;
|
||||
g_uart0_tx_count--;
|
||||
}
|
||||
else
|
||||
{
|
||||
r_uart0_callback_sendend();
|
||||
}
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_uart0_callback_receiveend
|
||||
* Description : This function is a callback function when UART0 finishes reception.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
static void r_uart0_callback_receiveend(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
UART_Rx_Pro(g_rx_buf[0]);
|
||||
R_UART0_Receive(g_rx_buf,1);
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_uart0_callback_softwareoverrun
|
||||
* Description : This function is a callback function when UART0 receives an overflow data.
|
||||
* Arguments : rx_data -
|
||||
* receive data
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
static void r_uart0_callback_softwareoverrun(uint16_t rx_data)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_uart0_callback_sendend
|
||||
* Description : This function is a callback function when UART0 finishes transmission.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
static void r_uart0_callback_sendend(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
uart_sendend = 1;
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_uart0_callback_error
|
||||
* Description : This function is a callback function when UART0 reception error occurs.
|
||||
* Arguments : err_type -
|
||||
* error type value
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
static void r_uart0_callback_error(uint8_t err_type)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
120
r_cg_timer.c
Normal file
120
r_cg_timer.c
Normal file
@ -0,0 +1,120 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_timer.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for TAU module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_timer.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_TAU0_Create
|
||||
* Description : This function initializes the TAU0 module.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_TAU0_Create(void)
|
||||
{
|
||||
TAU0EN = 1U; /* supplies input clock */
|
||||
TPS0 = _0000_TAU_CKM0_FCLK_0 | _0000_TAU_CKM1_FCLK_0 | _0000_TAU_CKM2_FCLK_1 | _0000_TAU_CKM3_FCLK_8;
|
||||
/* Stop all channels */
|
||||
TT0 = _0001_TAU_CH0_STOP_TRG_ON | _0002_TAU_CH1_STOP_TRG_ON | _0004_TAU_CH2_STOP_TRG_ON |
|
||||
_0008_TAU_CH3_STOP_TRG_ON | _0200_TAU_CH1_H8_STOP_TRG_ON | _0800_TAU_CH3_H8_STOP_TRG_ON;
|
||||
/* Mask channel 0 interrupt */
|
||||
TMMK00 = 1U; /* disable INTTM00 interrupt */
|
||||
TMIF00 = 0U; /* clear INTTM00 interrupt flag */
|
||||
/* Mask channel 1 interrupt */
|
||||
TMMK01 = 1U; /* disable INTTM01 interrupt */
|
||||
TMIF01 = 0U; /* clear INTTM01 interrupt flag */
|
||||
/* Mask channel 1 higher 8 bits interrupt */
|
||||
TMMK01H = 1U; /* disable INTTM01H interrupt */
|
||||
TMIF01H = 0U; /* clear INTTM01H interrupt flag */
|
||||
/* Mask channel 2 interrupt */
|
||||
TMMK02 = 1U; /* disable INTTM02 interrupt */
|
||||
TMIF02 = 0U; /* clear INTTM02 interrupt flag */
|
||||
/* Mask channel 3 interrupt */
|
||||
TMMK03 = 1U; /* disable INTTM03 interrupt */
|
||||
TMIF03 = 0U; /* clear INTTM03 interrupt flag */
|
||||
/* Mask channel 3 higher 8 bits interrupt */
|
||||
TMMK03H = 1U; /* disable INTTM03H interrupt */
|
||||
TMIF03H = 0U; /* clear INTTM03H interrupt flag */
|
||||
/* Set INTTM00 low priority */
|
||||
TMPR100 = 1U;
|
||||
TMPR000 = 1U;
|
||||
/* Channel 0 used as interval timer */
|
||||
TMR00 = _0000_TAU_CLOCK_SELECT_CKM0 | _0000_TAU_CLOCK_MODE_CKS | _0000_TAU_COMBINATION_SLAVE |
|
||||
_0000_TAU_TRIGGER_SOFTWARE | _0000_TAU_MODE_INTERVAL_TIMER | _0000_TAU_START_INT_UNUSED;
|
||||
TDR00 = _5DBF_TAU_TDR00_VALUE;
|
||||
TO0 &= ~_0001_TAU_CH0_OUTPUT_VALUE_1;
|
||||
TOE0 &= ~_0001_TAU_CH0_OUTPUT_ENABLE;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_TAU0_Channel0_Start
|
||||
* Description : This function starts TAU0 channel 0 counter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_TAU0_Channel0_Start(void)
|
||||
{
|
||||
TMIF00 = 0U; /* clear INTTM00 interrupt flag */
|
||||
TMMK00 = 0U; /* enable INTTM00 interrupt */
|
||||
TS0 |= _0001_TAU_CH0_START_TRG_ON;
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_TAU0_Channel0_Stop
|
||||
* Description : This function stops TAU0 channel 0 counter.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_TAU0_Channel0_Stop(void)
|
||||
{
|
||||
TT0 |= _0001_TAU_CH0_STOP_TRG_ON;
|
||||
/* Mask channel 0 interrupt */
|
||||
TMMK00 = 1U; /* disable INTTM00 interrupt */
|
||||
TMIF00 = 0U; /* clear INTTM00 interrupt flag */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
315
r_cg_timer.h
Normal file
315
r_cg_timer.h
Normal file
@ -0,0 +1,315 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_timer.h
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for TAU module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef TAU_H
|
||||
#define TAU_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
/*
|
||||
Peripheral Enable Register 0 (PER0)
|
||||
*/
|
||||
/* Control of timer array unit 0 input clock (TAU0EN) */
|
||||
#define _00_TAU0_CLOCK_STOP (0x00U) /* stops supply of input clock */
|
||||
#define _01_TAU0_CLOCK_SUPPLY (0x01U) /* supplies input clock */
|
||||
|
||||
/*
|
||||
Timer Clock Select Register m (TPSm)
|
||||
*/
|
||||
/* Operating mode and clear mode selection (PRSm03 - PRSm00) */
|
||||
#define _0000_TAU_CKM0_FCLK_0 (0x0000U) /* ckm0 - fCLK */
|
||||
#define _0001_TAU_CKM0_FCLK_1 (0x0001U) /* ckm0 - fCLK/2^1 */
|
||||
#define _0002_TAU_CKM0_FCLK_2 (0x0002U) /* ckm0 - fCLK/2^2 */
|
||||
#define _0003_TAU_CKM0_FCLK_3 (0x0003U) /* ckm0 - fCLK/2^3 */
|
||||
#define _0004_TAU_CKM0_FCLK_4 (0x0004U) /* ckm0 - fCLK/2^4 */
|
||||
#define _0005_TAU_CKM0_FCLK_5 (0x0005U) /* ckm0 - fCLK/2^5 */
|
||||
#define _0006_TAU_CKM0_FCLK_6 (0x0006U) /* ckm0 - fCLK/2^6 */
|
||||
#define _0007_TAU_CKM0_FCLK_7 (0x0007U) /* ckm0 - fCLK/2^7 */
|
||||
#define _0008_TAU_CKM0_FCLK_8 (0x0008U) /* ckm0 - fCLK/2^8 */
|
||||
#define _0009_TAU_CKM0_FCLK_9 (0x0009U) /* ckm0 - fCLK/2^9 */
|
||||
#define _000A_TAU_CKM0_FCLK_10 (0x000AU) /* ckm0 - fCLK/2^10 */
|
||||
#define _000B_TAU_CKM0_FCLK_11 (0x000BU) /* ckm0 - fCLK/2^11 */
|
||||
#define _000C_TAU_CKM0_FCLK_12 (0x000CU) /* ckm0 - fCLK/2^12 */
|
||||
#define _000D_TAU_CKM0_FCLK_13 (0x000DU) /* ckm0 - fCLK/2^13 */
|
||||
#define _000E_TAU_CKM0_FCLK_14 (0x000EU) /* ckm0 - fCLK/2^14 */
|
||||
#define _000F_TAU_CKM0_FCLK_15 (0x000FU) /* ckm0 - fCLK/2^15 */
|
||||
/* Operating mode and clear mode selection (PRSm13 - PRSm10) */
|
||||
#define _0000_TAU_CKM1_FCLK_0 (0x0000U) /* ckm1 - fCLK */
|
||||
#define _0010_TAU_CKM1_FCLK_1 (0x0010U) /* ckm1 - fCLK/2^1 */
|
||||
#define _0020_TAU_CKM1_FCLK_2 (0x0020U) /* ckm1 - fCLK/2^2 */
|
||||
#define _0030_TAU_CKM1_FCLK_3 (0x0030U) /* ckm1 - fCLK/2^3 */
|
||||
#define _0040_TAU_CKM1_FCLK_4 (0x0040U) /* ckm1 - fCLK/2^4 */
|
||||
#define _0050_TAU_CKM1_FCLK_5 (0x0050U) /* ckm1 - fCLK/2^5 */
|
||||
#define _0060_TAU_CKM1_FCLK_6 (0x0060U) /* ckm1 - fCLK/2^6 */
|
||||
#define _0070_TAU_CKM1_FCLK_7 (0x0070U) /* ckm1 - fCLK/2^7 */
|
||||
#define _0080_TAU_CKM1_FCLK_8 (0x0080U) /* ckm1 - fCLK/2^8 */
|
||||
#define _0090_TAU_CKM1_FCLK_9 (0x0090U) /* ckm1 - fCLK/2^9 */
|
||||
#define _00A0_TAU_CKM1_FCLK_10 (0x00A0U) /* ckm1 - fCLK/2^10 */
|
||||
#define _00B0_TAU_CKM1_FCLK_11 (0x00B0U) /* ckm1 - fCLK/2^11 */
|
||||
#define _00C0_TAU_CKM1_FCLK_12 (0x00C0U) /* ckm1 - fCLK/2^12 */
|
||||
#define _00D0_TAU_CKM1_FCLK_13 (0x00D0U) /* ckm1 - fCLK/2^13 */
|
||||
#define _00E0_TAU_CKM1_FCLK_14 (0x00E0U) /* ckm1 - fCLK/2^14 */
|
||||
#define _00F0_TAU_CKM1_FCLK_15 (0x00F0U) /* ckm1 - fCLK/2^15 */
|
||||
/* Operating mode and clear mode selection (PRSm21 - PRSm20) */
|
||||
#define _0000_TAU_CKM2_FCLK_1 (0x0000U) /* ckm2 - fCLK/2^1 */
|
||||
#define _0100_TAU_CKM2_FCLK_2 (0x0100U) /* ckm2 - fCLK/2^2 */
|
||||
#define _0200_TAU_CKM2_FCLK_4 (0x0200U) /* ckm2 - fCLK/2^4 */
|
||||
#define _0300_TAU_CKM2_FCLK_6 (0x0300U) /* ckm2 - fCLK/2^6 */
|
||||
/* Operating mode and clear mode selection (PRSm31 - PRSm30) */
|
||||
#define _0000_TAU_CKM3_FCLK_8 (0x0000U) /* ckm2 - fCLK/2^8 */
|
||||
#define _1000_TAU_CKM3_FCLK_10 (0x1000U) /* ckm2 - fCLK/2^10 */
|
||||
#define _2000_TAU_CKM3_FCLK_12 (0x2000U) /* ckm2 - fCLK/2^12 */
|
||||
#define _3000_TAU_CKM3_FCLK_14 (0x3000U) /* ckm2 - fCLK/2^14 */
|
||||
|
||||
/*
|
||||
Timer Mode Register mn (TMRmn)
|
||||
*/
|
||||
/* Selection of macro clock (MCK) of channel n (CKSmn1 - CKSmn0) */
|
||||
#define _0000_TAU_CLOCK_SELECT_CKM0 (0x0000U) /* operation clock CK0 set by PRS register */
|
||||
#define _8000_TAU_CLOCK_SELECT_CKM1 (0x8000U) /* operation clock CK1 set by PRS register */
|
||||
#define _4000_TAU_CLOCK_SELECT_CKM2 (0x4000U) /* operation clock CK2 set by PRS register */
|
||||
#define _C000_TAU_CLOCK_SELECT_CKM3 (0xC000U) /* operation clock CK3 set by PRS register */
|
||||
/* Selection of count clock (CCK) of channel n (CCSmn) */
|
||||
#define _0000_TAU_CLOCK_MODE_CKS (0x0000U) /* macro clock MCK specified by CKSmn bit */
|
||||
#define _1000_TAU_CLOCK_MODE_TIMN (0x1000U) /* valid edge of input signal input from TImn pin */
|
||||
/* Selection of slave/master of channel n (MASTERmn) */
|
||||
#define _0000_TAU_COMBINATION_SLAVE (0x0000U) /* operates as slave channel */
|
||||
#define _0000_TAU_COMBINATION_MASTER (0x0000U) /* channel0 operates as master channel */
|
||||
#define _0800_TAU_COMBINATION_MASTER (0x0800U) /* channel2, 4, 6 operates as master channel */
|
||||
/* Operation explanation of channel 1 or 3 (SPLIT) */
|
||||
#define _0000_TAU_16BITS_MODE (0x0000U) /* operates as 16 bits timer */
|
||||
#define _0800_TAU_8BITS_MODE (0x0800U) /* operates as 8 bits timer */
|
||||
/* Setting of start trigger or capture trigger of channel n (STSmn2 - STSmn0) */
|
||||
#define _0000_TAU_TRIGGER_SOFTWARE (0x0000U) /* only software trigger start is valid */
|
||||
#define _0100_TAU_TRIGGER_TIMN_VALID (0x0100U) /* TImn input edge is used as a start/capture trigger */
|
||||
#define _0200_TAU_TRIGGER_TIMN_BOTH (0x0200U) /* TImn input edges are used as a start/capture trigger */
|
||||
#define _0400_TAU_TRIGGER_MASTER_INT (0x0400U) /* interrupt signal of the master channel is used */
|
||||
/* Selection of TImn pin input valid edge (CISmn1 - CISmn0) */
|
||||
#define _0000_TAU_TIMN_EDGE_FALLING (0x0000U) /* falling edge */
|
||||
#define _0040_TAU_TIMN_EDGE_RISING (0x0040U) /* rising edge */
|
||||
#define _0080_TAU_TIMN_EDGE_BOTH_LOW (0x0080U) /* both edges (when low-level width is measured) */
|
||||
#define _00C0_TAU_TIMN_EDGE_BOTH_HIGH (0x00C0U) /* both edges (when high-level width is measured) */
|
||||
/* Operation mode of channel n (MDmn3 - MDmn0) */
|
||||
#define _0000_TAU_MODE_INTERVAL_TIMER (0x0000U) /* interval timer mode */
|
||||
#define _0004_TAU_MODE_CAPTURE (0x0004U) /* capture mode */
|
||||
#define _0006_TAU_MODE_EVENT_COUNT (0x0006U) /* event counter mode */
|
||||
#define _0008_TAU_MODE_ONE_COUNT (0x0008U) /* one count mode */
|
||||
#define _000C_TAU_MODE_HIGHLOW_MEASURE (0x000CU) /* high-/low-level width measurement mode */
|
||||
#define _0001_TAU_MODE_PWM_MASTER (0x0001U) /* PWM Function (Master Channel) mode */
|
||||
#define _0009_TAU_MODE_PWM_SLAVE (0x0009U) /* PWM Function (Slave Channel) mode */
|
||||
#define _0008_TAU_MODE_ONESHOT (0x0008U) /* one-shot pulse output mode */
|
||||
/* Setting of starting counting and interrupt (MDmn0) */
|
||||
#define _0000_TAU_START_INT_UNUSED (0x0000U) /* interrupt is not generated when counting is started */
|
||||
#define _0001_TAU_START_INT_USED (0x0001U) /* interrupt is generated when counting is started */
|
||||
|
||||
/*
|
||||
Timer Status Register mn (TSRmn)
|
||||
*/
|
||||
/* Counter overflow status of channel n (OVF) */
|
||||
#define _0000_TAU_OVERFLOW_NOT_OCCURS (0x0000U) /* overflow does not occur */
|
||||
#define _0001_TAU_OVERFLOW_OCCURS (0x0001U) /* overflow occurs */
|
||||
|
||||
/*
|
||||
Timer Channel Enable Status Register m (TEm)
|
||||
*/
|
||||
/* Indication of operation enable/stop status of channel 0 (TEm0) */
|
||||
#define _0000_TAU_CH0_OPERATION_STOP (0x0000U) /* operation is stopped */
|
||||
#define _0001_TAU_CH0_OPERATION_ENABLE (0x0001U) /* operation is enabled */
|
||||
/* Indication of operation enable/stop status of channel 1 (TEm1) */
|
||||
#define _0000_TAU_CH1_OPERATION_STOP (0x0000U) /* operation is stopped */
|
||||
#define _0002_TAU_CH1_OPERATION_ENABLE (0x0002U) /* operation is enabled */
|
||||
/* Indication of operation enable/stop status of channel 2 (TEm2) */
|
||||
#define _0000_TAU_CH2_OPERATION_STOP (0x0000U) /* operation is stopped */
|
||||
#define _0004_TAU_CH2_OPERATION_ENABLE (0x0004U) /* operation is enabled */
|
||||
/* Indication of operation enable/stop status of channel 3 (TEm3) */
|
||||
#define _0000_TAU_CH3_OPERATION_STOP (0x0000U) /* operation is stopped */
|
||||
#define _0008_TAU_CH3_OPERATION_ENABLE (0x0008U) /* operation is enabled */
|
||||
/* Indication of operation enable/stop status of channel 1 higher 8 bits (TEHm1) */
|
||||
#define _0000_TAU_CH1_H8_OPERATION_STOP (0x0000U) /* operation is stopped */
|
||||
#define _0200_TAU_CH1_H8_OPERATION_ENABLE (0x0200U) /* operation is enabled */
|
||||
/* Indication of operation enable/stop status of channel 3 higher 8 bits (TEHm3) */
|
||||
#define _0000_TAU_CH3_H8_OPERATION_STOP (0x0000U) /* operation is stopped */
|
||||
#define _0800_TAU_CH3_H8_OPERATION_ENABLE (0x0800U) /* operation is enabled */
|
||||
|
||||
/*
|
||||
Timer Channel Start Register m (TSm)
|
||||
*/
|
||||
/* Operation enable (start) trigger of channel 0 (TSm0) */
|
||||
#define _0000_TAU_CH0_START_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0001_TAU_CH0_START_TRG_ON (0x0001U) /* operation is enabled (start trigger is generated) */
|
||||
/* Operation enable (start) trigger of channel 1 (TSm1) */
|
||||
#define _0000_TAU_CH1_START_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0002_TAU_CH1_START_TRG_ON (0x0002U) /* operation is enabled (start trigger is generated) */
|
||||
/* Operation enable (start) trigger of channel 2 (TSm2) */
|
||||
#define _0000_TAU_CH2_START_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0004_TAU_CH2_START_TRG_ON (0x0004U) /* operation is enabled (start trigger is generated) */
|
||||
/* Operation enable (start) trigger of channel 3 (TSm3) */
|
||||
#define _0000_TAU_CH3_START_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0008_TAU_CH3_START_TRG_ON (0x0008U) /* operation is enabled (start trigger is generated) */
|
||||
/* Operation enable (start) trigger of channel 1 higher 8 bits (TSHm1) */
|
||||
#define _0000_TAU_CH1_H8_START_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0200_TAU_CH1_H8_START_TRG_ON (0x0200U) /* operation is enabled (start trigger is generated) */
|
||||
/* Operation enable (start) trigger of channel 3 higher 8 bits (TSHm3) */
|
||||
#define _0000_TAU_CH3_H8_START_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0800_TAU_CH3_H8_START_TRG_ON (0x0800U) /* operation is enabled (start trigger is generated) */
|
||||
|
||||
/*
|
||||
Timer Channel Stop Register m (TTm)
|
||||
*/
|
||||
/* Operation stop trigger of channel 0 (TTm0) */
|
||||
#define _0000_TAU_CH0_STOP_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0001_TAU_CH0_STOP_TRG_ON (0x0001U) /* operation is stopped (stop trigger is generated) */
|
||||
/* Operation stop trigger of channel 1 (TTm1) */
|
||||
#define _0000_TAU_CH1_STOP_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0002_TAU_CH1_STOP_TRG_ON (0x0002U) /* operation is stopped (stop trigger is generated) */
|
||||
/* Operation stop trigger of channel 2 (TTm2) */
|
||||
#define _0000_TAU_CH2_STOP_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0004_TAU_CH2_STOP_TRG_ON (0x0004U) /* operation is stopped (stop trigger is generated) */
|
||||
/* Operation stop trigger of channel 3 (TTm3) */
|
||||
#define _0000_TAU_CH3_STOP_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0008_TAU_CH3_STOP_TRG_ON (0x0008U) /* operation is stopped (stop trigger is generated) */
|
||||
/* Operation stop trigger of channel 1 higher 8 bits (TTHm1) */
|
||||
#define _0000_TAU_CH1_H8_STOP_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0200_TAU_CH1_H8_STOP_TRG_ON (0x0200U) /* operation is stopped (stop trigger is generated) */
|
||||
/* Operation stop trigger of channel 3 higher 8 bits (TTHm3) */
|
||||
#define _0000_TAU_CH3_H8_STOP_TRG_OFF (0x0000U) /* no trigger operation */
|
||||
#define _0800_TAU_CH3_H8_STOP_TRG_ON (0x0800U) /* operation is stopped (stop trigger is generated) */
|
||||
|
||||
/*
|
||||
Timer Input Select Register m (TIS0)
|
||||
*/
|
||||
/* Selection of timer input used with channel 1 (TIS01 - TIS00) */
|
||||
#define _00_TAU_CH1_INPUT_TI01 (0x00U) /* input signal of timer input pin (TI01) */
|
||||
#define _01_TAU_CH1_INPUT_FIL (0x01U) /* internal low speed oscillation colock (fIL) */
|
||||
#define _10_TAU_CH1_INPUT_TI01 (0x10U) /* input signal of timer input pin (TI01) */
|
||||
|
||||
/*
|
||||
Timer Output Enable Register m (TOEm)
|
||||
*/
|
||||
/* Timer output enable/disable of channel 0 (TOEm0) */
|
||||
#define _0001_TAU_CH0_OUTPUT_ENABLE (0x0001U) /* the TOm0 operation enabled by count operation */
|
||||
#define _0000_TAU_CH0_OUTPUT_DISABLE (0x0000U) /* the TOm0 operation stopped by count operation */
|
||||
/* Timer output enable/disable of channel 1 (TOEm1) */
|
||||
#define _0002_TAU_CH1_OUTPUT_ENABLE (0x0002U) /* the TOm1 operation enabled by count operation */
|
||||
#define _0000_TAU_CH1_OUTPUT_DISABLE (0x0000U) /* the TOm1 operation stopped by count operation */
|
||||
/* Timer output enable/disable of channel 2 (TOEm2) */
|
||||
#define _0004_TAU_CH2_OUTPUT_ENABLE (0x0004U) /* the TOm2 operation enabled by count operation */
|
||||
#define _0000_TAU_CH2_OUTPUT_DISABLE (0x0000U) /* the TOm2 operation stopped by count operation */
|
||||
/* Timer output enable/disable of channel 3 (TOEm3) */
|
||||
#define _0008_TAU_CH3_OUTPUT_ENABLE (0x0008U) /* the TOm3 operation enabled by count operation */
|
||||
#define _0000_TAU_CH3_OUTPUT_DISABLE (0x0000U) /* the TOm3 operation stopped by count operation */
|
||||
|
||||
/*
|
||||
Timer Output Register m (TOm)
|
||||
*/
|
||||
/* Timer output of channel 0 (TOm0) */
|
||||
#define _0000_TAU_CH0_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */
|
||||
#define _0001_TAU_CH0_OUTPUT_VALUE_1 (0x0001U) /* timer output value is "1" */
|
||||
/* Timer output of channel 1 (TOm1) */
|
||||
#define _0000_TAU_CH1_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */
|
||||
#define _0002_TAU_CH1_OUTPUT_VALUE_1 (0x0002U) /* timer output value is "1" */
|
||||
/* Timer output of channel 2 (TOm2) */
|
||||
#define _0000_TAU_CH2_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */
|
||||
#define _0004_TAU_CH2_OUTPUT_VALUE_1 (0x0004U) /* timer output value is "1" */
|
||||
/* Timer output of channel 3 (TOm3) */
|
||||
#define _0000_TAU_CH3_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */
|
||||
#define _0008_TAU_CH3_OUTPUT_VALUE_1 (0x0008U) /* timer output value is "1" */
|
||||
|
||||
/*
|
||||
Timer Output Level Register 0 (TOLm)
|
||||
*/
|
||||
/* Control of timer output level of channel 1 (TOLm1) */
|
||||
#define _0000_TAU_CH1_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */
|
||||
#define _0002_TAU_CH1_OUTPUT_LEVEL_L (0x0002U) /* inverted output (active-low) */
|
||||
/* Control of timer output level of channel 2 (TOLm2) */
|
||||
#define _0000_TAU_CH2_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */
|
||||
#define _0004_TAU_CH2_OUTPUT_LEVEL_L (0x0004U) /* inverted output (active-low) */
|
||||
/* Control of timer output level of channel 3 (TOLm3) */
|
||||
#define _0000_TAU_CH3_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */
|
||||
#define _0008_TAU_CH3_OUTPUT_LEVEL_L (0x0008U) /* inverted output (active-low) */
|
||||
|
||||
/*
|
||||
Timer Output Mode Register m (TOMm)
|
||||
*/
|
||||
/* Control of timer output mode of channel 1 (TOMm1) */
|
||||
#define _0000_TAU_CH1_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */
|
||||
#define _0002_TAU_CH1_OUTPUT_COMBIN (0x0002U) /* combination operation mode */
|
||||
/* Control of timer output mode of channel 2 (TOMm2) */
|
||||
#define _0000_TAU_CH2_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */
|
||||
#define _0004_TAU_CH2_OUTPUT_COMBIN (0x0004U) /* combination operation mode */
|
||||
/* Control of timer output mode of channel 3 (TOMm3) */
|
||||
#define _0000_TAU_CH3_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */
|
||||
#define _0008_TAU_CH3_OUTPUT_COMBIN (0x0008U) /* combination operation mode */
|
||||
|
||||
/*
|
||||
Input Switch Control Register (ISC)
|
||||
*/
|
||||
/* Switching channel 7 input of timer array unit (ISC1) */
|
||||
#define _00_TAU_CH7_NO_INPUT (0x00U) /* timer input is not used */
|
||||
#define _02_TAU_CH7_RXD3_INPUT (0x02U) /* input signal of RxD3 pin is used as timer input */
|
||||
|
||||
/*
|
||||
Noise Filter Enable Register 1 (NFEN1)
|
||||
*/
|
||||
/* Enable/disable using noise filter of TI03 pin input signal (TNFEN03) */
|
||||
#define _00_TAU_CH3_NOISE_OFF (0x00U) /* noise filter OFF */
|
||||
#define _08_TAU_CH3_NOISE_ON (0x08U) /* noise filter ON */
|
||||
/* Enable/disable using noise filter of TI02 pin input signal (TNFEN02) */
|
||||
#define _00_TAU_CH2_NOISE_OFF (0x00U) /* noise filter OFF */
|
||||
#define _04_TAU_CH2_NOISE_ON (0x04U) /* noise filter ON */
|
||||
/* Enable/disable using noise filter of TI01 pin input signal (TNFEN01) */
|
||||
#define _00_TAU_CH1_NOISE_OFF (0x00U) /* noise filter OFF */
|
||||
#define _02_TAU_CH1_NOISE_ON (0x02U) /* noise filter ON */
|
||||
/* Enable/disable using noise filter of TI00 pin input signal (TNFEN00) */
|
||||
#define _00_TAU_CH0_NOISE_OFF (0x00U) /* noise filter OFF */
|
||||
#define _01_TAU_CH0_NOISE_ON (0x01U) /* noise filter ON */
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
/* 16-bit timer data register 00 (TDR00) */
|
||||
#define _5DBF_TAU_TDR00_VALUE (0x5DBFU)
|
||||
/* Clock divisor for TAU0 channel 0 */
|
||||
#define _0001_TAU0_CHANNEL0_DIVISOR (0x0001U)
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_TAU0_Create(void);
|
||||
void R_TAU0_Channel0_Start(void);
|
||||
void R_TAU0_Channel0_Stop(void);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
66
r_cg_timer_user.c
Normal file
66
r_cg_timer_user.c
Normal file
@ -0,0 +1,66 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_timer_user.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for TAU module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_timer.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
#include "event.h"
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
#pragma interrupt r_tau0_channel0_interrupt(vect=INTTM00)
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: r_tau0_channel0_interrupt
|
||||
* Description : This function is INTTM00 interrupt service routine.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
static void __near r_tau0_channel0_interrupt(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
TimeBaseCount();
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
38
r_cg_userdefine.h
Normal file
38
r_cg_userdefine.h
Normal file
@ -0,0 +1,38 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_userdefine.h
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file includes user definition.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef _USER_DEF_H
|
||||
#define _USER_DEF_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
User definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
74
r_cg_wdt.c
Normal file
74
r_cg_wdt.c
Normal file
@ -0,0 +1,74 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_wdt.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for WDT module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_wdt.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_WDT_Create
|
||||
* Description : This function initializes the watchdogtimer.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_WDT_Create(void)
|
||||
{
|
||||
WDTIMK = 1U; /* disable INTWDTI interrupt */
|
||||
WDTIIF = 0U; /* clear INTWDTI interrupt flag */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_WDT_Restart
|
||||
* Description : This function restarts the watchdog timer.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_WDT_Restart(void)
|
||||
{
|
||||
WDTE = 0xACU; /* restart watchdog timer */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
52
r_cg_wdt.h
Normal file
52
r_cg_wdt.h
Normal file
@ -0,0 +1,52 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_wdt.h
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for WDT module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
#ifndef WDT_H
|
||||
#define WDT_H
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions (Register bit)
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Macro definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Typedef definitions
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global functions
|
||||
***********************************************************************************************************************/
|
||||
void R_WDT_Create(void);
|
||||
void R_WDT_Restart(void);
|
||||
|
||||
/* Start user code for function. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#endif
|
||||
51
r_cg_wdt_user.c
Normal file
51
r_cg_wdt_user.c
Normal file
@ -0,0 +1,51 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_cg_wdt_user.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements device driver for WDT module.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_wdt.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
90
r_main.c
Normal file
90
r_main.c
Normal file
@ -0,0 +1,90 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_main.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements main function.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_cgc.h"
|
||||
#include "r_cg_port.h"
|
||||
#include "r_cg_serial.h"
|
||||
#include "r_cg_timer.h"
|
||||
#include "r_cg_wdt.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
#include "appTask.h"
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
void R_MAIN_UserInit(void);
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: main
|
||||
* Description : This function implements main function.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void main(void)
|
||||
{
|
||||
R_MAIN_UserInit();
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
HardWare_Init();
|
||||
Variable_Init();
|
||||
|
||||
while (1U)
|
||||
{
|
||||
AppTask();
|
||||
}
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_MAIN_UserInit
|
||||
* Description : This function adds user code before implementing main function.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_MAIN_UserInit(void)
|
||||
{
|
||||
/* Start user code. Do not edit comment generated here */
|
||||
EI();
|
||||
/* End user code. Do not edit comment generated here */
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
86
r_systeminit.c
Normal file
86
r_systeminit.c
Normal file
@ -0,0 +1,86 @@
|
||||
/***********************************************************************************************************************
|
||||
* DISCLAIMER
|
||||
* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
|
||||
* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
* applicable laws, including copyright laws.
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
|
||||
* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
|
||||
* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
|
||||
* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
* following link:
|
||||
* http://www.renesas.com/disclaimer
|
||||
*
|
||||
* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* File Name : r_systeminit.c
|
||||
* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
|
||||
* Device(s) : R5F10268
|
||||
* Tool-Chain : CCRL
|
||||
* Description : This file implements system initializing function.
|
||||
* Creation Date: 2024-05-24
|
||||
***********************************************************************************************************************/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Includes
|
||||
***********************************************************************************************************************/
|
||||
#include "r_cg_macrodriver.h"
|
||||
#include "r_cg_cgc.h"
|
||||
#include "r_cg_port.h"
|
||||
#include "r_cg_serial.h"
|
||||
#include "r_cg_timer.h"
|
||||
#include "r_cg_wdt.h"
|
||||
/* Start user code for include. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
#include "r_cg_userdefine.h"
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Pragma directive
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for pragma. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
Global variables and functions
|
||||
***********************************************************************************************************************/
|
||||
/* Start user code for global. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: R_Systeminit
|
||||
* Description : This function initializes every macro.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void R_Systeminit(void)
|
||||
{
|
||||
PIOR = 0x02U;
|
||||
R_CGC_Get_ResetSource();
|
||||
R_CGC_Create();
|
||||
R_PORT_Create();
|
||||
R_SAU0_Create();
|
||||
R_TAU0_Create();
|
||||
R_WDT_Create();
|
||||
IAWCTL = 0x00U;
|
||||
}
|
||||
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* Function Name: hdwinit
|
||||
* Description : This function initializes hardware setting.
|
||||
* Arguments : None
|
||||
* Return Value : None
|
||||
***********************************************************************************************************************/
|
||||
void hdwinit(void)
|
||||
{
|
||||
DI();
|
||||
R_Systeminit();
|
||||
}
|
||||
|
||||
/* Start user code for adding. Do not edit comment generated here */
|
||||
/* End user code. Do not edit comment generated here */
|
||||
77
stkinit.asm
Normal file
77
stkinit.asm
Normal file
@ -0,0 +1,77 @@
|
||||
;/**********************************************************************************************************************
|
||||
; * DISCLAIMER
|
||||
; * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No
|
||||
; * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
|
||||
; * applicable laws, including copyright laws.
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
|
||||
; * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
|
||||
; * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM
|
||||
; * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES
|
||||
; * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO
|
||||
; * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
; * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of
|
||||
; * this software. By using this software, you agree to the additional terms and conditions found by accessing the
|
||||
; * following link:
|
||||
; * http://www.renesas.com/disclaimer
|
||||
; *
|
||||
; * Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
|
||||
; *********************************************************************************************************************/;---------------------------------------------------------------------
|
||||
; _stkinit
|
||||
;
|
||||
; void _stkinit(void __near * stackbss);
|
||||
;
|
||||
; input:
|
||||
; stackbss = AX (#LOWW(_stackend))
|
||||
; output:
|
||||
; NONE
|
||||
;---------------------------------------------------------------------
|
||||
|
||||
; NOTE : THIS IS A TYPICAL EXAMPLE.
|
||||
|
||||
.PUBLIC _stkinit
|
||||
|
||||
.textf .CSEG TEXTF
|
||||
_stkinit:
|
||||
MOVW HL,AX ; stack_end_addr
|
||||
MOV [SP+3],#0x00 ; [SP+0]-[SP+2] for return address
|
||||
MOVW AX,SP
|
||||
SUBW AX,HL ; SUBW AX,#LOWW _@STEND
|
||||
BNH $LSTINIT3 ; goto end
|
||||
SHRW AX,5 ; loop count for 32 byte transfer
|
||||
MOVW BC,AX
|
||||
CLRW AX
|
||||
LSTINIT1:
|
||||
CMPW AX,BC
|
||||
BZ $LSTINIT2
|
||||
MOVW [HL],AX
|
||||
MOVW [HL+2],AX
|
||||
MOVW [HL+4],AX
|
||||
MOVW [HL+6],AX
|
||||
MOVW [HL+8],AX
|
||||
MOVW [HL+10],AX
|
||||
MOVW [HL+12],AX
|
||||
MOVW [HL+14],AX
|
||||
MOVW [HL+16],AX
|
||||
MOVW [HL+18],AX
|
||||
MOVW [HL+20],AX
|
||||
MOVW [HL+22],AX
|
||||
MOVW [HL+24],AX
|
||||
MOVW [HL+26],AX
|
||||
MOVW [HL+28],AX
|
||||
MOVW [HL+30],AX
|
||||
XCHW AX,HL
|
||||
ADDW AX,#0x20
|
||||
XCHW AX,HL
|
||||
DECW BC
|
||||
BR $LSTINIT1
|
||||
LSTINIT2:
|
||||
MOVW AX,SP
|
||||
CMPW AX,HL
|
||||
BZ $LSTINIT3 ; goto end
|
||||
CLRW AX
|
||||
MOVW [HL],AX
|
||||
INCW HL
|
||||
INCW HL
|
||||
BR $LSTINIT2
|
||||
LSTINIT3:
|
||||
RET
|
||||
Loading…
x
Reference in New Issue
Block a user