316 lines
21 KiB
C
316 lines
21 KiB
C
/***********************************************************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
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* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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* applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
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* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
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* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
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* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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*
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* Copyright (C) 2011, 2021 Renesas Electronics Corporation. All rights reserved.
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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* File Name : r_cg_timer.h
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* Version : CodeGenerator for RL78/G12 V2.04.06.02 [08 Nov 2021]
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* Device(s) : R5F10268
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* Tool-Chain : CCRL
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* Description : This file implements device driver for TAU module.
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* Creation Date: 2024-05-24
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***********************************************************************************************************************/
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#ifndef TAU_H
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#define TAU_H
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/***********************************************************************************************************************
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Macro definitions (Register bit)
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***********************************************************************************************************************/
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/*
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Peripheral Enable Register 0 (PER0)
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*/
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/* Control of timer array unit 0 input clock (TAU0EN) */
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#define _00_TAU0_CLOCK_STOP (0x00U) /* stops supply of input clock */
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#define _01_TAU0_CLOCK_SUPPLY (0x01U) /* supplies input clock */
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/*
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Timer Clock Select Register m (TPSm)
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*/
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/* Operating mode and clear mode selection (PRSm03 - PRSm00) */
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#define _0000_TAU_CKM0_FCLK_0 (0x0000U) /* ckm0 - fCLK */
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#define _0001_TAU_CKM0_FCLK_1 (0x0001U) /* ckm0 - fCLK/2^1 */
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#define _0002_TAU_CKM0_FCLK_2 (0x0002U) /* ckm0 - fCLK/2^2 */
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#define _0003_TAU_CKM0_FCLK_3 (0x0003U) /* ckm0 - fCLK/2^3 */
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#define _0004_TAU_CKM0_FCLK_4 (0x0004U) /* ckm0 - fCLK/2^4 */
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#define _0005_TAU_CKM0_FCLK_5 (0x0005U) /* ckm0 - fCLK/2^5 */
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#define _0006_TAU_CKM0_FCLK_6 (0x0006U) /* ckm0 - fCLK/2^6 */
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#define _0007_TAU_CKM0_FCLK_7 (0x0007U) /* ckm0 - fCLK/2^7 */
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#define _0008_TAU_CKM0_FCLK_8 (0x0008U) /* ckm0 - fCLK/2^8 */
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#define _0009_TAU_CKM0_FCLK_9 (0x0009U) /* ckm0 - fCLK/2^9 */
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#define _000A_TAU_CKM0_FCLK_10 (0x000AU) /* ckm0 - fCLK/2^10 */
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#define _000B_TAU_CKM0_FCLK_11 (0x000BU) /* ckm0 - fCLK/2^11 */
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#define _000C_TAU_CKM0_FCLK_12 (0x000CU) /* ckm0 - fCLK/2^12 */
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#define _000D_TAU_CKM0_FCLK_13 (0x000DU) /* ckm0 - fCLK/2^13 */
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#define _000E_TAU_CKM0_FCLK_14 (0x000EU) /* ckm0 - fCLK/2^14 */
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#define _000F_TAU_CKM0_FCLK_15 (0x000FU) /* ckm0 - fCLK/2^15 */
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/* Operating mode and clear mode selection (PRSm13 - PRSm10) */
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#define _0000_TAU_CKM1_FCLK_0 (0x0000U) /* ckm1 - fCLK */
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#define _0010_TAU_CKM1_FCLK_1 (0x0010U) /* ckm1 - fCLK/2^1 */
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#define _0020_TAU_CKM1_FCLK_2 (0x0020U) /* ckm1 - fCLK/2^2 */
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#define _0030_TAU_CKM1_FCLK_3 (0x0030U) /* ckm1 - fCLK/2^3 */
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#define _0040_TAU_CKM1_FCLK_4 (0x0040U) /* ckm1 - fCLK/2^4 */
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#define _0050_TAU_CKM1_FCLK_5 (0x0050U) /* ckm1 - fCLK/2^5 */
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#define _0060_TAU_CKM1_FCLK_6 (0x0060U) /* ckm1 - fCLK/2^6 */
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#define _0070_TAU_CKM1_FCLK_7 (0x0070U) /* ckm1 - fCLK/2^7 */
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#define _0080_TAU_CKM1_FCLK_8 (0x0080U) /* ckm1 - fCLK/2^8 */
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#define _0090_TAU_CKM1_FCLK_9 (0x0090U) /* ckm1 - fCLK/2^9 */
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#define _00A0_TAU_CKM1_FCLK_10 (0x00A0U) /* ckm1 - fCLK/2^10 */
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#define _00B0_TAU_CKM1_FCLK_11 (0x00B0U) /* ckm1 - fCLK/2^11 */
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#define _00C0_TAU_CKM1_FCLK_12 (0x00C0U) /* ckm1 - fCLK/2^12 */
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#define _00D0_TAU_CKM1_FCLK_13 (0x00D0U) /* ckm1 - fCLK/2^13 */
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#define _00E0_TAU_CKM1_FCLK_14 (0x00E0U) /* ckm1 - fCLK/2^14 */
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#define _00F0_TAU_CKM1_FCLK_15 (0x00F0U) /* ckm1 - fCLK/2^15 */
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/* Operating mode and clear mode selection (PRSm21 - PRSm20) */
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#define _0000_TAU_CKM2_FCLK_1 (0x0000U) /* ckm2 - fCLK/2^1 */
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#define _0100_TAU_CKM2_FCLK_2 (0x0100U) /* ckm2 - fCLK/2^2 */
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#define _0200_TAU_CKM2_FCLK_4 (0x0200U) /* ckm2 - fCLK/2^4 */
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#define _0300_TAU_CKM2_FCLK_6 (0x0300U) /* ckm2 - fCLK/2^6 */
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/* Operating mode and clear mode selection (PRSm31 - PRSm30) */
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#define _0000_TAU_CKM3_FCLK_8 (0x0000U) /* ckm2 - fCLK/2^8 */
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#define _1000_TAU_CKM3_FCLK_10 (0x1000U) /* ckm2 - fCLK/2^10 */
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#define _2000_TAU_CKM3_FCLK_12 (0x2000U) /* ckm2 - fCLK/2^12 */
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#define _3000_TAU_CKM3_FCLK_14 (0x3000U) /* ckm2 - fCLK/2^14 */
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/*
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Timer Mode Register mn (TMRmn)
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*/
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/* Selection of macro clock (MCK) of channel n (CKSmn1 - CKSmn0) */
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#define _0000_TAU_CLOCK_SELECT_CKM0 (0x0000U) /* operation clock CK0 set by PRS register */
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#define _8000_TAU_CLOCK_SELECT_CKM1 (0x8000U) /* operation clock CK1 set by PRS register */
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#define _4000_TAU_CLOCK_SELECT_CKM2 (0x4000U) /* operation clock CK2 set by PRS register */
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#define _C000_TAU_CLOCK_SELECT_CKM3 (0xC000U) /* operation clock CK3 set by PRS register */
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/* Selection of count clock (CCK) of channel n (CCSmn) */
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#define _0000_TAU_CLOCK_MODE_CKS (0x0000U) /* macro clock MCK specified by CKSmn bit */
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#define _1000_TAU_CLOCK_MODE_TIMN (0x1000U) /* valid edge of input signal input from TImn pin */
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/* Selection of slave/master of channel n (MASTERmn) */
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#define _0000_TAU_COMBINATION_SLAVE (0x0000U) /* operates as slave channel */
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#define _0000_TAU_COMBINATION_MASTER (0x0000U) /* channel0 operates as master channel */
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#define _0800_TAU_COMBINATION_MASTER (0x0800U) /* channel2, 4, 6 operates as master channel */
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/* Operation explanation of channel 1 or 3 (SPLIT) */
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#define _0000_TAU_16BITS_MODE (0x0000U) /* operates as 16 bits timer */
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#define _0800_TAU_8BITS_MODE (0x0800U) /* operates as 8 bits timer */
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/* Setting of start trigger or capture trigger of channel n (STSmn2 - STSmn0) */
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#define _0000_TAU_TRIGGER_SOFTWARE (0x0000U) /* only software trigger start is valid */
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#define _0100_TAU_TRIGGER_TIMN_VALID (0x0100U) /* TImn input edge is used as a start/capture trigger */
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#define _0200_TAU_TRIGGER_TIMN_BOTH (0x0200U) /* TImn input edges are used as a start/capture trigger */
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#define _0400_TAU_TRIGGER_MASTER_INT (0x0400U) /* interrupt signal of the master channel is used */
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/* Selection of TImn pin input valid edge (CISmn1 - CISmn0) */
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#define _0000_TAU_TIMN_EDGE_FALLING (0x0000U) /* falling edge */
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#define _0040_TAU_TIMN_EDGE_RISING (0x0040U) /* rising edge */
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#define _0080_TAU_TIMN_EDGE_BOTH_LOW (0x0080U) /* both edges (when low-level width is measured) */
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#define _00C0_TAU_TIMN_EDGE_BOTH_HIGH (0x00C0U) /* both edges (when high-level width is measured) */
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/* Operation mode of channel n (MDmn3 - MDmn0) */
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#define _0000_TAU_MODE_INTERVAL_TIMER (0x0000U) /* interval timer mode */
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#define _0004_TAU_MODE_CAPTURE (0x0004U) /* capture mode */
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#define _0006_TAU_MODE_EVENT_COUNT (0x0006U) /* event counter mode */
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#define _0008_TAU_MODE_ONE_COUNT (0x0008U) /* one count mode */
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#define _000C_TAU_MODE_HIGHLOW_MEASURE (0x000CU) /* high-/low-level width measurement mode */
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#define _0001_TAU_MODE_PWM_MASTER (0x0001U) /* PWM Function (Master Channel) mode */
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#define _0009_TAU_MODE_PWM_SLAVE (0x0009U) /* PWM Function (Slave Channel) mode */
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#define _0008_TAU_MODE_ONESHOT (0x0008U) /* one-shot pulse output mode */
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/* Setting of starting counting and interrupt (MDmn0) */
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#define _0000_TAU_START_INT_UNUSED (0x0000U) /* interrupt is not generated when counting is started */
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#define _0001_TAU_START_INT_USED (0x0001U) /* interrupt is generated when counting is started */
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/*
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Timer Status Register mn (TSRmn)
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*/
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/* Counter overflow status of channel n (OVF) */
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#define _0000_TAU_OVERFLOW_NOT_OCCURS (0x0000U) /* overflow does not occur */
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#define _0001_TAU_OVERFLOW_OCCURS (0x0001U) /* overflow occurs */
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/*
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Timer Channel Enable Status Register m (TEm)
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*/
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/* Indication of operation enable/stop status of channel 0 (TEm0) */
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#define _0000_TAU_CH0_OPERATION_STOP (0x0000U) /* operation is stopped */
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#define _0001_TAU_CH0_OPERATION_ENABLE (0x0001U) /* operation is enabled */
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/* Indication of operation enable/stop status of channel 1 (TEm1) */
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#define _0000_TAU_CH1_OPERATION_STOP (0x0000U) /* operation is stopped */
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#define _0002_TAU_CH1_OPERATION_ENABLE (0x0002U) /* operation is enabled */
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/* Indication of operation enable/stop status of channel 2 (TEm2) */
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#define _0000_TAU_CH2_OPERATION_STOP (0x0000U) /* operation is stopped */
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#define _0004_TAU_CH2_OPERATION_ENABLE (0x0004U) /* operation is enabled */
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/* Indication of operation enable/stop status of channel 3 (TEm3) */
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#define _0000_TAU_CH3_OPERATION_STOP (0x0000U) /* operation is stopped */
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#define _0008_TAU_CH3_OPERATION_ENABLE (0x0008U) /* operation is enabled */
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/* Indication of operation enable/stop status of channel 1 higher 8 bits (TEHm1) */
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#define _0000_TAU_CH1_H8_OPERATION_STOP (0x0000U) /* operation is stopped */
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#define _0200_TAU_CH1_H8_OPERATION_ENABLE (0x0200U) /* operation is enabled */
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/* Indication of operation enable/stop status of channel 3 higher 8 bits (TEHm3) */
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#define _0000_TAU_CH3_H8_OPERATION_STOP (0x0000U) /* operation is stopped */
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#define _0800_TAU_CH3_H8_OPERATION_ENABLE (0x0800U) /* operation is enabled */
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/*
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Timer Channel Start Register m (TSm)
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*/
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/* Operation enable (start) trigger of channel 0 (TSm0) */
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#define _0000_TAU_CH0_START_TRG_OFF (0x0000U) /* no trigger operation */
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#define _0001_TAU_CH0_START_TRG_ON (0x0001U) /* operation is enabled (start trigger is generated) */
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/* Operation enable (start) trigger of channel 1 (TSm1) */
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#define _0000_TAU_CH1_START_TRG_OFF (0x0000U) /* no trigger operation */
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#define _0002_TAU_CH1_START_TRG_ON (0x0002U) /* operation is enabled (start trigger is generated) */
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/* Operation enable (start) trigger of channel 2 (TSm2) */
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#define _0000_TAU_CH2_START_TRG_OFF (0x0000U) /* no trigger operation */
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#define _0004_TAU_CH2_START_TRG_ON (0x0004U) /* operation is enabled (start trigger is generated) */
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/* Operation enable (start) trigger of channel 3 (TSm3) */
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#define _0000_TAU_CH3_START_TRG_OFF (0x0000U) /* no trigger operation */
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#define _0008_TAU_CH3_START_TRG_ON (0x0008U) /* operation is enabled (start trigger is generated) */
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/* Operation enable (start) trigger of channel 1 higher 8 bits (TSHm1) */
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#define _0000_TAU_CH1_H8_START_TRG_OFF (0x0000U) /* no trigger operation */
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#define _0200_TAU_CH1_H8_START_TRG_ON (0x0200U) /* operation is enabled (start trigger is generated) */
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/* Operation enable (start) trigger of channel 3 higher 8 bits (TSHm3) */
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#define _0000_TAU_CH3_H8_START_TRG_OFF (0x0000U) /* no trigger operation */
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#define _0800_TAU_CH3_H8_START_TRG_ON (0x0800U) /* operation is enabled (start trigger is generated) */
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/*
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Timer Channel Stop Register m (TTm)
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*/
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/* Operation stop trigger of channel 0 (TTm0) */
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#define _0000_TAU_CH0_STOP_TRG_OFF (0x0000U) /* no trigger operation */
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#define _0001_TAU_CH0_STOP_TRG_ON (0x0001U) /* operation is stopped (stop trigger is generated) */
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/* Operation stop trigger of channel 1 (TTm1) */
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#define _0000_TAU_CH1_STOP_TRG_OFF (0x0000U) /* no trigger operation */
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#define _0002_TAU_CH1_STOP_TRG_ON (0x0002U) /* operation is stopped (stop trigger is generated) */
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/* Operation stop trigger of channel 2 (TTm2) */
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#define _0000_TAU_CH2_STOP_TRG_OFF (0x0000U) /* no trigger operation */
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#define _0004_TAU_CH2_STOP_TRG_ON (0x0004U) /* operation is stopped (stop trigger is generated) */
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/* Operation stop trigger of channel 3 (TTm3) */
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#define _0000_TAU_CH3_STOP_TRG_OFF (0x0000U) /* no trigger operation */
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#define _0008_TAU_CH3_STOP_TRG_ON (0x0008U) /* operation is stopped (stop trigger is generated) */
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/* Operation stop trigger of channel 1 higher 8 bits (TTHm1) */
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#define _0000_TAU_CH1_H8_STOP_TRG_OFF (0x0000U) /* no trigger operation */
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#define _0200_TAU_CH1_H8_STOP_TRG_ON (0x0200U) /* operation is stopped (stop trigger is generated) */
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/* Operation stop trigger of channel 3 higher 8 bits (TTHm3) */
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#define _0000_TAU_CH3_H8_STOP_TRG_OFF (0x0000U) /* no trigger operation */
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#define _0800_TAU_CH3_H8_STOP_TRG_ON (0x0800U) /* operation is stopped (stop trigger is generated) */
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/*
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Timer Input Select Register m (TIS0)
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*/
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/* Selection of timer input used with channel 1 (TIS01 - TIS00) */
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#define _00_TAU_CH1_INPUT_TI01 (0x00U) /* input signal of timer input pin (TI01) */
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#define _01_TAU_CH1_INPUT_FIL (0x01U) /* internal low speed oscillation colock (fIL) */
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#define _10_TAU_CH1_INPUT_TI01 (0x10U) /* input signal of timer input pin (TI01) */
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/*
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Timer Output Enable Register m (TOEm)
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*/
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/* Timer output enable/disable of channel 0 (TOEm0) */
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#define _0001_TAU_CH0_OUTPUT_ENABLE (0x0001U) /* the TOm0 operation enabled by count operation */
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#define _0000_TAU_CH0_OUTPUT_DISABLE (0x0000U) /* the TOm0 operation stopped by count operation */
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/* Timer output enable/disable of channel 1 (TOEm1) */
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#define _0002_TAU_CH1_OUTPUT_ENABLE (0x0002U) /* the TOm1 operation enabled by count operation */
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#define _0000_TAU_CH1_OUTPUT_DISABLE (0x0000U) /* the TOm1 operation stopped by count operation */
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/* Timer output enable/disable of channel 2 (TOEm2) */
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#define _0004_TAU_CH2_OUTPUT_ENABLE (0x0004U) /* the TOm2 operation enabled by count operation */
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#define _0000_TAU_CH2_OUTPUT_DISABLE (0x0000U) /* the TOm2 operation stopped by count operation */
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/* Timer output enable/disable of channel 3 (TOEm3) */
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#define _0008_TAU_CH3_OUTPUT_ENABLE (0x0008U) /* the TOm3 operation enabled by count operation */
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#define _0000_TAU_CH3_OUTPUT_DISABLE (0x0000U) /* the TOm3 operation stopped by count operation */
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/*
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Timer Output Register m (TOm)
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*/
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/* Timer output of channel 0 (TOm0) */
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#define _0000_TAU_CH0_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */
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#define _0001_TAU_CH0_OUTPUT_VALUE_1 (0x0001U) /* timer output value is "1" */
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/* Timer output of channel 1 (TOm1) */
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#define _0000_TAU_CH1_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */
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#define _0002_TAU_CH1_OUTPUT_VALUE_1 (0x0002U) /* timer output value is "1" */
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/* Timer output of channel 2 (TOm2) */
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#define _0000_TAU_CH2_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */
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#define _0004_TAU_CH2_OUTPUT_VALUE_1 (0x0004U) /* timer output value is "1" */
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/* Timer output of channel 3 (TOm3) */
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#define _0000_TAU_CH3_OUTPUT_VALUE_0 (0x0000U) /* timer output value is "0" */
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#define _0008_TAU_CH3_OUTPUT_VALUE_1 (0x0008U) /* timer output value is "1" */
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/*
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Timer Output Level Register 0 (TOLm)
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*/
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/* Control of timer output level of channel 1 (TOLm1) */
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#define _0000_TAU_CH1_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */
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#define _0002_TAU_CH1_OUTPUT_LEVEL_L (0x0002U) /* inverted output (active-low) */
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/* Control of timer output level of channel 2 (TOLm2) */
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#define _0000_TAU_CH2_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */
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#define _0004_TAU_CH2_OUTPUT_LEVEL_L (0x0004U) /* inverted output (active-low) */
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/* Control of timer output level of channel 3 (TOLm3) */
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#define _0000_TAU_CH3_OUTPUT_LEVEL_H (0x0000U) /* positive logic output (active-high) */
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#define _0008_TAU_CH3_OUTPUT_LEVEL_L (0x0008U) /* inverted output (active-low) */
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/*
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Timer Output Mode Register m (TOMm)
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*/
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/* Control of timer output mode of channel 1 (TOMm1) */
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#define _0000_TAU_CH1_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */
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#define _0002_TAU_CH1_OUTPUT_COMBIN (0x0002U) /* combination operation mode */
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/* Control of timer output mode of channel 2 (TOMm2) */
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#define _0000_TAU_CH2_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */
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#define _0004_TAU_CH2_OUTPUT_COMBIN (0x0004U) /* combination operation mode */
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/* Control of timer output mode of channel 3 (TOMm3) */
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#define _0000_TAU_CH3_OUTPUT_TOGGLE (0x0000U) /* toggle operation mode */
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#define _0008_TAU_CH3_OUTPUT_COMBIN (0x0008U) /* combination operation mode */
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/*
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Input Switch Control Register (ISC)
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*/
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/* Switching channel 7 input of timer array unit (ISC1) */
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#define _00_TAU_CH7_NO_INPUT (0x00U) /* timer input is not used */
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#define _02_TAU_CH7_RXD3_INPUT (0x02U) /* input signal of RxD3 pin is used as timer input */
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/*
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Noise Filter Enable Register 1 (NFEN1)
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*/
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/* Enable/disable using noise filter of TI03 pin input signal (TNFEN03) */
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#define _00_TAU_CH3_NOISE_OFF (0x00U) /* noise filter OFF */
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#define _08_TAU_CH3_NOISE_ON (0x08U) /* noise filter ON */
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/* Enable/disable using noise filter of TI02 pin input signal (TNFEN02) */
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#define _00_TAU_CH2_NOISE_OFF (0x00U) /* noise filter OFF */
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#define _04_TAU_CH2_NOISE_ON (0x04U) /* noise filter ON */
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/* Enable/disable using noise filter of TI01 pin input signal (TNFEN01) */
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#define _00_TAU_CH1_NOISE_OFF (0x00U) /* noise filter OFF */
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#define _02_TAU_CH1_NOISE_ON (0x02U) /* noise filter ON */
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/* Enable/disable using noise filter of TI00 pin input signal (TNFEN00) */
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#define _00_TAU_CH0_NOISE_OFF (0x00U) /* noise filter OFF */
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#define _01_TAU_CH0_NOISE_ON (0x01U) /* noise filter ON */
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/***********************************************************************************************************************
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Macro definitions
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***********************************************************************************************************************/
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/* 16-bit timer data register 00 (TDR00) */
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#define _5DBF_TAU_TDR00_VALUE (0x5DBFU)
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/* Clock divisor for TAU0 channel 0 */
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#define _0001_TAU0_CHANNEL0_DIVISOR (0x0001U)
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/***********************************************************************************************************************
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Typedef definitions
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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Global functions
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***********************************************************************************************************************/
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void R_TAU0_Create(void);
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void R_TAU0_Channel0_Start(void);
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void R_TAU0_Channel0_Stop(void);
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/* Start user code for function. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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#endif
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