416 lines
16 KiB
C
416 lines
16 KiB
C
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/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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*
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* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* File Name : r_rl78_can_sfr.h
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* Version : 1.0
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* Description : This is include file for CAN I/O registers.
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******************************************************************************/
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/*****************************************************************************
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* History : DD.MM.YYYY Version Description
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* : 29.03.2013 1.00 First Release
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******************************************************************************/
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#include "r_cg_macrodriver.h"
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#ifndef R_RL78_CAN_SFR_H
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#define R_RL78_CAN_SFR_H
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#define BIT_ON(x) (uint16_t)(1 << (x))
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#define BITS_2_ON(x) (uint16_t)(3 << (x))
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/*
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* Address
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*/
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/* ---- Channel ---- */
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typedef struct {
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volatile uint16_t CnCFGL;
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volatile uint16_t CnCFGH;
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volatile uint16_t CnCTRL;
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volatile uint16_t CnCTRH;
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volatile uint16_t CnSTSL;
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volatile uint16_t CnSTSH;
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volatile uint16_t CnERFLL;
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volatile uint16_t CnERFLH;
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} can_ch_top_sfr_t;
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typedef struct {
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volatile uint16_t IDL;
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volatile uint16_t IDH;
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volatile uint16_t TS;
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volatile uint16_t PTR;
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volatile uint16_t DF0;
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volatile uint16_t DF1;
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volatile uint16_t DF2;
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volatile uint16_t DF3;
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} can_frame_sfr_t;
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typedef struct {
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volatile uint16_t IDL;
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volatile uint16_t IDH;
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volatile uint16_t ML;
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volatile uint16_t MH;
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volatile uint16_t PL;
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volatile uint16_t PH;
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} can_rxrule_sfr_t;
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/* ---- Tx buffers ---- */
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#define TMCp(txbuf) (*((volatile uint8_t *)((uint16_t)&TMC0 + txbuf))) //__near
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#define CAN_ADDR_TMSTSp(txbuf) (volatile uint8_t *)((uint16_t)&TMSTS0 + txbuf) // __near
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/* ---- RAM ---- */
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#define CAN_ADDR_RMIDLp(buf) (volatile can_frame_sfr_t *)((uint16_t)&RMIDL0 + (0x10 * (buf))) //__near
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#define CAN_ADDR_TMIDLp(txbuf) (volatile can_frame_sfr_t *)((uint16_t)&TMIDL0 + (0x10 * (txbuf))) //__near
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#define CAN_ADDR_GAFLIDL0 0x03a0 // (volatile can_rxrule_sfr_t *)((uint16_t)&GAFLIDL0) //near
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/* ==== CAN SFR register bit field position ==== */
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/* ---- C0CFGL ---- */
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#define CAN_BRP_BIT_POS 0U
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#define CAN_CFG_BAUDRATEL(brp) ((brp) << CAN_BRP_BIT_POS)
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/* ---- C0CFGH ---- */
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#define CAN_SJW_BIT_POS 8U
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#define CAN_TSEG2_BIT_POS 4U
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#define CAN_TSEG1_BIT_POS 0U
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#define CAN_CFG_BAUDRATEH(tseg1, tseg2, sjw) \
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( ((tseg1) << CAN_TSEG1_BIT_POS) \
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+ ((tseg2) << CAN_TSEG2_BIT_POS) \
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+ ((sjw) << CAN_SJW_BIT_POS) )
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/* ---- C0CTRL ---- */
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#define CAN_ALIE_BIT_POS 15U
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#define CAN_BLIE_BIT_POS 14U
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#define CAN_OLIE_BIT_POS 13U
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#define CAN_BORIE_BIT_POS 12U
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#define CAN_BOEIE_BIT_POS 11U
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#define CAN_EPIE_BIT_POS 10U
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#define CAN_EWIE_BIT_POS 9U
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#define CAN_BEIE_BIT_POS 8U
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#define CAN_CSLPR_BIT_POS 2U
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#define CAN_CHMDC_BIT_POS 0U
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#define CAN_CFG_FUNCL(ie_bus, ie_ew, ie_ep, ie_boe, \
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ie_bor, ie_ol, ie_bl, ie_al) \
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( ((ie_bus) << CAN_BEIE_BIT_POS) \
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+ ((ie_ew) << CAN_EWIE_BIT_POS) \
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+ ((ie_ep) << CAN_EPIE_BIT_POS) \
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+ ((ie_boe) << CAN_BOEIE_BIT_POS) \
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+ ((ie_bor) << CAN_BORIE_BIT_POS) \
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+ ((ie_ol) << CAN_OLIE_BIT_POS) \
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+ ((ie_bl) << CAN_BLIE_BIT_POS) \
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+ ((ie_al) << CAN_ALIE_BIT_POS) )
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#define CAN_STP_BIT_ON BIT_ON(CAN_CSLPR_BIT_POS)
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#define CAN_MODE_BITS_ON BITS_2_ON(CAN_CHMDC_BIT_POS)
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/* ---- C0CTRH ---- */
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#define CAN_ERRD_BIT_POS 7U
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#define CAN_BOM_BIT_POS 5U
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#define CAN_TAIE_BIT_POS 0U
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#define CAN_CFG_FUNCH(ie_ta, boff_mode, er_disp) \
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( ((ie_ta) << CAN_TAIE_BIT_POS) \
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+ ((boff_mode) << CAN_BOM_BIT_POS) \
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+ ((er_disp) << CAN_ERRD_BIT_POS) )
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/* ---- C0STSL ---- */
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#define CAN_CSLPSTS_BIT_POS 2U
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#define CAN_CRSTSTS_BIT_POS 0U
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#define CAN_STP_STS_BIT_ON BIT_ON(CAN_CSLPSTS_BIT_POS)
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#define CAN_RST_STS_BIT_ON BIT_ON(CAN_CRSTSTS_BIT_POS)
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/* ---- GCFGL ---- */
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#define CAN_TSSS_BIT_POS 12U
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#define CAN_TSP_BIT_POS 8U
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#define CAN_DCS_BIT_POS 4U
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#define CAN_MME_BIT_POS 3U
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#define CAN_DRE_BIT_POS 2U
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#define CAN_DCE_BIT_POS 1U
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#define CAN_TPRI_BIT_POS 0U
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#define CAN_CFG_GCFGL(priority, dlc_check, dlc_replace, \
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mirror, can_clock, ts_clock, \
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ts_pr) \
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( ((priority) << CAN_TPRI_BIT_POS) \
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+ ((dlc_check) << CAN_DCE_BIT_POS) \
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+ ((dlc_replace) << CAN_DRE_BIT_POS) \
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+ ((mirror) << CAN_MME_BIT_POS) \
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+ ((can_clock) << CAN_DCS_BIT_POS) \
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+ ((ts_pr) << CAN_TSP_BIT_POS) \
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+ ((ts_clock) << CAN_TSSS_BIT_POS) )
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/* ---- GCFGH ---- */
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#define CAN_ITRCP_BIT_POS 0U
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#define CAN_CFG_GCFGH(it_pr) \
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( (it_pr) << CAN_ITRCP_BIT_POS )
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/* ---- GCTRL ---- */
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#define CAN_THLEIE_BIT_POS 10U
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#define CAN_MEIE_BIT_POS 9U
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#define CAN_DEIE_BIT_POS 8U
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#define CAN_GSLPR_BIT_POS 2U
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#define CAN_GMDC_BIT_POS 0U
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#define CAN_CFG_GCTRL(overflow_ie, msg_lost_ie, dlc_error_ie) \
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( ((overflow_ie) << CAN_THLEIE_BIT_POS) \
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+ ((msg_lost_ie) << CAN_MEIE_BIT_POS) \
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+ ((dlc_error_ie) << CAN_DEIE_BIT_POS))
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#define CAN_GLB_STP_BIT_ON BIT_ON(CAN_GSLPR_BIT_POS)
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#define CAN_GLB_MODE_BITS_ON BITS_2_ON(CAN_GMDC_BIT_POS)
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/* ---- GSTS ---- */
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#define CAN_GRAMINIT_BIT_POS 3U
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#define CAN_GSLPSTS_BIT_POS 2U
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#define CAN_GRSTSTS_BIT_POS 0U
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#define CAN_RAM_INIT_BIT_ON BIT_ON(CAN_GRAMINIT_BIT_POS)
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#define CAN_GLB_STP_STS_BIT_ON BIT_ON(CAN_GSLPSTS_BIT_POS)
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#define CAN_GLB_RST_STS_BIT_ON BIT_ON(CAN_GRSTSTS_BIT_POS)
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/* ---- GRWCR ---- */
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#define CAN_RPAGE_BIT_POS 0U
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#define CAN_RAM_WINDOW_BIT_ON BIT_ON(CAN_RPAGE_BIT_POS)
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/* ---- RFCCm ---- */
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#define CAN_RFIGCV_BIT_POS 13U
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#define CAN_RFIM_BIT_POS 12U
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#define CAN_RFDC_BIT_POS 8U
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#define CAN_RFIE_BIT_POS 1U
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#define CAN_RFE_BIT_POS 0U
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#define CAN_CFG_RXFIFO(dc, i_enable, i_factor, i_timing) \
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( ((i_timing) << CAN_RFIGCV_BIT_POS) \
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+ ((i_factor) << CAN_RFIM_BIT_POS) \
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+ ((i_enable) << CAN_RFIE_BIT_POS) \
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+ ((dc) << CAN_RFDC_BIT_POS) )
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#define CAN_RFIFO_EN_BIT_ON BIT_ON(CAN_RFE_BIT_POS)
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/* ---- RFSTSm ---- */
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#define CAN_RFIF_BIT_POS 3U
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#define CAN_RFMLT_BIT_POS 2U
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#define CAN_RFEMP_BIT_POS 0U
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#define CAN_RFIFO_MSGLST_BIT_ON BIT_ON(CAN_RFMLT_BIT_POS)
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#define CAN_RFIFO_EMPTY_BIT_ON BIT_ON(CAN_RFEMP_BIT_POS)
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#define CAN_CLR_WITHOUT_RX_INT BIT_ON(CAN_RFIF_BIT_POS)
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/* ---- CFCCLk ---- */
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#define CAN_CFIGCV_BIT_POS 13U
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#define CAN_CFIM_BIT_POS 12U
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#define CAN_CFDC_BIT_POS 8U
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#define CAN_CFTXIE_BIT_POS 2U
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#define CAN_CFRXIE_BIT_POS 1U
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#define CAN_CFE_BIT_POS 0U
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#define CAN_CFG_TRFIFO_TXL(dc, i_enable, i_factor) \
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( ((i_factor) << CAN_CFIM_BIT_POS) \
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+ ((dc) << CAN_CFDC_BIT_POS) \
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+ ((i_enable) << CAN_CFTXIE_BIT_POS) )
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#define CAN_CFG_TRFIFO_RXL(dc, i_enable, i_factor, i_timing) \
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( ((i_timing) << CAN_CFIGCV_BIT_POS) \
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+ ((i_factor) << CAN_CFIM_BIT_POS) \
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+ ((dc) << CAN_CFDC_BIT_POS) \
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+ ((i_enable) << CAN_CFRXIE_BIT_POS) )
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#define CAN_TRFIFO_EN_BIT_ON BIT_ON(CAN_CFE_BIT_POS)
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/* ---- CFCCHk ---- */
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#define CAN_CFITT_BIT_POS 8U
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#define CAN_CFTML_BIT_POS 4U
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#define CAN_CFITR_BIT_POS 3U
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#define CAN_CFITSS_BIT_POS 2U
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#define CAN_CFM_BIT_POS 0U
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#define CAN_CFG_TRFIFO_TXH(txbuf_idx, timer, time) \
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( ((time) << CAN_CFITT_BIT_POS) \
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+ ((txbuf_idx) << CAN_CFTML_BIT_POS) \
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+ ((timer) << CAN_CFITSS_BIT_POS) \
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+ ((CAN_TRFIFO_TX_MODE) << CAN_CFM_BIT_POS) )
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#define CAN_CFG_TRFIFO_RXH ((CAN_TRFIFO_RX_MODE) << CAN_CFM_BIT_POS)
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/* ---- CFSTSk ---- */
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#define CAN_CFTXIF_BIT_POS 4U
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#define CAN_CFRXIF_BIT_POS 3U
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#define CAN_CFMLT_BIT_POS 2U
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#define CAN_CFFLL_BIT_POS 1U
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#define CAN_CFEMP_BIT_POS 0U
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#define CAN_TRFIFO_MSGLST_BIT_ON BIT_ON(CAN_CFMLT_BIT_POS)
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#define CAN_TRFIFO_FULL_BIT_ON BIT_ON(CAN_CFFLL_BIT_POS)
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#define CAN_TRFIFO_EMPTY_BIT_ON BIT_ON(CAN_CFEMP_BIT_POS)
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#define CAN_CLR_WITHOUT_TX_RX_INT \
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(BIT_ON(CAN_CFTXIF_BIT_POS) | BIT_ON(CAN_CFRXIF_BIT_POS))
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/* ---- TMCp ---- */
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#define CAN_TMTAR_BIT_ON 1U
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#define CAN_TMTR_BIT_ON 0U
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#define CAN_TXBUF_ABT_BIT_ON BIT_ON(CAN_TMTAR_BIT_ON)
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#define CAN_TXBUF_TRM_BIT_ON BIT_ON(CAN_TMTR_BIT_ON)
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/* ---- TMSTSp ---- */
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#define CAN_TMTRF_BIT_POS 1U
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#define CAN_TXBUF_RSLT_BITS_POS CAN_TMTRF_BIT_POS
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#define CAN_TXBUF_RSLT_BITS_ON BITS_2_ON(CAN_TXBUF_RSLT_BITS_POS)
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/* ==== CAN SFR register value ==== */
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/* ---- Resynchronization jump width ---- */
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#define CAN_SJW_1TQ 0U
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#define CAN_SJW_2TQ 1U
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#define CAN_SJW_3TQ 2U
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#define CAN_SJW_4TQ 3U
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/* ---- Time segment 2 ---- */
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#define CAN_TSEG2_2TQ 1U
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#define CAN_TSEG2_3TQ 2U
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#define CAN_TSEG2_4TQ 3U
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#define CAN_TSEG2_5TQ 4U
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#define CAN_TSEG2_6TQ 5U
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#define CAN_TSEG2_7TQ 6U
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#define CAN_TSEG2_8TQ 7U
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/* ---- Time segment 1 ---- */
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#define CAN_TSEG1_4TQ 3U
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#define CAN_TSEG1_5TQ 4U
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#define CAN_TSEG1_6TQ 5U
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#define CAN_TSEG1_7TQ 6U
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#define CAN_TSEG1_8TQ 7U
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#define CAN_TSEG1_9TQ 8U
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#define CAN_TSEG1_10TQ 9U
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#define CAN_TSEG1_11TQ 10U
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#define CAN_TSEG1_12TQ 11U
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#define CAN_TSEG1_13TQ 12U
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#define CAN_TSEG1_14TQ 13U
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#define CAN_TSEG1_15TQ 14U
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#define CAN_TSEG1_16TQ 15U
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/* ---- Error display mode ---- */
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#define CAN_ERRDISP_FIRST_ERR_ONLY 0U
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#define CAN_ERRDISP_ALL_ERR 1U
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/* ---- Bus off recovery mode ---- */
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#define CAN_BOFF_RECOVERY_ISO11898 0U
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#define CAN_BOFF_RECOVERY_START_ENTRY 1U
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#define CAN_BOFF_RECOVERY_END_ENTRY 2U
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#define CAN_BOFF_RECOVERY_MANUAL_ENTRY 3U
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/* ---- Channel mode ---- */
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#define CAN_MODE_CH_COMM_MODE 0U
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#define CAN_MODE_CH_RESET_MODE 1U
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#define CAN_MODE_CH_HALT_MODE 2U
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||
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/* ---- Time stamp clock source ---- */
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#define CAN_TS_PCLOCK_2 0U
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#define CAN_TS_CAN0_BT_CLOCK 1U
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/* ---- Time stamp clock source division ---- */
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#define CAN_TS_NO_DIV 0U
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#define CAN_TS_2_DIV 1U
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#define CAN_TS_4_DIV 2U
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#define CAN_TS_8_DIV 3U
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#define CAN_TS_16_DIV 4U
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#define CAN_TS_32_DIV 5U
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#define CAN_TS_64_DIV 6U
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#define CAN_TS_128_DIV 7U
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#define CAN_TS_256_DIV 8U
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#define CAN_TS_512_DIV 9U
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||
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#define CAN_TS_1024_DIV 10U
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||
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#define CAN_TS_2048_DIV 11U
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||
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#define CAN_TS_4096_DIV 12U
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||
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#define CAN_TS_8192_DIV 13U
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||
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#define CAN_TS_16384_DIV 14U
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||
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#define CAN_TS_32768_DIV 15U
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||
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|
|
||
|
|
/* ---- CAN clock source ---- */
|
||
|
|
#define CAN_SOURCE_PCLOCK_2 0U
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||
|
|
#define CAN_SOURCE_MAIN_CLOCK 1U
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||
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|
|
||
|
|
/* ---- transmission priority ---- */
|
||
|
|
#define CAN_TX_ID_FIRST 0U
|
||
|
|
#define CAN_TX_BUF_IDX_FIRST 1U
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||
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|
|
||
|
|
/* ---- global mode ---- */
|
||
|
|
#define CAN_GLB_OPERATION_MODE 0U
|
||
|
|
#define CAN_GLB_RESET_MODE 1U
|
||
|
|
#define CAN_GLB_TEST_MODE 2U
|
||
|
|
|
||
|
|
/* ---- FIFO (Rx, Common) interrupt generation timing ---- */
|
||
|
|
#define CAN_FIFO_THRESHOLD_1_8 0U
|
||
|
|
#define CAN_FIFO_THRESHOLD_2_8 1U
|
||
|
|
#define CAN_FIFO_THRESHOLD_3_8 2U
|
||
|
|
#define CAN_FIFO_THRESHOLD_4_8 3U
|
||
|
|
#define CAN_FIFO_THRESHOLD_5_8 4U
|
||
|
|
#define CAN_FIFO_THRESHOLD_6_8 5U
|
||
|
|
#define CAN_FIFO_THRESHOLD_7_8 6U
|
||
|
|
#define CAN_FIFO_THRESHOLD_FULL 7U
|
||
|
|
|
||
|
|
/* ---- FIFO (Rx, Common) interrupt factor ---- */
|
||
|
|
#define CAN_FIFO_INT_THRESHOLD 0U
|
||
|
|
#define CAN_FIFO_INT_EACH_MSG 1U
|
||
|
|
|
||
|
|
/* ---- FIFO (Rx, Common) depth define ---- */
|
||
|
|
#define CAN_FIFO_DEPTH_0 0U
|
||
|
|
#define CAN_FIFO_DEPTH_4 1U
|
||
|
|
#define CAN_FIFO_DEPTH_8 2U
|
||
|
|
#define CAN_FIFO_DEPTH_16 3U
|
||
|
|
|
||
|
|
/* ---- Tx buffer ---- */
|
||
|
|
#define CAN_TX_BUFFER_0 0U
|
||
|
|
#define CAN_TX_BUFFER_1 1U
|
||
|
|
#define CAN_TX_BUFFER_2 2U
|
||
|
|
#define CAN_TX_BUFFER_3 3U
|
||
|
|
|
||
|
|
/* ---- Common FIFO interval time counter source ---- */
|
||
|
|
#define CAN_IT_PCLOCK_2 0U
|
||
|
|
#define CAN_IT_CAN_BIT_CLK 1U
|
||
|
|
#define CAN_IT_PCLOCK_2_10_DIV 2U
|
||
|
|
|
||
|
|
/* ---- Common FIFO mode ---- */
|
||
|
|
#define CAN_TRFIFO_RX_MODE 0U
|
||
|
|
#define CAN_TRFIFO_TX_MODE 1U
|
||
|
|
|
||
|
|
#endif /* R_RL78_CAN_SFR_H */
|