139 lines
6.6 KiB
Plaintext
139 lines
6.6 KiB
Plaintext
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;==============================================================================
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;
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; Project = Sample program for flash self-programming library
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; Module = r_fsl_sample_c.dr
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; Version = V1.01(Target FSL Version for CA78K0R is V2.20)
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; Target CPU = RL78/G13 ( R5F100LEA / QB-R5F100LE-TB )
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; Environment = CS+ for CA[CA78K0R],CX (V3.00)
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;
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; Date = 12, 28, 2016
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;
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;==============================================================================
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; COPYRIGHT
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;==============================================================================
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; DISCLAIMER
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; This software is supplied by Renesas Electronics Corporation and is only
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; intended for use with Renesas products. No other uses are authorized. This
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; software is owned by Renesas Electronics Corporation and is protected under
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; all applicable laws, including copyright laws.
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; THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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; THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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; LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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; AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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; TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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; ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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; FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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; ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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; BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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; Renesas reserves the right, without notice, to make changes to this software
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; and to discontinue the availability of this software. By using this software,
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; you agree to the additional terms and conditions found by accessing the
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; following link:
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; http://www.renesas.com/disclaimer
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;
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; Copyright (C) 2010-2016 Renesas Electronics Corporation. All rights reserved.
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;==============================================================================
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;***********************************************************
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; Redefined ROM area
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;***********************************************************
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; ----------------------------------------------------------
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; Define new memory entry for boot cluster 0
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; ----------------------------------------------------------
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MEMORY BCL0 : ( 000000H, 001000H )
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; ----------------------------------------------------------
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; Define new memory entry for boot cluster 1
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; ----------------------------------------------------------
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MEMORY BCL1 : ( 001000H, 001000H )
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; ----------------------------------------------------------
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; Redefined default code segment ROM
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; ----------------------------------------------------------
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MEMORY ROM : ( 002000H, 000800H )
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; ----------------------------------------------------------
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; Define new memory entry for fsl-code area
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; ----------------------------------------------------------
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MEMORY ROM_FSL : ( 002800H, 000400H )
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; ----------------------------------------------------------
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; Define new memory entry for write-data area
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; ----------------------------------------------------------
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MEMORY ROM_DATA : ( 002C00H, 000800H )
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; ----------------------------------------------------------
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; Define new memory entry for write-data area
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; ----------------------------------------------------------
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;MEMORY OCDROM : ( 00FE00H, 000200H )
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;***********************************************************
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; Redefined RAM area
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;***********************************************************
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; ----------------------------------------------------------
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; Redefined default data segment RAM
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; ----------------------------------------------------------
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MEMORY RAM : ( 0FFB00H, 000320H )
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; ----------------------------------------------------------
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; Define new memory entry for saddr area
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; ----------------------------------------------------------
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MEMORY RAM_SADDR : ( 0FFE20H, 0000E0H )
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;***********************************************************
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; Library(fsl.lib) segment
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;***********************************************************
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; ----------------------------------------------------------
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; Merge FSL_FCD segment
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; ----------------------------------------------------------
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MERGE FSL_FCD := ROM_FSL
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; ----------------------------------------------------------
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; Merge FSL_FECD segment
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; ----------------------------------------------------------
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;MERGE FSL_FECD := ROM_FSL
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; ----------------------------------------------------------
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; Merge FSL_RCD segment
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; ----------------------------------------------------------
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MERGE FSL_RCD := ROM_FSL
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; ----------------------------------------------------------
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; Merge FSL_BCD segment
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; ----------------------------------------------------------
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MERGE FSL_BCD := ROM_FSL
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; ----------------------------------------------------------
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; Merge FSL_BECD segment
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; ----------------------------------------------------------
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MERGE FSL_BECD := ROM_FSL
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;***********************************************************
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; sample_c.c segment
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;***********************************************************
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; ----------------------------------------------------------
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; Merge SAM_CODE segment
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; ----------------------------------------------------------
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MERGE SAM_CODE := ROM
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; ----------------------------------------------------------
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; Merge SAM_CNST segment
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; ----------------------------------------------------------
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MERGE SAM_CNST := ROM_DATA
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; ----------------------------------------------------------
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; Merge SAM_DATA segment
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; ----------------------------------------------------------
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MERGE SAM_DATA := RAM
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;***********************************************************
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; run-time library segment ( 0000H - FFFFH )
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;***********************************************************
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; ----------------------------------------------------------
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; Merge @@LCODE,@@LCODEL(run-time library) segment
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; ----------------------------------------------------------
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MERGE @@LCODE := BCL0
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MERGE @@LCODEL := BCL0
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