2024-05-26 08:08:32 +08:00
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/***********************************************************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
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* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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* applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
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* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
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* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
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* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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*
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* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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* File Name : r_cg_intc.h
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* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021]
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* Device(s) : R5F10BGG
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* Tool-Chain : CCRL
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* Description : This file implements device driver for INTC module.
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2024-05-26 11:13:55 +08:00
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* Creation Date: 2022/7/8
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2024-05-26 08:08:32 +08:00
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***********************************************************************************************************************/
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#ifndef INTC_H
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#define INTC_H
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/***********************************************************************************************************************
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Macro definitions (Register bit)
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***********************************************************************************************************************/
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/*
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External Interrupt Rising Edge Enable Register 0 (EGP0)
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*/
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/* INTPn pin valid edge selection (EGPn) */
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#define _01_INTP0_EDGE_RISING_SEL (0x01U) /* rising edge selected for INTP0 pin */
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#define _00_INTP0_EDGE_RISING_UNSEL (0x00U) /* rising edge not selected for INTP0 pin */
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#define _02_INTP1_EDGE_RISING_SEL (0x02U) /* rising edge selected for INTP1 pin */
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#define _00_INTP1_EDGE_RISING_UNSEL (0x00U) /* rising edge not selected for INTP1 pin*/
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#define _04_INTP2_EDGE_RISING_SEL (0x04U) /* rising edge selected for INTP2 pin */
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#define _00_INTP2_EDGE_RISING_UNSEL (0x00U) /* rising edge not selected for INTP2 pin */
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#define _08_INTP3_EDGE_RISING_SEL (0x08U) /* rising edge selected for INTP3 pin */
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#define _00_INTP3_EDGE_RISING_UNSEL (0x00U) /* rising edge not selected for INTP3 pin */
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#define _10_INTP4_EDGE_RISING_SEL (0x10U) /* rising edge selected for INTP4 pin */
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#define _00_INTP4_EDGE_RISING_UNSEL (0x00U) /* rising edge not selected for INTP4 pin */
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#define _20_INTP5_EDGE_RISING_SEL (0x20U) /* rising edge selected for INTP5 pin */
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#define _00_INTP5_EDGE_RISING_UNSEL (0x00U) /* rising edge not selected for INTP5 pin */
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#define _40_INTP6_EDGE_RISING_SEL (0x40U) /* rising edge selected for INTP6 pin */
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#define _00_INTP6_EDGE_RISING_UNSEL (0x00U) /* rising edge not selected for INTP6 pin */
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#define _80_INTP7_EDGE_RISING_SEL (0x80U) /* rising edge selected for INTP7 pin */
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#define _00_INTP7_EDGE_RISING_UNSEL (0x00U) /* rising edge not selected for INTP7 pin */
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/*
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External Interrupt Falling Edge Enable Register 0 (EGN0)
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*/
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/* INTPn pin valid edge selection (EGNn) */
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#define _01_INTP0_EDGE_FALLING_SEL (0x01U) /* falling edge selected for INTP0 pin */
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#define _00_INTP0_EDGE_FALLING_UNSEL (0x00U) /* falling edge not selected for INTP0 pin */
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#define _02_INTP1_EDGE_FALLING_SEL (0x02U) /* falling edge selected for INTP1 pin */
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#define _00_INTP1_EDGE_FALLING_UNSEL (0x00U) /* falling edge not selected for INTP1 pin */
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#define _04_INTP2_EDGE_FALLING_SEL (0x04U) /* falling edge selected for INTP2 pin */
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#define _00_INTP2_EDGE_FALLING_UNSEL (0x00U) /* falling edge not selected for INTP2 pin */
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#define _08_INTP3_EDGE_FALLING_SEL (0x08U) /* falling edge selected for INTP3 pin */
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#define _00_INTP3_EDGE_FALLING_UNSEL (0x00U) /* falling edge not selected for INTP3 pin */
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#define _10_INTP4_EDGE_FALLING_SEL (0x10U) /* falling edge selected for INTP4 pin */
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#define _00_INTP4_EDGE_FALLING_UNSEL (0x00U) /* falling edge not selected for INTP4 pin */
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#define _20_INTP5_EDGE_FALLING_SEL (0x20U) /* falling edge selected for INTP5 pin */
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#define _00_INTP5_EDGE_FALLING_UNSEL (0x00U) /* falling edge not selected for INTP5 pin */
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#define _40_INTP6_EDGE_FALLING_SEL (0x40U) /* falling edge selected for INTP6 pin */
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#define _00_INTP6_EDGE_FALLING_UNSEL (0x00U) /* falling edge not selected for INTP6 pin */
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#define _80_INTP7_EDGE_FALLING_SEL (0x80U) /* falling edge selected for INTP7 pin */
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#define _00_INTP7_EDGE_FALLING_UNSEL (0x00U) /* falling edge not selected for INTP7 pin */
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/*
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External Interrupt Rising Edge Enable Register 1 (EGP1)
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*/
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/* INTPn pin valid edge selection (EGPn) */
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#define _01_INTP8_EDGE_RISING_SEL (0x01U) /* rising edge selected for INTP8 pin */
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#define _00_INTP8_EDGE_RISING_UNSEL (0x00U) /* rising edge not selected for INTP8 pin */
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#define _02_INTP9_EDGE_RISING_SEL (0x02U) /* rising edge selected for INTP9 pin */
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#define _00_INTP9_EDGE_RISING_UNSEL (0x00U) /* rising edge not selected for INTP9 pin*/
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/*
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External Interrupt Falling Edge Enable Register 1 (EGN1)
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*/
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/* INTPn pin valid edge selection (EGNn) */
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#define _01_INTP8_EDGE_FALLING_SEL (0x01U) /* falling edge selected for INTP8 pin */
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#define _00_INTP8_EDGE_FALLING_UNSEL (0x00U) /* falling edge not selected for INTP8 pin */
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#define _02_INTP9_EDGE_FALLING_SEL (0x02U) /* falling edge selected for INTP9 pin */
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#define _00_INTP9_EDGE_FALLING_UNSEL (0x00U) /* falling edge not selected for INTP9 pin */
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/*
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Interrupt Mask Register (INTMSK)
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*/
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#define _F8_INTP_INTMSK_INIT_VALUE (0xF8U) /* set INTMSK initial value */
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/* Setting masking for INTP4 interrupt source to the interrupt control circuit INTMSK0 */
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#define _01_INTP4_CONTROL_DISABLE (0x01U) /* requests to the interrupt control circuit are disabled */
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#define _00_INTP4_CONTROL_ENABLE (0x00U) /* requests to the interrupt control circuit, ELC, and DTC are enabled */
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/* Setting masking for INTP5 interrupt source to the interrupt control circuit INTMSK1 */
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#define _02_INTP5_CONTROL_DISABLE (0x02U) /* requests to the interrupt control circuit are disabled, and requests */
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#define _00_INTP5_CONTROL_ENABLE (0x00U) /* requests to the interrupt control circuit, ELC, and DTC are enabled */
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/* Setting masking for INTP6 interrupt source to the interrupt control circuit INTMSK1 */
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#define _04_INTP6_CONTROL_DISABLE (0x04U) /* requests to the interrupt control circuit are disabled, and requests */
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#define _00_INTP6_CONTROL_ENABLE (0x00U) /* requests to the interrupt control circuit, ELC, and DTC are enabled */
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/*
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Key Return Mode Register (KRM)
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*/
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/* Key interrupt mode control (KRM0) */
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#define _00_KR0_SIGNAL_DETECT_OFF (0x00U) /* not detect KR0 signal */
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#define _01_KR0_SIGNAL_DETECT_ON (0x01U) /* detect KR0 signal */
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/* Key interrupt mode control (KRM1) */
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#define _00_KR1_SIGNAL_DETECT_OFF (0x00U) /* not detect KR1 signal */
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#define _02_KR1_SIGNAL_DETECT_ON (0x02U) /* detect KR1 signal */
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/* Key interrupt mode control (KRM2) */
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#define _00_KR2_SIGNAL_DETECT_OFF (0x00U) /* not detect KR2 signal */
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#define _04_KR2_SIGNAL_DETECT_ON (0x04U) /* detect KR2 signal */
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/* Key interrupt mode control (KRM3) */
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#define _00_KR3_SIGNAL_DETECT_OFF (0x00U) /* not detect KR3 signal */
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#define _08_KR3_SIGNAL_DETECT_ON (0x08U) /* detect KR3 signal */
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/***********************************************************************************************************************
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Macro definitions
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***********************************************************************************************************************/
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2024-05-26 11:13:55 +08:00
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#define _C2_INTFLG0_MASK_VALUE (0xC2U) /* set interrupt factor distinction flag */
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2024-05-26 08:08:32 +08:00
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/***********************************************************************************************************************
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Typedef definitions
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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Global functions
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***********************************************************************************************************************/
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void R_INTC_Create(void);
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2024-05-26 11:13:55 +08:00
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void R_INTC0_Start(void);
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void R_INTC0_Stop(void);
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void R_INTC1_Start(void);
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void R_INTC1_Stop(void);
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void R_INTC2_Start(void);
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void R_INTC2_Stop(void);
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void R_INTC4_Start(void);
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void R_INTC4_Stop(void);
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void R_INTC6_Start(void);
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void R_INTC6_Stop(void);
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void R_INTC7_Start(void);
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void R_INTC7_Stop(void);
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void R_INTC8_Start(void);
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void R_INTC8_Stop(void);
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2024-05-26 08:08:32 +08:00
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/* Start user code for function. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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#endif
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