/* * CPU.c * * Created on: Oct 4, 2016 * Author: Administrator */ #include "CPU.h" //bus时钟为32M，内部高速时钟为64M，程序运行为32M void CLK_CONFIG(void) { /*** !!! Here you can place your own code using property "User code before PE initialization" on the build options tab of the CPU compoennt. !!! ***/ /* ### MC9S12ZVL32_48 "Cpu" init code ... */ /* PE initialization code after reset */ /* IVBR: IVB_ADDR=0x7FFF,??=0 */ setReg16(IVBR, 0xFFFEU); /* ECLKCTL: NECLK=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ setReg8(ECLKCTL, 0x80U); /* System clock initialization */ /* CPMUPROT: ??=0,??=0,??=1,??=0,??=0,??=1,??=1,PROT=0 */ setReg8(CPMUPROT, 0x26U); /* Disable protection of clock configuration registers */ /* CPMUCLKS: PSTP=0 */ clrReg8Bits(CPMUCLKS, 0x40U); /* CPMUCLKS: PLLSEL=1 */ setReg8Bits(CPMUCLKS, 0x80U); /* Enable the PLL to allow write to divider registers */ /* CPMUPOSTDIV: ??=0,??=0,??=0,POSTDIV4=0,POSTDIV3=0,POSTDIV2=0,POSTDIV1=0,POSTDIV0=0 */ setReg8(CPMUPOSTDIV, 0x00U); /* Set the post divider register */ /* Whenever changing PLL reference clock (REFCLK) frequency to a higher value it is recommended to write CPMUSYNR = 0x00 in order to stay within specified maximum frequency of the MCU */ /* CPMUSYNR: VCOFRQ1=0,VCOFRQ0=0,SYNDIV5=0,SYNDIV4=0,SYNDIV3=0,SYNDIV2=0,SYNDIV1=0,SYNDIV0=0 */ setReg8(CPMUSYNR, 0x00U); /* Set the multiplier register */ /* CPMUPLL: ??=0,??=0,FM1=0,FM0=0,??=0,??=0,??=0,??=0 */ setReg8(CPMUPLL, 0x00U); /* Set the PLL frequency modulation */ /* CPMUSYNR: VCOFRQ1=0,VCOFRQ0=1,SYNDIV5=0,SYNDIV4=1,SYNDIV3=1,SYNDIV2=1,SYNDIV1=1,SYNDIV0=1 */ setReg8(CPMUSYNR, 0x5FU); /* Set the multiplier register */ while(CPMUIFLG_LOCK == 0U) { /* Wait until the PLL is within the desired tolerance of the target frequency */ } /* CPMUPROT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,PROT=0 */ setReg8(CPMUPROT, 0x00U); /* Enable protection of clock configuration registers */ /* CPMUCOP: RSBCK=0,WRTMASK=1 */ clrSetReg8Bits(CPMUCOP, 0x40U, 0x20U); /* CPMUHTCTL: ??=0,??=0,VSEL=0,??=0,HTE=0,HTDS=0,HTIE=0,HTIF=0 */ setReg8(CPMUHTCTL, 0x00U); /* CPMUVREGCTL: ??=0,??=0,??=0,??=0,??=0,??=0,EXTXON=0,INTXON=1 */ setReg8(CPMUVREGCTL, 0x81U); /*** End of PE initialization code after reset ***/ } void Peripheral_Init(void) { /* Int. priority initialization */ /* No. Address Pri XGATE Name Description */ setReg8(INT_CFADDR, 0x28U); setReg8(INT_CFDATA3, 0x04U); /* 0x2B 0x00FFFEAC 4 no ivVtim1ch0 used by PE */ setReg8(INT_CFADDR, 0x60U); setReg8(INT_CFDATA1, 0x04U); /* 0x61 0x00FFFF84 4 no ivVadc0conv_compl used by PE */ setReg8(INT_CFDATA2, 0x04U); /* 0x62 0x00FFFF88 4 no ivVadc0conv_seq_abrt used by PE */ setReg8(INT_CFDATA3, 0x04U); /* 0x63 0x00FFFF8C 4 no ivVadc0err used by PE */ /* Common initialization of the CPU registers */ /* DIENADL: DIENADL7=1,DIENADL6=1,DIENADL5=1,DIENADL4=1,DIENADL3=1,DIENADL2=1 */ setReg8Bits(DIENADL, 0xFCU); /* PIEADL: PIEADL7=0,PIEADL6=0,PIEADL5=0,PIEADL4=0,PIEADL3=0,PIEADL2=0 */ clrReg8Bits(PIEADL, 0xFCU); /* PERADL: PERADL7=0,PERADL6=0,PERADL5=0,PERADL4=0,PERADL3=0,PERADL2=0 */ clrReg8Bits(PERADL, 0xFCU); /* DDRADL: DDRADL7=0,DDRADL6=0,DDRADL5=0,DDRADL4=0,DDRADL3=0,DDRADL2=0 */ clrReg8Bits(DDRADL, 0xFCU); /* TIM1TSCR1: TEN=0,TSWAI=0,TSFRZ=0,TFFCA=0,PRNT=1,??=0,??=0,??=0 */ setReg8(TIM1TSCR1, 0x08U); /* TIM1OCPD: OCPD0=1 */ setReg8Bits(TIM1OCPD, 0x01U); /* TIM1TIOS: IOS0=1 */ setReg8Bits(TIM1TIOS, 0x01U); /* TIM1TCTL2: OM0=0,OL0=0 */ clrReg8Bits(TIM1TCTL2, 0x03U); /* TIM1TTOV: TOV0=0 */ clrReg8Bits(TIM1TTOV, 0x01U); /* TIM1TSCR2: TOI=0 */ clrReg8Bits(TIM1TSCR2, 0x80U); /* TIM1TFLG1: ??=1,??=1,??=1,??=1,??=1,??=1,C1F=1,C0F=1 */ setReg8(TIM1TFLG1, 0xFFU); /* TIM1TIE: C0I=1 */ setReg8Bits(TIM1TIE, 0x01U); /* TIM1PTPSR: PTPS7=0,PTPS6=0,PTPS5=0,PTPS4=0,PTPS3=0,PTPS2=0,PTPS1=0,PTPS0=0 */ setReg8(TIM1PTPSR, 0x00U); /* PERJ: PERJ1=0 */ clrReg8Bits(PERJ, 0x02U); /* DDRJ: DDRJ1=0 */ clrReg8Bits(DDRJ, 0x02U); /* PIEP: PIEP6=0,PIEP1=0 */ clrReg8Bits(PIEP, 0x42U); /* PERP: PERP6=0,PERP1=0 */ clrReg8Bits(PERP, 0x42U); /* PTP: PTP6=0 */ clrReg8Bits(PTP, 0x40U); /* DDRP: DDRP6=1,DDRP1=0 */ clrSetReg8Bits(DDRP, 0x02U, 0x40U); /* DIENADH: DIENADH1=1,DIENADH0=1 */ setReg8Bits(DIENADH, 0x03U); /* PIEADH: PIEADH1=0,PIEADH0=0 */ clrReg8Bits(PIEADH, 0x03U); /* PERADH: PERADH1=0,PERADH0=0 */ clrReg8Bits(PERADH, 0x03U); /* DDRADH: DDRADH1=0,DDRADH0=0 */ clrReg8Bits(DDRADH, 0x03U); /* PERT: PERT7=0 */ clrReg8Bits(PERT, 0x80U); /* DDRT: DDRT7=0 */ clrReg8Bits(DDRT, 0x80U); /* CPMUINT: LOCKIE=0,OSCIE=0 */ clrReg8Bits(CPMUINT, 0x12U); /* CPMULVCTL: LVIE=0 */ clrReg8Bits(CPMULVCTL, 0x02U); /* ECCIE: SBEEIE=0 */ clrReg8Bits(ECCIE, 0x01U); /* ECCDCMD: ECCDRR=0 */ clrReg8Bits(ECCDCMD, 0x80U); /* RDRP: RDRP7=0,RDRP5=0,RDRP3=0,RDRP1=0 */ clrReg8Bits(RDRP, 0xAAU); /* IRQCR: IRQEN=0 */ clrReg8Bits(IRQCR, 0x40U); clrReg8Bits(PTP, 0x88U); /* DDRP: DDRP7=1,DDRP5=0,DDRP3=1 */ clrSetReg8Bits(DDRP, 0x20U, 0x88U); /* PIEP: PIEP5=0,PIEP3=0 */ clrReg8Bits(PIEP, 0x28U); /* PERP: PERP5=0,PERP3=0 */ clrReg8Bits(PERP, 0x28U); /* ### ADC "AD1" init code ... */ AD1_Init(); /* ### BitIO "Bit1" init code ... */ /* ### BitIO "Bit2" init code ... */ /* ### BitIO "Bit3" init code ... */ /* ### BitIO "Bit4" init code ... */ /* ### TimerInt "TI1" init code ... */ /* TIM1TC0: BIT=0x7D00 */ setReg16(TIM1TC0, 0x7D00U); /* Store given value to the compare register */ /* ### BitIO "Bit5" init code ... */ /* ### BitIO "Bit6" init code ... */ /* ### BitIO "Bit7" init code ... */ /* ### BitIO "Bit8" init code ... */ /* ### BitIO "Bit9" init code ... */ /* ### BitIO "Bit10" init code ... */ /* ### BitIO "Bit11" init code ... */ /* ### BitIO "Bit12" init code ... */ /* ### BitIO "Bit13" init code ... */ /* ### BitIO "Bit14" init code ... */ /* ### Programable pulse generation "PWM1" init code ... */ //PWM1_Init(); /* ### WatchDog "WDog1" init code ... */ /* CPMUPROT: ??=0,??=0,??=1,??=0,??=0,??=1,??=1,PROT=0 */ setReg8(CPMUPROT, 0x26U); /* Disable protection of clock-source register */ /* CPMUCLKS: CSAD=1,PCE=0,COPOSCSEL0=0 */ clrSetReg8Bits(CPMUCLKS, 0x05U, 0x20U); /* CPMUPROT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,PROT=0 */ setReg8(CPMUPROT, 0x00U); /* Re-Enable protection of clock-source register */ /* CPMURFLG: COPRF=0 */ setReg8(CPMURFLG, 0x00U); /* Clear COP reset flag */ /* CPMUCOP: WCOP=0,CR2=1,CR1=0,CR0=1 */ clrSetReg8Bits(CPMUCOP, 0x82U, 0x05U); /* Common peripheral initialization - ENABLE */ /* TIM1TSCR1: TEN=1,TSWAI=0,TSFRZ=0,TFFCA=0,PRNT=1,??=0,??=0,??=0 */ setReg8(TIM1TSCR1, 0x88U); AD1_Start(); EnableInterrupts; }