191 lines
7.6 KiB
C
191 lines
7.6 KiB
C
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/*
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* CPU.c
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*
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* Created on: Oct 4, 2016
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* Author: Administrator
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*/
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#include "CPU.h"
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//busʱ<73><CAB1>Ϊ32M<32><4D><EFBFBD>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ64M<34><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ32M
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void CLK_CONFIG(void)
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{
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/*** !!! Here you can place your own code using property "User code before PE initialization" on the build options tab of the CPU compoennt. !!! ***/
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/* ### MC9S12ZVL32_48 "Cpu" init code ... */
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/* PE initialization code after reset */
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/* IVBR: IVB_ADDR=0x7FFF,??=0 */
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setReg16(IVBR, 0xFFFEU);
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/* ECLKCTL: NECLK=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
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setReg8(ECLKCTL, 0x80U);
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/* System clock initialization */
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/* CPMUPROT: ??=0,??=0,??=1,??=0,??=0,??=1,??=1,PROT=0 */
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setReg8(CPMUPROT, 0x26U); /* Disable protection of clock configuration registers */
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/* CPMUCLKS: PSTP=0 */
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clrReg8Bits(CPMUCLKS, 0x40U);
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/* CPMUCLKS: PLLSEL=1 */
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setReg8Bits(CPMUCLKS, 0x80U); /* Enable the PLL to allow write to divider registers */
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/* CPMUPOSTDIV: ??=0,??=0,??=0,POSTDIV4=0,POSTDIV3=0,POSTDIV2=0,POSTDIV1=0,POSTDIV0=0 */
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setReg8(CPMUPOSTDIV, 0x00U); /* Set the post divider register */
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/* Whenever changing PLL reference clock (REFCLK) frequency to a higher value
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it is recommended to write CPMUSYNR = 0x00 in order to stay within specified
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maximum frequency of the MCU */
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/* CPMUSYNR: VCOFRQ1=0,VCOFRQ0=0,SYNDIV5=0,SYNDIV4=0,SYNDIV3=0,SYNDIV2=0,SYNDIV1=0,SYNDIV0=0 */
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setReg8(CPMUSYNR, 0x00U); /* Set the multiplier register */
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/* CPMUPLL: ??=0,??=0,FM1=0,FM0=0,??=0,??=0,??=0,??=0 */
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setReg8(CPMUPLL, 0x00U); /* Set the PLL frequency modulation */
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/* CPMUSYNR: VCOFRQ1=0,VCOFRQ0=1,SYNDIV5=0,SYNDIV4=1,SYNDIV3=1,SYNDIV2=1,SYNDIV1=1,SYNDIV0=1 */
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setReg8(CPMUSYNR, 0x5FU); /* Set the multiplier register */
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while(CPMUIFLG_LOCK == 0U) { /* Wait until the PLL is within the desired tolerance of the target frequency */
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}
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/* CPMUPROT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,PROT=0 */
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setReg8(CPMUPROT, 0x00U); /* Enable protection of clock configuration registers */
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/* CPMUCOP: RSBCK=0,WRTMASK=1 */
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clrSetReg8Bits(CPMUCOP, 0x40U, 0x20U);
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/* CPMUHTCTL: ??=0,??=0,VSEL=0,??=0,HTE=0,HTDS=0,HTIE=0,HTIF=0 */
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setReg8(CPMUHTCTL, 0x00U);
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/* CPMUVREGCTL: ??=0,??=0,??=0,??=0,??=0,??=0,EXTXON=0,INTXON=1 */
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setReg8(CPMUVREGCTL, 0x81U);
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/*** End of PE initialization code after reset ***/
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}
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void Peripheral_Init(void)
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{
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/* Int. priority initialization */
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/* No. Address Pri XGATE Name Description */
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setReg8(INT_CFADDR, 0x28U);
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setReg8(INT_CFDATA3, 0x04U); /* 0x2B 0x00FFFEAC 4 no ivVtim1ch0 used by PE */
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setReg8(INT_CFADDR, 0x60U);
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setReg8(INT_CFDATA1, 0x04U); /* 0x61 0x00FFFF84 4 no ivVadc0conv_compl used by PE */
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setReg8(INT_CFDATA2, 0x04U); /* 0x62 0x00FFFF88 4 no ivVadc0conv_seq_abrt used by PE */
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setReg8(INT_CFDATA3, 0x04U); /* 0x63 0x00FFFF8C 4 no ivVadc0err used by PE */
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/* Common initialization of the CPU registers */
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/* DIENADL: DIENADL7=1,DIENADL6=1,DIENADL5=1,DIENADL4=1,DIENADL3=1,DIENADL2=1 */
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setReg8Bits(DIENADL, 0xFCU);
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/* PIEADL: PIEADL7=0,PIEADL6=0,PIEADL5=0,PIEADL4=0,PIEADL3=0,PIEADL2=0 */
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clrReg8Bits(PIEADL, 0xFCU);
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/* PERADL: PERADL7=0,PERADL6=0,PERADL5=0,PERADL4=0,PERADL3=0,PERADL2=0 */
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clrReg8Bits(PERADL, 0xFCU);
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/* DDRADL: DDRADL7=0,DDRADL6=0,DDRADL5=0,DDRADL4=0,DDRADL3=0,DDRADL2=0 */
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clrReg8Bits(DDRADL, 0xFCU);
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/* TIM1TSCR1: TEN=0,TSWAI=0,TSFRZ=0,TFFCA=0,PRNT=1,??=0,??=0,??=0 */
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setReg8(TIM1TSCR1, 0x08U);
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/* TIM1OCPD: OCPD0=1 */
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setReg8Bits(TIM1OCPD, 0x01U);
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/* TIM1TIOS: IOS0=1 */
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setReg8Bits(TIM1TIOS, 0x01U);
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/* TIM1TCTL2: OM0=0,OL0=0 */
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clrReg8Bits(TIM1TCTL2, 0x03U);
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/* TIM1TTOV: TOV0=0 */
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clrReg8Bits(TIM1TTOV, 0x01U);
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/* TIM1TSCR2: TOI=0 */
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clrReg8Bits(TIM1TSCR2, 0x80U);
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/* TIM1TFLG1: ??=1,??=1,??=1,??=1,??=1,??=1,C1F=1,C0F=1 */
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setReg8(TIM1TFLG1, 0xFFU);
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/* TIM1TIE: C0I=1 */
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setReg8Bits(TIM1TIE, 0x01U);
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/* TIM1PTPSR: PTPS7=0,PTPS6=0,PTPS5=0,PTPS4=0,PTPS3=0,PTPS2=0,PTPS1=0,PTPS0=0 */
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setReg8(TIM1PTPSR, 0x00U);
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/* PERJ: PERJ1=0 */
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clrReg8Bits(PERJ, 0x02U);
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/* DDRJ: DDRJ1=0 */
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clrReg8Bits(DDRJ, 0x02U);
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/* PIEP: PIEP6=0,PIEP1=0 */
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clrReg8Bits(PIEP, 0x42U);
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/* PERP: PERP6=0,PERP1=0 */
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clrReg8Bits(PERP, 0x42U);
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/* PTP: PTP6=0 */
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clrReg8Bits(PTP, 0x40U);
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/* DDRP: DDRP6=1,DDRP1=0 */
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clrSetReg8Bits(DDRP, 0x02U, 0x40U);
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/* DIENADH: DIENADH1=1,DIENADH0=1 */
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setReg8Bits(DIENADH, 0x03U);
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/* PIEADH: PIEADH1=0,PIEADH0=0 */
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clrReg8Bits(PIEADH, 0x03U);
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/* PERADH: PERADH1=0,PERADH0=0 */
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clrReg8Bits(PERADH, 0x03U);
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/* DDRADH: DDRADH1=0,DDRADH0=0 */
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clrReg8Bits(DDRADH, 0x03U);
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/* PERT: PERT7=0 */
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clrReg8Bits(PERT, 0x80U);
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/* DDRT: DDRT7=0 */
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clrReg8Bits(DDRT, 0x80U);
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/* CPMUINT: LOCKIE=0,OSCIE=0 */
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clrReg8Bits(CPMUINT, 0x12U);
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/* CPMULVCTL: LVIE=0 */
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clrReg8Bits(CPMULVCTL, 0x02U);
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/* ECCIE: SBEEIE=0 */
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clrReg8Bits(ECCIE, 0x01U);
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/* ECCDCMD: ECCDRR=0 */
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clrReg8Bits(ECCDCMD, 0x80U);
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/* RDRP: RDRP7=0,RDRP5=0,RDRP3=0,RDRP1=0 */
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clrReg8Bits(RDRP, 0xAAU);
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/* IRQCR: IRQEN=0 */
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clrReg8Bits(IRQCR, 0x40U);
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clrReg8Bits(PTP, 0x88U);
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/* DDRP: DDRP7=1,DDRP5=0,DDRP3=1 */
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clrSetReg8Bits(DDRP, 0x20U, 0x88U);
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/* PIEP: PIEP5=0,PIEP3=0 */
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clrReg8Bits(PIEP, 0x28U);
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/* PERP: PERP5=0,PERP3=0 */
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clrReg8Bits(PERP, 0x28U);
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/* ### ADC "AD1" init code ... */
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AD1_Init();
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/* ### BitIO "Bit1" init code ... */
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/* ### BitIO "Bit2" init code ... */
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/* ### BitIO "Bit3" init code ... */
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/* ### BitIO "Bit4" init code ... */
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/* ### TimerInt "TI1" init code ... */
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/* TIM1TC0: BIT=0x7D00 */
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setReg16(TIM1TC0, 0x7D00U); /* Store given value to the compare register */
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/* ### BitIO "Bit5" init code ... */
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/* ### BitIO "Bit6" init code ... */
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/* ### BitIO "Bit7" init code ... */
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/* ### BitIO "Bit8" init code ... */
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/* ### BitIO "Bit9" init code ... */
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/* ### BitIO "Bit10" init code ... */
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/* ### BitIO "Bit11" init code ... */
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/* ### BitIO "Bit12" init code ... */
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/* ### BitIO "Bit13" init code ... */
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/* ### BitIO "Bit14" init code ... */
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/* ### Programable pulse generation "PWM1" init code ... */
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//PWM1_Init();
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/* ### WatchDog "WDog1" init code ... */
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/* CPMUPROT: ??=0,??=0,??=1,??=0,??=0,??=1,??=1,PROT=0 */
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setReg8(CPMUPROT, 0x26U); /* Disable protection of clock-source register */
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/* CPMUCLKS: CSAD=1,PCE=0,COPOSCSEL0=0 */
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clrSetReg8Bits(CPMUCLKS, 0x05U, 0x20U);
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/* CPMUPROT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,PROT=0 */
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setReg8(CPMUPROT, 0x00U); /* Re-Enable protection of clock-source register */
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/* CPMURFLG: COPRF=0 */
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setReg8(CPMURFLG, 0x00U); /* Clear COP reset flag */
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/* CPMUCOP: WCOP=0,CR2=1,CR1=0,CR0=1 */
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clrSetReg8Bits(CPMUCOP, 0x82U, 0x05U);
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/* Common peripheral initialization - ENABLE */
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/* TIM1TSCR1: TEN=1,TSWAI=0,TSFRZ=0,TFFCA=0,PRNT=1,??=0,??=0,??=0 */
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setReg8(TIM1TSCR1, 0x88U);
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AD1_Start();
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EnableInterrupts;
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}
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