2023-11-18 11:46:58 +08:00
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/***********************************************************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
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* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
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* applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
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* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
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* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
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* of this software. By using this software, you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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*
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* Copyright (C) 2012, 2021 Renesas Electronics Corporation. All rights reserved.
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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* File Name : r_cg_cgc.h
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* Version : CodeGenerator for RL78/F13 V2.03.07.02 [08 Nov 2021]
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2023-11-26 11:43:55 +08:00
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* Device(s) : R5F10AGF
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2023-11-18 11:46:58 +08:00
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* Tool-Chain : CCRL
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* Description : This file implements device driver for CGC module.
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2023-11-26 11:43:55 +08:00
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* Creation Date: 2023-11-24
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2023-11-18 11:46:58 +08:00
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***********************************************************************************************************************/
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#ifndef CGC_H
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#define CGC_H
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/***********************************************************************************************************************
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Macro definitions (Register bit)
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***********************************************************************************************************************/
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/*
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Clock operation mode control register (CMC)
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*/
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/* High-speed system clock pin operation mode (EXCLK, OSCSEL) */
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#define _C0_CGC_HISYS_PIN (0xC0U)
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#define _00_CGC_HISYS_PORT (0x00U) /* X1, X2 as I/O port */
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#define _40_CGC_HISYS_OSC (0x40U) /* X1, X2 as crystal/ceramic resonator connection */
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#define _80_CGC_HISYS_PORT1 (0x80U) /* X1, X2 as I/O port */
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#define _C0_CGC_HISYS_EXT (0xC0U) /* X1 as I/O port, X2 as external clock input */
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/* Subsystem clock pin operation mode (EXCLKS, OSCSELS) */
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#define _30_CGC_SUB_PIN (0x30U)
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#define _00_CGC_SUB_PORT (0x00U) /* XT1, XT2 as I/O port */
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#define _10_CGC_SUB_OSC (0x10U) /* XT1, XT2 as crystal connection */
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#define _20_CGC_SUB_PORT1 (0x20U) /* XT1, XT2 as I/O port */
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#define _30_CGC_SUB_EXT (0x30U) /* XT1 as I/O port, XT2 as external clock input */
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/* XT1 oscillator oscillation mode selection (AMPHS1, AMPHS0) */
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#define _00_CGC_SUBMODE_DEFAULT (0x00U)
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#define _00_CGC_SUBMODE_LOW (0x00U) /* low power consumption oscillation */
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#define _02_CGC_SUBMODE_NORMAL (0x02U) /* normal oscillation */
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#define _04_CGC_SUBMODE_ULOW (0x04U) /* ultra-low power consumption oscillation */
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/* Control of X1 high-speed system clock oscillation frequency (AMPH) */
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#define _00_CGC_SYSOSC_DEFAULT (0x00U)
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#define _00_CGC_SYSOSC_UNDER10M (0x00U) /* fX <= 10MHz */
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#define _01_CGC_SYSOSC_OVER10M (0x01U) /* fX > 10MHz */
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/*
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Clock operation status control register (CSC)
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*/
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/* Control of high-speed system clock operation (MSTOP) */
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#define _00_CGC_HISYS_OPER (0x00U) /* X1 oscillator/external clock operating */
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#define _80_CGC_HISYS_STOP (0x80U) /* X1 oscillator/external clock stopped */
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/* Subsystem clock operation (XTSTOP) */
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#define _00_CGC_SUB_OPER (0x00U) /* XT1 oscillator operating */
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#define _40_CGC_SUB_STOP (0x40U) /* XT1 oscillator stopped */
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/* High-speed OCO operation (HIOSTOP) */
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#define _00_CGC_HIO_OPER (0x00U) /* high-speed OCO operating */
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#define _01_CGC_HIO_STOP (0x01U) /* high-speed OCO stopped */
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/*
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Oscillation stabilization time counter status register (OSTC)
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*/
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/* Oscillation stabilization time status (MOST18 - MOST8) */
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#define _00_CGC_OSCSTAB_STA0 (0x00U) /* < 2^8/fX */
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#define _80_CGC_OSCSTAB_STA8 (0x80U) /* 2^8/fX */
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#define _C0_CGC_OSCSTAB_STA9 (0xC0U) /* 2^9/fX */
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#define _E0_CGC_OSCSTAB_STA10 (0xE0U) /* 2^10/fX */
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#define _F0_CGC_OSCSTAB_STA11 (0xF0U) /* 2^11/fX */
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#define _F8_CGC_OSCSTAB_STA13 (0xF8U) /* 2^13/fX */
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#define _FC_CGC_OSCSTAB_STA15 (0xFCU) /* 2^15/fX */
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#define _FE_CGC_OSCSTAB_STA17 (0xFEU) /* 2^17/fX */
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#define _FF_CGC_OSCSTAB_STA18 (0xFFU) /* 2^18/fX */
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/*
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Oscillation stabilization time select register (OSTS)
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*/
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/* Oscillation stabilization time selection (OSTS2 - OSTS0) */
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#define _00_CGC_OSCSTAB_SEL8 (0x00U) /* 2^8/fX */
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#define _01_CGC_OSCSTAB_SEL9 (0x01U) /* 2^9/fX */
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#define _02_CGC_OSCSTAB_SEL10 (0x02U) /* 2^10/fX */
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#define _03_CGC_OSCSTAB_SEL11 (0x03U) /* 2^11/fX */
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#define _04_CGC_OSCSTAB_SEL13 (0x04U) /* 2^13/fX */
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#define _05_CGC_OSCSTAB_SEL15 (0x05U) /* 2^15/fX */
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#define _06_CGC_OSCSTAB_SEL17 (0x06U) /* 2^17/fX */
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#define _07_CGC_OSCSTAB_SEL18 (0x07U) /* 2^18/fX */
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/*
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PLL control register (PLLCTL)
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*/
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/* Lockup wait counter setting value */
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#define _00_CGC_LOCKUP_WAIT_7 (0x00U) /* 2^7/fMAIN */
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#define _40_CGC_LOCKUP_WAIT_8 (0x40U) /* 2^8/fMAIN */
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#define _80_CGC_LOCKUP_WAIT_9 (0x80U) /* 2^9/fMAIN */
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/* PLL output clock selection (PLLDIV1) */
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#define _00_CGC_PLL_BELOW_32MHZ (0x00U) /* when fMAIN <= 32 MHz */
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#define _20_CGC_PLL_ABOVE_32MHZ (0x20U) /* when fMAIN > 32 MHz */
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/* PLL output clock division selection (PLLDIV0) */
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#define _00_CGC_PLL_DIVISION_2 (0x00U) /* divides the clock frequency by 2 */
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#define _10_CGC_PLL_DIVISION_4 (0x10U) /* divides the clock frequency by 4 */
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/* Clock mode selection (SELPLL) */
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#define _00_CGC_NOSEL_PLL (0x00U) /* clock through mode */
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#define _04_CGC_SEL_PLL (0x04U) /* PLL clock select mode */
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/* PLL output clock (fPLLO) multiplier selection (PLLMUL) */
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#define _00_CGC_PLL_MULTIPLY_X12 (0x00U) /* clock through mode */
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#define _02_CGC_PLL_MULTIPLY_X16 (0x02U) /* PLL clock select mode */
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/* Operating or stopping PLL function (PLLON) */
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#define _00_CGC_PLL_STOP (0x00U) /* PLL operating stopped */
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#define _01_CGC_PLL_ENABLE (0x01U) /* PLL operating */
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/*
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PLL status register (PLLSTS)
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*/
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/* PLL lock state */
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#define _00_CGC_PLL_UNLOCKED (0x00U) /* Unlocked state */
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#define _80_CGC_PLL_LOCKED (0x80U) /* Locked state */
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/*
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FMP clock selection division register (MDIV)
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*/
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/* Division of PLL clock (fMP) */
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#define _00_CGC_FMP_DIV_DEFAULT (0x00U) /* fMP (default) */
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#define _01_CGC_FMP_DIV_1 (0x01U) /* fMP/2^1 */
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#define _02_CGC_FMP_DIV_2 (0x02U) /* fMP/2^2 */
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#define _03_CGC_FMP_DIV_3 (0x03U) /* fMP/2^3 */
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#define _04_CGC_FMP_DIV_4 (0x04U) /* fMP/2^4 */
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#define _05_CGC_FMP_DIV_5 (0x05U) /* fMP/2^5 */
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#define _06_CGC_FMP_DIV_6 (0x06U) /* fMP/2^6 */
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/*
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System clock control register (CKC)
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*/
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/* Status of CPU/peripheral hardware clock fCLK (CLS) */
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#define _00_CGC_CPUCLK_MAIN (0x00U) /* main system clock (fMAIN) */
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#define _80_CGC_CPUCLK_SUB (0x80U) /* subsystem clock (fSUB) */
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/* Selection of CPU/peripheral hardware clock fCLK (CSS) */
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#define _00_CGC_CPUCLK_SELMAIN (0x00U) /* main system clock (fMAIN) */
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#define _40_CGC_CPUCLK_SELSUB (0x40U) /* subsystem clock (fSUB) */
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/* Status of Main system clock fMAIN (MCS) */
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#define _00_CGC_MAINCLK_HIO (0x00U) /* high-speed OCO clock (fIH) */
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#define _20_CGC_MAINCLK_HISYS (0x20U) /* high-speed system clock (fMX) */
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/* Selection of Main system clock fMAIN (MCM0) */
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#define _00_CGC_MAINCLK_SELHIO (0x00U) /* high-speed OCO clock (fIH) */
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#define _10_CGC_MAINCLK_SELHISYS (0x10U) /* high-speed system clock (fMX) */
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/*
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Operation speed mode control register (OSMC)
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*/
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/* Setting in subsystem clock HALT mode (RTCLPC) */
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#define _00_CGC_SUBINHALT_ON (0x00U) /* enables supply of subsystem clock to peripheral functions */
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#define _80_CGC_SUBINHALT_OFF (0x80U) /* stops supply to peripheral functions other than RTC and interval timer */
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/* RTC macro operation clock (WUTMMCK0) */
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#define _00_CGC_RTC_CLK_OTHER (0x00U) /* Other than fIL */
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#define _10_CGC_RTC_CLK_FIL (0x10U) /* use fIL clock */
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/*
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Illegal memory access detection control register (IAWCTL)
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*/
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/* Illegal memory access detection control (IAWEN) */
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#define _00_CGC_ILLEGAL_ACCESS_OFF (0x00U) /* disables illegal memory access detection */
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#define _80_CGC_ILLEGAL_ACCESS_ON (0x80U) /* enables illegal memory access detection */
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/* RAM guard area (GRAM1, GRAM0) */
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#define _00_CGC_RAM_GUARD_OFF (0x00U) /* invalid, it is possible to write RAM */
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#define _10_CGC_RAM_GUARD_AREA0 (0x10U) /* 128 bytes from RAM bottom address */
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#define _20_CGC_RAM_GUARD_AREA1 (0x20U) /* 256 bytes from RAM bottom address */
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#define _30_CGC_RAM_GUARD_AREA2 (0x30U) /* 512 bytes from RAM bottom address */
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/* PORT register guard (GPORT) */
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#define _00_CGC_PORT_GUARD_OFF (0x00U) /* invalid, it is possible to write PORT register */
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#define _04_CGC_PORT_GUARD_ON (0x04U) /* valid, it is impossible to write PORT register, but possible for read */
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/* Interrupt register guard (GINT) */
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#define _00_CGC_INT_GUARD_OFF (0x00U) /* invalid, it is possible to write interrupt register */
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#define _02_CGC_INT_GUARD_ON (0x02U) /* valid, it is impossible to write , but possible for read */
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/* CSC register guard (GCSC) */
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#define _00_CGC_CSC_GUARD_OFF (0x00U) /* invalid, it is possible to write CSC register */
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#define _01_CGC_CSC_GUARD_ON (0x01U) /* valid, it is impossible to write CSC register, but possible for read */
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/*
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RTC clock selection register (RTCCL)
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*/
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/* Operation clock source selection for RTC (RTCCL7) */
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#define _00_CGC_RTC_FMX (0x00U) /* RTC uses External Main clock (fMX) */
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#define _80_CGC_RTC_FIH (0x80U) /* RTC uses Internal high speed clock (fIH) */
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/* Operation selection of RTC macro (RTCCL6,RTCCKS1 - RTCCKS0) */
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#define _00_CGC_RTC_FSUB (0x00U) /* RTC uses sub clock */
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#define _02_CGC_RTC_DIV128 (0x02U) /* RTC uses high-speed clock / 128 */
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#define _03_CGC_RTC_DIV256 (0x03U) /* RTC uses high-speed clock / 256 */
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#define _42_CGC_RTC_DIV122 (0x42U) /* RTC uses high-speed clock / 122 */
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#define _43_CGC_RTC_DIV244 (0x43U) /* RTC uses high-speed clock / 244 */
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/***********************************************************************************************************************
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Macro definitions
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***********************************************************************************************************************/
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/***********************************************************************************************************************
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Typedef definitions
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***********************************************************************************************************************/
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typedef enum
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{
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HIOCLK,
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SYSX1CLK,
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SYSEXTCLK,
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SUBXT1CLK,
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SUBEXTCLK
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} clock_mode_t;
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/***********************************************************************************************************************
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Global functions
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***********************************************************************************************************************/
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void R_CGC_Create(void);
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/* Start user code for function. Do not edit comment generated here */
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/* End user code. Do not edit comment generated here */
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#endif
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